Version 0.12 June 7, 2026

We released a new schedule version!

We have new sessions!

• “UnifiedDB : Status and Plans for Fast and Rigorous RISC-V Development” by Derek Hower, Paul Clarke
• “From Architecture to GDS: Introducing the X200, a Market-Ready, High-Performance RISC-V Core” by feixiaolong
• “A RISC-V Dual-Core Microcontroller Architecture for Flight Control OSD: A Single-Chip Implementation” by Yong Yang
• “NoC and Memory Subsystems for AI Employing RISC-V Processors with Vector or Matrix Extensions” by Ashley Stevens
• “A RISC-V based Coarse-Grained Reconfigurable Architecture to Unify Signal and AI Processing” by Christian Siemers

Version 0.11 June 6, 2026

We released a new schedule version!

We have a new session: “VASCO: ASIC Test Platform for Hardware Security on FD-SOI” by Stefano Di Matteo.

Version 0.10 June 5, 2026

We released a new schedule version!

We have a new session: “The Practical Security Rules Proposal to HW RoT in Security Requirement RISC-V Server Specification” by Vincent Cui.

Version 0.9 June 5, 2026

We released a new schedule version!

We have a new session: “Epic Contrail AIX for RISC-V Developers” by Chloe Jian Ma.

Version 0.8 June 5, 2026

We released a new schedule version!

Version 0.7 June 5, 2026

We released a new schedule version!

Version 0.6 June 5, 2026

We released a new schedule version!

We have a new session: “Accelerating the Future Computing with RISC-V” by Li Chenxi.

Version 0.5 June 5, 2026

We released a new schedule version!

We have new sessions!

• “Welcome to the RISC-V Summit Europe 2026!” by Teresa Cervero, Nick Kossifidis, Andrea Bartolini
• “Farewell and closing remarks” by Teresa Cervero, Nick Kossifidis, Andrea Bartolini
• “Lightning Round” by RVI

We had to move some sessions, so if you were planning on seeing them, check their new dates or locations:

• “Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform” by Manolis Marazakis (June 10, 2026, 11 a.m. → June 10, 2026, 10:50 a.m.)
• “The ISOLDE Space Demonstrator: a RISC-V Ecosystem for Low-Power On-board Inference” by Emanuele Valpreda, Davide Di Ienno, Mattia Paladino (June 10, 2026, 10:50 a.m. → June 10, 2026, 10:40 a.m.)
• “A Doom Demo Journey: Tenstorrent's Ascalon CPU on Synopsys emulation and prototyping systems” by Rae Parnmukh, Dongjie Xie, Brandon Zupan (June 10, 2026, 10:30 a.m., Poster Island C → June 11, 2026, 1:20 p.m., Poster Island D)
• “Vitamin-V: Results and Lessons Learnt” by Ramon Canal, Stefano Di Carlo, Dimitris Gizopoulos (June 10, 2026, 11:20 a.m. → June 10, 2026, 11:10 a.m.)
• “Monte Cimone v3: Where RISC-V Stands in High-Performance Computing” by Emanuele Venieri (June 10, 2026, 11:10 a.m. → June 10, 2026, 11 a.m.)
• “From Open Architecture to Open Silicon: Taping out CORE-ET Many-Core RISC-V Platform” by Tanya Dadasheva, Roman Shaposhnik (June 10, 2026, 10:40 a.m. → June 10, 2026, 10:30 a.m.)

Version 0.4 June 4, 2026

We released a new schedule version!

We have new sessions!

• “Utilizing the RISC V Architecture to Accelerate Real Time Motor Control Applications” by Sean Murphy
• “DiffTest-H: FPGA-Accelerated RISC-V Co-simulation Verification Beyond 10 MHz” by XU AN, Yinan Xu
• “Nuclei RISC-V Automotive Solutions: ASIL-D Safety & Full-Spectrum IP for Next-Gen Vehicles” by Jianying Peng
• “Albania is an AI-Factory” by Kushtrim Shala
• “No Fab Required: Monetizing RISC-V Designs in the Cloud” by Jeremy Dahan
• “SoCMake: Modular RISC-V SoCs for Radiation-Harsh and Safety-Critical Environments” by Benoît Denkinger
• “Control your core. Own your future” by Troy Jones
• ““PRG32: Teaching RISC-V Through Playable Game Cartridges"” by Raffele Montella
• “AIA, IOMMU and Other Flash Points: Driving RISC-V Sub-System Verification” by Adnan Hamid
• “PQCUARK: A Scalar RISC-V ISA Extension for ML-KEM and ML-DSA” by Xavier Carril Gil
• “High performance RISC-V Image Processing Chip EAI8800” by Changqing Li

We had to move some sessions, so if you were planning on seeing them, check their new dates or locations:

• “An Embedded RISC-V Vector Extension for Edge-Oriented Acceleration” by Iñigo Díez de Ulzurrun (June 11, 2026, 11:20 a.m., Poster Island A → June 9, 2026, 4 p.m., Poster Island C)
• “Code size reduction by advanced near addressing modes” by Kajetan Nürnberger (Poster Island C → Poster Island D)

Version 0.3 June 1, 2026

We released a new schedule version!

We have new sessions!

• “Realising the Future of European Computing from Research to Industry” by TBD
• “Delivering the Future of Software Enablement for RISC-V” by TBD
• “It's a RISC-V World: Innovation, Collaboration, Competition, and Deployment on a Global Stage” by TBD

Version 0.2 June 1, 2026

We released a new schedule version!

We have new sessions!

• “RISC-V for the Planet: Open-Source Microprocessors in the Internet of Trees” by Marcelo Zuffo
• “Beyond Privilege: The RISC‑V Isolation Toolbox from Microcontrollers to Confidential Computing” by Andrew dellow
• “ARBEL™ The Leading Server-Class RISC-V CPU” by Yiftach Gilad
• “HBENCH: RISC-V Microbenchmark Suite” by Victor Asanza, Carlos Rojas Morales, Erick Brandon Cureño Contreras
• “Tailoring Workloads for Agentic AI Using Advanced Virtual Platforms for RISC-V” by Sam Grove
• “Transforming MCUs in an AI-Defined Era” by Edward Wilford
• “From Eyewear to Silicon: RISC-V for Low-Power AI in Next-Generation Smart Glasses” by Marco Fariselli
• “Shield-XS: A Lightweight Dynamic Security Isolation for RISC-V” by yuanmiaomiao
• “XiangShan Practice: The Path to Industrial Deployment of Open-Source High-Performance RISC-V Processor” by YUNGANG BAO
• “Loop Optimization Practices for RISC-V” by Lei Qiu, Lulin Wang, Yingying Wang
• “RISC-V Innovation at Scale” by Andrea Gallo
• “CHERI for RISC‑V: From Academic Breakthrough to Industry-Scale Ecosystem Adoption” by Mike EFTIMAKIS
• “RISC-V Architecture innovations need software stack innovations” by Henri-Pierre CHARLES, Quentin MÉLOTTE
• “RISC-V State of the Union” by Krste Asanović
• “Let's shift the mindset” by Giordano Mancini
• “Nuclei: Full-Spectrum RISC-V IP & Automated SoC Design from Months to Hours” by Bob Hu
• “Machine Learning-Based Performance Estimation for RISC-V Virtual Prototypes” by Caaliph Andriamisaina
• “InterFinder: A Framework for Memory Interference Analysis in RISC-V Vectors” by Oumaima Matoussi
• “RISC-V: Enabling Open Physical AI” by Luca Benini
• “RISC-V Based SoC for Event-Based Sparse Convolutions” by Diego Gigena Ivanovich
• “Developing an Open Agentic SoC” by Tanya Dadasheva
• “RISC-V Server Platform 1.0: One Spec to Boot Them All” by Radim Krčmář
• “CHERI-VP: Evaluating CHERI Early for Embedded RISC-V Systems with Virtual Prototypes” by Spandan Das
• “High-performance code generation for early and future RISC-V vector systems” by Alexandre de Limas Santana
• “Linux on RISC-V: Learning from the Mistakes of History” by Greg Kroah-Hartman
• “Matrix Extensions for RISC-V: Delivering on the Promise” by Dr. Philipp Tomsich
• “RISCVML: Teaching RISC-V Embedded ML with Rust — From ESP32-C3 to ESP32-P4” by Scottie_von_Bruchhausen
• “Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs” by Philippe Sauter
• “HyperCroc: Open-Source RISC-V MCU with Plug-In Interface for Domain-Specific Accelerators” by Philippe Sauter
• “XSCC: A High-Performance Compiler for RISC-V” by Lei Qiu, Lulin Wang, Kangda Hao
• “RISC‑V at Scale: From Embedded Dominance to Application Processor Opportunities” by John Holland

We had to move some sessions, so if you were planning on seeing them, check their new dates or locations:

• “REPTILES: Repeated tiles of Sargantana” by Lluc Alvarez, Serik Perez Gomez, Arnau Bigas Soldevila (June 9, 2026, 2 p.m. → June 11, 2026, 10:30 a.m.)
• “CREATOR: A RISC-V web simulator based on Sail specification language” by Juan Carlos Cano Resa (June 9, 2026, 3:40 p.m. → June 9, 2026, 3:30 p.m.)
• “Rust on RISC-V: Alignment and Friction at the Hardware-Software Boundary” by David de Rosier (June 9, 2026, 2:20 p.m. → June 9, 2026, 3:50 p.m.)
• “FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor Tomasulo-Style” by Roberto Giorgi (June 9, 2026, 3:50 p.m. → June 9, 2026, 3:40 p.m.)
• “Functional Verification Strategy for a CVA6 MMU” by Tanuj Khandelwal (June 10, 2026, 11:10 a.m., Poster Island A → June 11, 2026, 1:40 p.m., Poster Island C)
• “Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V Cores” by Ihsane Tahir (June 10, 2026, 11:20 a.m. → June 10, 2026, 11:10 a.m.)
• “A Proof-of-Concept RISC-V with 128-bit Extension” by Frédéric Pétrot (June 10, 2026, 5:30 p.m. → June 11, 2026, 4:30 p.m.)
• “RVV Tips & Tricks” by Olaf Bernstein (June 9, 2026, 10:30 a.m. → June 9, 2026, 10:40 a.m.)
• “Hardware Acceleration Island for Safety-Critical Applications based on RISC-V” by Luis Waucquez (June 11, 2026, 10:30 a.m. → June 9, 2026, 2 p.m.)
• “Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System” by Dave Cremins (June 11, 2026, 4:30 p.m. → June 10, 2026, 5:30 p.m.)

Version 0.1 May 19, 2026

We released our first schedule!