{"$schema": "https://c3voc.de/schedule/schema.json", "generator": {"name": "pretalx", "version": "2025.2.2"}, "schedule": {"url": "https://cfp.riscv-europe.org/eu-summit-2026/schedule/", "version": "0.1", "base_url": "https://cfp.riscv-europe.org", "conference": {"acronym": "eu-summit-2026", "title": "RISC-V Summit Europe 2026", "start": "2026-06-08", "end": "2026-06-12", "daysCount": 5, "timeslot_duration": "00:05", "time_zone_name": "Europe/Rome", "colors": {"primary": "#003262"}, "rooms": [{"name": "Avorio A - Linux Kernel", "slug": "11-avorio-a-linux-kernel", "guid": "110a7e92-034e-597f-97c9-0ed4e2ed8dc7", "description": null, "capacity": null}, {"name": "Avorio B -TWG1", "slug": "8-avorio-b-twg1", "guid": "031e852b-1ad9-5b0c-9a89-1f015ca4ea43", "description": null, "capacity": null}, {"name": "Bianca A - TWG2", "slug": "9-bianca-a-twg2", "guid": "cebfd69f-5794-5a28-bfa3-7df518344a76", "description": null, "capacity": null}, {"name": "Bianca B - TWG3", "slug": "10-bianca-b-twg3", "guid": "cad89c4d-0055-5702-852d-b8d3c6a521ac", "description": null, "capacity": null}, {"name": "Italia - Intro to RISC-V", "slug": "12-italia-intro-to-risc-v", "guid": "76b432b0-7dc8-5af3-9fe8-3e2f76f4648d", "description": null, "capacity": null}, {"name": "Devroom - A.I.", "slug": "13-devroom-ai", "guid": "7e642aa7-1303-5e81-baa0-5524e264e5a2", "description": null, "capacity": null}, {"name": "Devroom - Automotive", "slug": "14-devroom-automotive", "guid": "3847f6a9-e7f8-5f41-b43a-19c6e530b17b", "description": null, "capacity": null}, {"name": "Plenary", "slug": "15-plenary", "guid": "29dc7a70-3428-5415-86ea-72e32649f4bd", "description": null, "capacity": 1000}, {"name": "Poster Island A", "slug": "16-poster-island-a", "guid": "7a9ba8f4-80cf-51cb-846a-bde6423c3198", "description": null, "capacity": null}, {"name": "Poster Island B", "slug": "17-poster-island-b", "guid": "68c12ba7-0646-5445-80b9-72eaa4b49330", "description": null, "capacity": null}, {"name": "Poster Island C", "slug": "18-poster-island-c", "guid": "b4acc14f-d67e-5134-9612-e23b6a7f1f98", "description": null, "capacity": null}, {"name": "Poster Island D", "slug": "19-poster-island-d", "guid": "1bd26697-ccc1-5884-999f-76aeabf6b3d5", "description": null, "capacity": null}, {"name": "Devzone", "slug": "22-devzone", "guid": "729fe554-9c7f-56c1-a8e6-2599d8ff6933", "description": null, "capacity": null}], "tracks": [{"name": "Blind Submission (Default)", "slug": "4-blind-submission-default", "color": "#0a6b7c"}, {"name": "Non-Blind submission", "slug": "5-non-blind-submission", "color": "#60269e"}, {"name": "Demos", "slug": "6-demos", "color": "#5d033a"}, {"name": "Keynotes", "slug": "7-keynotes", "color": "#23a5c5"}, {"name": "Demo Theater", "slug": "8-demo-theater", "color": "#4c1fd2"}], "days": [{"index": 1, "date": "2026-06-08", "day_start": "2026-06-08T04:00:00+02:00", "day_end": "2026-06-09T03:59:00+02:00", "rooms": {}}, {"index": 2, "date": "2026-06-09", "day_start": "2026-06-09T04:00:00+02:00", "day_end": "2026-06-10T03:59:00+02:00", "rooms": {"Plenary": [{"guid": "c1477e86-683d-5198-9bb4-530800572197", "code": "B7EASJ", "id": 176, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/B7EASJ/RVA23_Mandatory_Extension_-_L_LbpTgGw.webp", "date": "2026-06-09T12:00:00+02:00", "start": "12:00", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-176-rva23-profile-support-in-linux-kernel-from-extension-definitions-to-userspace-export", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B7EASJ/", "title": "RVA23 Profile Support in Linux Kernel: From Extension Definitions to Userspace Export", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "The RVA23 profile, ratified in October 2024, defines a mandatory baseline of 33 U-mode and 25 S-mode extensions. During the upstream enablement of SpacemiT K3, I identified gaps in the kernel's RVA23 extension coverage and submitted patches to address them. After several revision cycles, the patches were merged into Linux v7.0, raising coverage from 69% to 100%.\r\n\r\nThis talk will examine how the Linux kernel community approaches RISC-V extension support - the design principles behind accepting new extensions into the kernel, and how the maintainers manage the growing complexity of the RISC-V extension landscape.\r\n\r\nI will then present two patchsets currently under review for Linux v7.1: my series adding cpufeature parsing and hwprobe export for RVA23 extensions, and Andrew Jones' (Qualcomm) RFC introducing rva23u64 base behavior detection. I will discuss the key architectural decisions in these patches, the review feedback received, and the current status.\r\n\r\nDepending on the upstream timeline, these may already be merged by the Summit, or still in progress - either way, the talk will reflect the latest state of the kernel community's work.\r\n\r\nAchieving complete RVA23 support in mainline Linux is a prerequisite for distributions to ship generic RISC-V images that work across compliant hardware, reducing fragmentation. We hope to invite RISC-V kernel community members at the Summit for an open discussion on remaining challenges and future profile evolution.", "description": "By sharing the technical considerations and review discussions from the kernel community, this talk aims to:\r\n1)  help community and SoC vendors better understand what is expected when bringing RVA23-compliant hardware to mainline Linux.\r\n\r\n2) It also provides feedback to the RISC-V profile specification process on how profile definitions interact with kernel design constraints. (that's a more ambitious goal).\r\n\r\nMy target audience include: Linux kernel and boot firmware developers working on RISC-V architecture support, SoC vendors planning RVA23-compliant products, distribution (such as Debian, Fedora) maintainers interested in generic RISC-V image support, and RISC-V profile specification contributors.", "recording_license": "", "do_not_record": false, "persons": [{"code": "AX7YYX", "name": "Guodong Xu", "avatar": "https://cfp.riscv-europe.org/media/avatars/AX7YYX_hZwwgsp.webp", "biography": "Guodong Xu is Director of Software Engineering at RISCstar Solutions, with over 20 years of Linux kernel development experience. Previously at Motorola (Mobile phone low-level software) and Linaro (Sr. Tech Lead 10+ years), he now focuses on RISC-V upstream kernel enablement and BSP development. He is an active contributor to the mainline Linux kernel for RISC-V, including SpacemiT K1/K3 SoC support and RVA23 profile extensions.", "public_name": "Guodong Xu", "guid": "de3a80b6-ec4c-5699-8eed-7ed8e261195e", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AX7YYX/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B7EASJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B7EASJ/", "attachments": []}, {"guid": "8f509eff-2a2e-5783-a743-6927c7a90cd0", "code": "KMNP8Q", "id": 363, "logo": null, "date": "2026-06-09T12:15:00+02:00", "start": "12:15", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-363-the-rise-project-advancing-the-risc-v-software-ecosystem", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KMNP8Q/", "title": "The RISE Project: Advancing the RISC-V Software Ecosystem", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "The RISC-V Software Ecosystem (RISE) Project is a Linux Foundation Europe initiative where hardware, software and services companies collaborate to bridge the gap between architectural potential and commercial software readiness. While the RISC-V community is highly impactful, industrial-grade software often requires an extra push. RISE provides this through direct engineering, an RFP process that has already deployed over \u20ac1M in contracts, and individual support through the RISE Developer Appreciation Program.\r\n\r\nThis session highlights how RISE is accelerating RISC-V adoption within key upstream open-source projects. We will detail our strategic push to enable AI/ML workloads through targeted investments in PyTorch, Llama.cpp, IREE, oneDNN, and OpenBLAS. We\u2019ll demonstrate how RISE is lowering the barrier to entry by providing free GitHub and GitLab runners for riscv64, alongside self-service remote hardware access via the RISE Board Farm. Finally, we will share our long-term roadmap for ecosystem performance and stability, focusing on LLVM auto-vectorization for RVV at scale and the RISE Build Farm\u2019s role in proactive bug detection across kernel, toolchain and system libraries.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "VXWRAQ", "name": "Nathan Egge", "avatar": null, "biography": "Nathan Egge is a Staff Software Engineer at Google working on the native tools and libraries used to build AOSP and Android applications, including the C/C++ and Rust toolchains. He serves as co-chair of the Technical Steering Committee in RISE and previously as the chair of the System Libraries WG. Nathan received the RISC-V Board of Directors Software Leadership award in 2024 for contributions to RISC-V industry adoption.", "public_name": "Nathan Egge", "guid": "b7d5b32b-318d-529f-93e4-871add0fa991", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VXWRAQ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KMNP8Q/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KMNP8Q/", "attachments": []}, {"guid": "3482c861-f0a1-57ec-88e9-f34444395246", "code": "BTUW3M", "id": 88, "logo": null, "date": "2026-06-09T12:30:00+02:00", "start": "12:30", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-88-building-the-software-ecosystem-for-a-risc-v-datacenter", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BTUW3M/", "title": "Building the software ecosystem for a RISC-V datacenter", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "The RISC-V software ecosystem has grown steadily over the last few years. For embedded software it is reasonably complete, with good compiler, RTOS, and IDE support. The Linux kernel is also well supported, with RISC-V long having upstream support, and RVA23 now supported too. Canonical moved to requiring RVA23 with the release of Ubuntu 25.10, ready for the next generation of RISC-V silicon. But building out a data center takes more than just a good desktop experience. This poster/paper will examine the other elements required including provisioning, hypervisors, containers, orchestration, and also discusses how to manage custom instructions, security, maintenance. Going beyond theory, it discusses the data center Canonical will be building to include RISC-V RVA23 silicon supporting the Launchpad.net community website as well as other uses.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "JYL7YR", "name": "Jon Taylor", "avatar": null, "biography": "Jon has 25 years of experience in the semiconductor and software industries and has been involved with RISC-V since 2019. He is currently product manager for RISC-V at Canonical driving product development to strengthen the RISC-V ecosystem.", "public_name": "Jon Taylor", "guid": "4456fdff-5e86-5d10-835b-c69c39136217", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JYL7YR/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BTUW3M/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BTUW3M/", "attachments": []}, {"guid": "6424c0f0-f7a4-5098-bff1-b3be00fd6613", "code": "PC8KYU", "id": 35, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/PC8KYU/Tariq_and_Jas_nwV9KR3_dumiFps_eeAHdJJ.webp", "date": "2026-06-09T17:00:00+02:00", "start": "17:00", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-35-why-the-industry-needs-cheri-to-be-able-to-meet-the-eu-cyber-resilience-act", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PC8KYU/", "title": "Why the industry needs CHERI to be able to meet the EU Cyber Resilience Act", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "The Cyber Resilience Act is fully enforced in for all products \"with a digital element\" sold in the EU from December 2027. It has highly stringent requirements on manufacturers, such as products being \u201csecure by design and by default\u201d and \u201chaving no known vulnerabilities\u201d at the point of going on sale. Discovered vulnerabilities in the product must be reported within 24 hours for critical exploits. All vulnerabilities must be patched within a short time frame, and support must be for 5 years or longer depending on the product.\r\nAs a specific example of the effect of the CRA on consumer products, the Linux kernel had 4336 reported exploits (CVEs) in 2024 (12 per day) and 5779 in 2025 (16 per day). Linux is used in an increasingly large range of consumer devices, not least a large proportion of the world\u2019s smartphones. The able to continue to sell these products in Europe, then the industry really needs to move to a much more securely constructed systems.  CHERI systems have memory safety bult-in which resolves 70% of vulnerabilities seen in weaker non-CHERI legacy systems.\r\nResolving such a large proportion of vulnerabilities at source will greatly reduce the support and maintenance costs, if nothing else. As a result of the CRA, there will be a large shift in the industry to make systems much more secure.\r\nWe expect that much of that shift will be towards CHERI systems as manufacturers wake up to the cost savings.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "NPHGQ7", "name": "Tariq Kurd", "avatar": null, "biography": "", "public_name": "Tariq Kurd", "guid": "89c6a20e-6915-5d34-8ba8-ed2f2f119ab5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/NPHGQ7/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PC8KYU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PC8KYU/", "attachments": []}, {"guid": "3bdafcd1-3653-5d20-bfc2-aa7b5580aa0e", "code": "XFYMDU", "id": 138, "logo": null, "date": "2026-06-09T17:15:00+02:00", "start": "17:15", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-138-practical-implications-of-spmp-based-virtualization-in-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XFYMDU/", "title": "Practical Implications of SPMP-Based Virtualization in RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "The RISC-V SPMP for Hypervisor specification enable MMU-less virtualization through a multi-layered memory protection architecture. While this model provides strong isolation for mixed-criticality MCUs, concerns have been raised regarding the hardware overhead and timing impact of multiple PMP layers. In this work, we present an empirical evaluation of an SPMP for Hypervisor proof-of-concept implementation. We analyze FPGA resource utilization and timing behavior as a function of entry count and discuss realistic entry requirements for MCU-based virtualization workloads, providing insights for hardware designers adopting SPMP-based architectures.", "description": "This work provides information and empirical data about implications derived from the multi-PMP nature of a memory protection architecture using the SPMP for hypervisor (e.g., HW resource usage, timing, etc.), with a complementary discussion about the number of entries that real-world use cases require. This study serves as a response to several concerns raised regarding the impact in HW and timing of having so many PMP entries.", "recording_license": "", "do_not_record": false, "persons": [{"code": "WGRM8G", "name": "Manuel Rodr\u00edguez", "avatar": "https://cfp.riscv-europe.org/media/avatars/WGRM8G_OxgjlrN.webp", "biography": "MANUEL RODR\u00cdGUEZ earned his M.Sc. degree in Electronic and Computer Engineering at the University of Minho, Portugal, with a focus on Embedded Systems and Micro/Nanotechnologies. He is currently pursuing a Ph.D. in Electronics and Computer Engineering at the same institution, focusing on the development of novel RISC-V ISA primitives for secure virtualization in mixed-criticality systems. Throughout his career, he has contributed to the RISC-V ecosystem providing PoC artifacts for ongoing specifications, mostly in the hardware area. His research interests encompass computer architecture, RISC-V, hardware design, embedded virtualization, and safety-critical and mixed-criticality systems.", "public_name": "Manuel Rodr\u00edguez", "guid": "221259dd-fd48-5eac-b7c6-bf1edc61d5cc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WGRM8G/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XFYMDU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XFYMDU/", "attachments": []}, {"guid": "03606954-7618-5c50-8f65-c8d263d45c38", "code": "EXN7PD", "id": 223, "logo": null, "date": "2026-06-09T17:30:00+02:00", "start": "17:30", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-223-enabling-confidential-computing-on-risc-v-an-open-source-mpt-implementation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EXN7PD/", "title": "Enabling Confidential Computing on RISC-V: An Open-Source MPT Implementation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "Memory Protection Tables (MPT) is an emerging RISC-V extension under community discussion that enables fine-grained multi-supervisor domain physical memory isolation and access control for multi-tenant computing, addressing the security and isolation limitations of the traditional PMP mechanisms. This work presents the first open-source hardware implementation of the MPT draft specification (v0.4). Our design features a multi-level cache for accelerated permission checking and an L1TLB extension to reduce query frequency, with a decoupled architecture for portability. Evaluation shows only 2.32\\% average SPEC06 performance overhead and a 0.244\\% core area overhead, providing a hardware reference for SMMPT standardization.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "VB7CEB", "name": "Haoyuan Liu", "avatar": "https://cfp.riscv-europe.org/media/avatars/VB7CEB_35kKono.webp", "biography": "", "public_name": "Haoyuan Liu", "guid": "2f8ff0d7-22b9-5d36-b7da-0b2fd79f2bb6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VB7CEB/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EXN7PD/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EXN7PD/", "attachments": [{"title": "Extended Abstract with names", "url": "/media/eu-summit-2026/submissions/EXN7PD/resources/eusummitMPT_1_aDfcJpV.pdf", "type": "related"}]}, {"guid": "d5e63c78-803d-5e33-af08-3c1e5119f42f", "code": "3EZXZV", "id": 305, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/3EZXZV/vpoline_scheme_SIIxKoQ_rwSBB0_m3qpP6Z.webp", "date": "2026-06-09T17:45:00+02:00", "start": "17:45", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-305-heuristic-free-system-call-interception-on-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3EZXZV/", "title": "Heuristic-free system call interception on RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "Many applications benefit from the ability to intercept, block, or modify system calls efficiently. Binary rewriting is one of the fastest techniques to achieve this, but it often relies on instruction-dependent heuristics that limit its applicability. To date, exhaustive rewriting techniques (introduced by zpoline) are only available for x86-64 ISA. This work introduces vpoline, the first fully heuristics-free system call interception library for RISC-V. By leveraging the RISC-V linker relaxation mechanism, vpoline achieves the same benefits as zpoline while overcoming the intrinsic limitation of requiring privileged access.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "J3M3VC", "name": "Ottavio Monticelli", "avatar": "https://cfp.riscv-europe.org/media/avatars/J3M3VC_hhtoZeU.webp", "biography": "", "public_name": "Ottavio Monticelli", "guid": "f243c204-781f-5d1e-8736-c96c8edbb33f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/J3M3VC/"}, {"code": "D7VHGA", "name": "Iacopo Colonnelli", "avatar": "https://cfp.riscv-europe.org/media/avatars/D7VHGA_mMllG3G.webp", "biography": "Iacopo Colonnelli is an Assistant Professor in the [Department of Computer Science](https://www.cs.unito.it/do/home.pl) at the University\r\nof Turin. He serves on the Technical Committee of the [Common Workflow Language](https://www.commonwl.org/) (CWL), and is a founding coordinator of the [CWL4HPC](https://www.commonwl.org/working-groups/cwl4hpc) working group. He has co-authored over 40 peer-reviewed publications in national and international journals and conferences, and has contributed to more than 10 funded research projects. He is currently the local Principal Investigator for the [DARE European project](https://dare-riscv.eu/) (total budget: e240M). His research interests include workflow modeling and management in heterogeneous distributed architectures, high-performance computing and I/O, distributed confidential computing, and large-scale data science.", "public_name": "Iacopo Colonnelli", "guid": "9ec9925e-299e-5d8c-ba5d-3e98d9b05730", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/D7VHGA/"}, {"code": "FF9UW7", "name": "Marco Santimaria", "avatar": null, "biography": "", "public_name": "Marco Santimaria", "guid": "e311bd3f-b832-5783-9186-b8a8c1231549", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FF9UW7/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3EZXZV/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3EZXZV/", "attachments": []}], "Poster Island A": [{"guid": "e1696f2a-e960-520d-8557-d966d9745e1c", "code": "ZZ7ADW", "id": 279, "logo": null, "date": "2026-06-09T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-279-microarchitectural-side-channel-attack-on-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZ7ADW/", "title": "Microarchitectural Side-Channel Attack on RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Side-channel attacks leveraging microarchitectural features are well-studied on x86 and ARM, but less so on RISC-V. This work implements and evaluates Flush+Reload cache-side-channel attacks on user-space software in a RISC-V system simulated in gem5 full-system mode. We develop both eviction-based and cache-block-invalidate (cbo.inval) probes, establishing an attack methodology for an unprivileged process using the RISC-V cycle counter. Our experiments reveal timing differences between cached and evicted accesses, confirming the existence of exploitable timing channels. While key recovery remains partial, these results demonstrate the feasibility of cache side-channel attacks on RISC-V and validate gem5 as an effective platform for microarchitectural security research.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "DLHEHX", "name": "Sadia Shamas", "avatar": null, "biography": "", "public_name": "Sadia Shamas", "guid": "8e5771da-a381-5d49-aacc-85fce993ccbb", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DLHEHX/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZ7ADW/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZ7ADW/", "attachments": []}, {"guid": "0446eda8-af31-576a-89f2-be4cdefcc0a5", "code": "MKBAZS", "id": 354, "logo": null, "date": "2026-06-09T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-354-evaluating-the-vulnerability-of-risc-v-cpus-against-cache-timing-attacks", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MKBAZS/", "title": "Evaluating the Vulnerability of RISC-V CPUs Against Cache Timing Attacks", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Assessing the vulnerability of caches against side-channel attacks is of critical importance when enhanced microarchitectural security is a must-have feature for a multicore CPU implementation. Previous works have proposed various metrics and methodologies to assess such vulnerabilities. However, those works suffer from limitations regarding either the range of target cache attacks, the support for the RISC-V ISA, or the public availability of the assessment tools. The goal of this paper is to provide support for systematically evaluating RISC-V multicore CPUs against a wide range of cache timing attacks. This support should allow the assessment of both real and simulated systems, enabling early security evaluation in the design phase of the processor using the open-source gem5 microarchitectural simulator. We base our approach on the Cache Timing Vulnerability Score (CTVS) methodology and enhance it along two axes. We first port the CTVS methodology to the RISC-V ISA, and then we integrate the CTVS methodology for the RISC-V and x86 ISAs with gem5. We evaluate the use of the CTVS methodology for simulated RISC-V and x86 multicore CPUs and analyze the results.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CHURPA", "name": "Vasileios Karakostas", "avatar": null, "biography": "", "public_name": "Vasileios Karakostas", "guid": "2b4290cd-9e8a-59ce-a2d4-4033941bb00b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CHURPA/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MKBAZS/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MKBAZS/", "attachments": []}, {"guid": "c6e44df9-4f8e-5917-87c5-aa541534ad12", "code": "EFXQQP", "id": 158, "logo": null, "date": "2026-06-09T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-158-from-leakage-to-exploitability-empirical-study-of-cross-process-l1-prime-probe-on-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EFXQQP/", "title": "From Leakage to Exploitability: Empirical Study of Cross-Process L1 Prime+Probe on RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Cache timing attacks against AES are well studied on x86 and ARM, but their end-to-end exploitability on commercially deployed RISC-V systems under realistic OS scheduling is less documented. This paper presents an experimental evaluation of a Prime+Probe attack targeting the private L1 data cache of a PolarFire SoC RISC-V platform running Linux, where attacker and victim are independent user-space processes time-multiplexed on the same core. We separate three stages, leakage observability, cache-set classification, and key inference, and show that first-round T-table lookups induce measurable per-set interference enabling reliable inference of the most significant 4 bits of AES key bytes. We also find substantial cache-set variability highlighting a practical gap between observable leakage and end-to-end exploitability on real RISC-V systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "A93HJ8", "name": "Fortunelli Gianmarco", "avatar": null, "biography": "Gianmarco Fortunelli is an Electronic Engineering student at Politecnico di Torino and EURECOM, focusing on embedded systems, hardware security, and computer architecture. His work spans RISC-V security research and digital design, with a strong interest in efficient and secure computing.", "public_name": "Fortunelli Gianmarco", "guid": "41a9004f-d2e0-5a98-9c7c-a157ba48c12b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/A93HJ8/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EFXQQP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EFXQQP/", "attachments": []}, {"guid": "605433dd-9bf9-5a51-a557-951aa344688f", "code": "HZQQP9", "id": 194, "logo": null, "date": "2026-06-09T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-194-riscy-prefetchers", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HZQQP9/", "title": "RISCY Prefetchers", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "While hardware prefetchers accelerate memory performance, they inadvertently leave microarchitectural footprints that attackers can exploit. Previous work showed that instruction and data prefetchers on Intel, AMD and Apple processors are prone to microarchitectural side-channel attacks. In this paper we investigate the data stride prefetcher in the \\textit{Xuantie C910} -- a server-grade RISC-V processor extensively deployed in cloud environments. Furthermore, we present the first microarchitectural attack targeting a hardware prefetcher on a RISC-V processors. In that regard, we port StrideRE on RISC-V processors to reverse engineer its hardware prefetcher. Finally, we provide two Proof-of-Concept (PoC) attacks: partial memory address disclosure and control flow leakage. We find that both attacks are effective across privilege levels.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "7BYLVM", "name": "Mohamed Soliman", "avatar": "https://cfp.riscv-europe.org/media/avatars/7BYLVM_Fu1ToVI.webp", "biography": "I'm a doctoral researcher at Tampere University. My research focus is hardware security and specifically, researching CPU side-channel attacks and defenses. Previously, I worked on hardware design, verification and physical implementation for 2 System-on-Chips at Tampere University, and now I'm starting my doctoral research.", "public_name": "Mohamed Soliman", "guid": "33f0e077-bc56-5ed4-815a-3e688970ac12", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7BYLVM/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HZQQP9/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HZQQP9/", "attachments": []}, {"guid": "65e19398-53e6-56e6-a278-e77ee3617aba", "code": "DZKKKP", "id": 341, "logo": null, "date": "2026-06-09T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-341-beyond-bare-metal-a-lightweight-cross-privilege-framework-for-risc-v-rtl-security-evaluation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DZKKKP/", "title": "Beyond Bare-Metal: A Lightweight Cross-Privilege Framework for RISC-V RTL Security Evaluation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Mitigating transient execution attacks like Spectre in RISC-V processors requires cycle-accurate Register Transfer Level (RTL) simulation. However, existing methodologies face a severe dichotomy: simple bare-metal benchmarks lack crucial architectural features (e.g., virtual memory, privilege boundaries), while full-OS simulations incur prohibitive execution times. To bridge this gap, we propose a novel, lightweight RTL simulation framework that accurately models cross-privilege transitions (User and Supervisor modes) and virtual address translation without the overhead of a full OS payload. We validated this approach by simulating a realistic, cross-privilege Spectre-PHT attack on the out-of-order NaxRiscv core, achieving secret recovery in approximately 100,000 cycles. This drastically accelerates vulnerability characterization compared to Linux-boot environments. Ultimately, this low-noise environment provides hardware designers with an efficient tool to rapidly analyze transient vulnerabilities and evaluate the performance overhead of hardware countermeasures.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "E899MZ", "name": "Karim AIT LAHSSAINE", "avatar": null, "biography": "", "public_name": "Karim AIT LAHSSAINE", "guid": "b54d10ed-c7be-5d53-badb-833d53b5ffaa", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/E899MZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DZKKKP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DZKKKP/", "attachments": []}, {"guid": "35fe29dd-02af-5d21-84f9-c308c8ceb34c", "code": "CEW33C", "id": 254, "logo": null, "date": "2026-06-09T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-254-injectv-modeling-fault-injection-attacks-in-risc-v-simulation-environment", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CEW33C/", "title": "InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Fault Injection Attacks (FIAs) induce transient hardware faults to subvert software security mechanisms, yet assessing fault resilience, especially during early design phases, remains impractical without specialized laboratory equipment. Microarchitectural simulation provides a reproducible and scalable alternative. This paper presents InjectV, a gem5-based fault injection framework targeting RISC-V systems, which employs trace-guided fault injection by identifying Candidate Injection Points (CIPs) at security-critical operations including control-flow branches and conditional comparisons. Supporting transient corruption of architectural registers and physical memory under full-system simulation, InjectV demonstrates that guided fault injection requires 95.8% fewer injections than random exploration to expose successful attacks on the FISSC VerifyPIN benchmarks.", "description": "InjectV is a research framework designed to evaluate the security impact of Fault Injection Attacks (FIAs) on RISC-V systems using full-system simulation. The project focuses on modeling realistic physical attacks that can induce transient faults and alter program execution. \r\nThe framework is implemented on top of the gem5 microarchitectural simulator in full-system mode, enabling experiments that include the operating system, firmware, and user applications. This allows the study of fault propagation across the entire hardware\u2013software stack in a deterministic and reproducible environment.\r\nInjectV introduces an attack-oriented methodology for fault injection so that instead of randomly exploring the fault space, it analyzes execution traces to identify Candidate Injection Points (CIPs) associated with security-relevant operations such as conditional branches, comparisons, and control-flow decisions. Fault injections are then guided toward these points to model realistic attack vectors more efficiently.\r\nThe system supports transient corruption of both architectural registers and physical memory, with configurable parameters for timing, bit selection, and injection frequency. A campaign manager orchestrates large experimental campaigns, automating simulation execution, parallelization, timeout handling, and result aggregation. The framework was evaluated using the FISSC VerifyPIN benchmark, demonstrating that guided campaigns significantly improve the efficiency of discovering security-relevant faults compared to random exploration.\r\nOverall, InjectV provides a reproducible environment for studying how transient hardware faults can be exploited to bypass software protections, enabling early-stage security evaluation of embedded and processor-based systems before physical hardware is available.", "recording_license": "", "do_not_record": false, "persons": [{"code": "ARSJVN", "name": "Niccol\u00f2 Lentini", "avatar": "https://cfp.riscv-europe.org/media/avatars/ARSJVN_0eINKHN.webp", "biography": "Niccol\u00f2 Lentini is a PhD student in Computer and Cybersecurity Engineering at Politecnico di Torino, Italy. His research focuses on hardware and system security, with particular emphasis on fault injection attacks, the resilience of RISC-V systems, and post-quantum security. He received his MSc in Cybersecurity Engineering from Politecnico di Torino, where his Master\u2019s thesis focused on securing avionic embedded systems using hardware-assisted security mechanisms. His current research investigates methodologies and tools for evaluating the security of computing platforms against physical attacks.", "public_name": "Niccol\u00f2 Lentini", "guid": "fb446f72-bd3c-5577-a766-514c79f39799", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ARSJVN/"}, {"code": "87T3FE", "name": "Giorgio Fardo", "avatar": "https://cfp.riscv-europe.org/media/avatars/87T3FE_apbxBsu.webp", "biography": "Research Engineer at CEA-List, I hold a Master\u2019s degree in Cybersecurity Engineering from Politecnico di Torino. I am passionate about hardware and software security, with a strong focus on fault injection and microarchitectural security.", "public_name": "Giorgio Fardo", "guid": "cc2afc26-c985-5de8-a5c7-19ea626f7e75", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/87T3FE/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CEW33C/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CEW33C/", "attachments": []}, {"guid": "f064dfa6-d1d7-5b12-bf46-f21407c7d75b", "code": "A9JD3J", "id": 237, "logo": null, "date": "2026-06-09T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-237-exhaustive-security-verification-of-access-control-in-processors", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A9JD3J/", "title": "Exhaustive Security Verification of Access Control in Processors", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Access control is a foundation of security and is implemented in the hardware of Systems-on-chip. The entire system stack relies on the secure and correct functioning of these access control mechanisms. However, contemporary security verification methods face major challenges in exhaustively detecting targeted security vulnerabilities while also being scalable. We address these challenges with a novel formulation of security property sets. Our approach introduces interlocked property sets, which have a mathematical characteristic that enables scalable and exhaustive verification of general security targets. We propose an interlocked property set for access control verification in processors and have evaluated our approach in several case studies on RISC-V processor cores. Our approach detected multiple security vulnerabilities.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "PBQLNB", "name": "Anna Duque Ant\u00f3n", "avatar": null, "biography": "Anna Duque Ant\u00f3n received her Dipl.-Ing. degree in Electrical and Computer Engineering from the RPTU University Kaiserslautern-Landau in 2019. She is currently a Ph.D. candidate at the Electronic Design Automation group at the same university, working under supervision of Prof. Kunz and Prof. Stoffel. Her research interests include formal security verification, access control mechanisms and hardware trojan detection. For her work on SoC-wide security verification, she received the Intel Hardware Security Academic Award 2022.", "public_name": "Anna Duque Ant\u00f3n", "guid": "9945acc1-d880-5ff6-a2f9-fa5b4afc35d0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/PBQLNB/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A9JD3J/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A9JD3J/", "attachments": []}, {"guid": "d3b82f9d-f78a-5edf-82e7-e278efa0a5d2", "code": "SPL3GT", "id": 270, "logo": null, "date": "2026-06-09T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-270-cva6-cfi-a-first-glance-at-risc-v-control-flow-integrity-extensions", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SPL3GT/", "title": "CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "This work presents the first design and evaluation of the standard RISC-V Control-Flow Integrity (CFI)\r\nextensions. The Zicfiss and Zicfilp extensions protect vulnerable software from control-flow hijacking through shadow stack and landing pad mechanisms. We integrate dedicated hardware support for both extensions into the open-source CVA6 core. Synthesis in 22 nm FDX technology shows only 1.0% area overhead, while evaluation on the MiBench automotive benchmark subset reports up to 15.6% runtime overhead.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "Z97MVH", "name": "Simone Manoni", "avatar": "https://cfp.riscv-europe.org/media/avatars/Z97MVH_TUbgO1b.webp", "biography": "", "public_name": "Simone Manoni", "guid": "bc32104f-1080-5b22-961b-f62d03e2ba9a", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Z97MVH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SPL3GT/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SPL3GT/", "attachments": []}, {"guid": "b5c561fa-46ad-5cba-a835-031b4a19ec52", "code": "YLJJMH", "id": 159, "logo": null, "date": "2026-06-09T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-159-cheri-rvy-development-support-platform", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YLJJMH/", "title": "CHERI RVY development support platform", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "We present the development flow and platform we have built to support CHERI development and ratification of the RVY extension. CHERI is an ISA extension providing hardware support for capabilities - unforgeable memory references embedding a memory address as well as bounds and permissions metadata. It enables spatial and temporal memory safety by design. We have developed a comprehensive workflow used to validate the proposed RVY extension both for functionality and performance. We maintain and make use of a formal golden model, which we leverage for design verification effort through directed-random fuzz testing of architectural features under development. We gather core CHERI functionalities in a reusable RTL library to use across multiple commercial and research implementations, maximising reuse of verification effort. We build and boot soft-core images of CHERI-enabled systems on FPGA at scale, enabling software development and performance\r\nevaluation of RV64Y microarchitectures and software stacks. This infrastructure has enabled rapid convergence for the development of the RVY extension with a high level of confidence in functionality and performance. We are now making use of this infrastructure to further enable various streams of research.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "39D7SY", "name": "Alexandre Joannou", "avatar": null, "biography": "", "public_name": "Alexandre Joannou", "guid": "f38b3456-f379-58f9-9dcb-239ce7ff3c00", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/39D7SY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YLJJMH/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YLJJMH/", "attachments": []}, {"guid": "f3a0c275-2605-5ceb-9508-8abe089c9ab0", "code": "MD7RVM", "id": 283, "logo": null, "date": "2026-06-09T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-283-rv64y-temporal-safety-exploration", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MD7RVM/", "title": "RV64Y Temporal Safety Exploration", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "We present the studies leading up to the temporal safety support included in the RV64Y \u201cCHERI\u201d capability RISC-V extension. Memory safety enforcement is increasingly important for new programs, languages, and architectures. RV64Y enforces spatial memory safety natively, and provides the necessary invariants to enforce temporal safety in software.\r\nTo ensure that RV64Y systems can enforce temporal safety with reasonable performance and memory overhead, we have reproduced experiments from previous CHERI research, optimised CheriBSD revocation support, and explored simplified state machines for virtual memory pages encoded in Page Table Entry (PTE) bits.  We managed to optimize revocation in CheriBSD to reduce overhead in Spec2006 by 12%. We then explored the simplest PTE encoding with generational capability read support, and found that they incurred an overhead of about 33% over the optimised baseline, justifying the inclusion of generational capability dirty states in the frozen RV64Y specification. Finally, we discuss ongoing work that has the potential to further optimize temporal safety for RV64Y with vendor-specific or future ratified extensions.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "YUBWWU", "name": "Jonathan Woodruff", "avatar": "https://cfp.riscv-europe.org/media/avatars/YUBWWU_6MonRRm.webp", "biography": "Jonathan Woodruff is a Associate Research Professor with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.", "public_name": "Jonathan Woodruff", "guid": "a65a5565-e105-5697-83b9-875ae4c6d9c5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YUBWWU/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MD7RVM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MD7RVM/", "attachments": []}, {"guid": "148a9968-a1c6-5fb0-a413-3181b6d4987d", "code": "9S7HBH", "id": 119, "logo": null, "date": "2026-06-09T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-119-the-art-of-zeroing-on-cheri-risc-v-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9S7HBH/", "title": "The art of zeroing on CHERI RISC-V systems", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Memory zeroing is a common operation for enforcing system security. Zeroing is used to clear memory contents to prevent information leakage and initialise memory contents to prevent uninitialized memory access. Vendors such as Intel and ARM support fast memory zeroing instructions to improve system performance efficiency. The cache management operation (CMO) extension has also been recently been added to RISC-V which can be used for improving memory zeroing performance. Compared to the standard systems, memory zeroing is more frequently used in capability systems such as CHERI to prevent capability leakage. In this work, we evaluate different memory zeroing strategies on CHERI, and implement hardware support for improving the performance and efficiency of memory zeroing on CHERI-Toooba: a CHERI-extended RISC-V CPU.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "LVW8XV", "name": "Yuecheng Wang", "avatar": null, "biography": "", "public_name": "Yuecheng Wang", "guid": "46f10293-9dbe-5531-8470-fc438cbcdcf0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/LVW8XV/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9S7HBH/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9S7HBH/", "attachments": []}, {"guid": "1a44b932-f9a2-50f1-92ab-edc4fbe11903", "code": "JFUNQZ", "id": 241, "logo": null, "date": "2026-06-09T14:00:00+02:00", "start": "14:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-241-bao-cheri-a-pure-capability-risc-v-hypervisor", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JFUNQZ/", "title": "Bao-CHERI: A Pure-Capability RISC-V Hypervisor", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "We present our work on porting CHERI to the open-source Bao hypervisor targeting the RISC-V architecture. A preliminary evaluation of our implementation shows a 30.2% increase in code size, an additional 1 KiB of runtime memory usage, a 20% increase in boot time, and a 13.43% increase in interrupt latency. To the best of our knowledge, this is the first publicly available implementation of a hypervisor incorporating CHERI for RISC-V that supports both CHERI and the RISC-V hypervisor extension. The port is publicly available as an open-source artifact for the RISC-V and CHERI communities.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HEYXRW", "name": "Bruno Sa", "avatar": "https://cfp.riscv-europe.org/media/avatars/HEYXRW_WzOvVYF.webp", "biography": "", "public_name": "Bruno Sa", "guid": "23c1d188-895e-5953-b7a1-0534424e99c5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HEYXRW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JFUNQZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JFUNQZ/", "attachments": []}, {"guid": "ac519886-1b06-5958-8f86-b8ef66975929", "code": "ZBWRKF", "id": 236, "logo": null, "date": "2026-06-09T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-236-distinguishing-exploit-failure-from-effective-cheri-protection-on-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWRKF/", "title": "Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "CHERI extends conventional ISAs with hardware-enforced capabilities to provide fine-grained memory protection and its integration in RISC-V is gaining momentum with RVY. As adoption grows, implementations must be evaluated to ensure working CHERI protection mechanisms. We show that existing memory-corruption exploit implementations do not directly carry over to CHERI-enabled architectures, and that observed exploit failures (i.e., unsuccessful exploits) do not necessarily imply effective protection. To resolve this ambiguity, we propose a methodology that temporarily disables CHERI enforcement within a RISC-V VP. Comparing exploit behavior with and without CHERI enforcement under otherwise identical conditions makes it possible to distinguish exploit failure from effective CHERI protection.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "SXX79M", "name": "Andreas Hinterdorfer", "avatar": "https://cfp.riscv-europe.org/media/avatars/SXX79M_Y1lPzYM.webp", "biography": "", "public_name": "Andreas Hinterdorfer", "guid": "ae289a56-55b9-5129-a67d-8bd063a0cb1f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SXX79M/"}, {"code": "YYN8DQ", "name": "Manfred Schl\u00e4gl", "avatar": null, "biography": "Manfred Schl\u00e4gl is a PhD student at the Institute for Complex Systems, JKU Linz, under Prof. Daniel Gro\u00dfe. For 15 years, he worked in industry, focusing mainly on low-level firmware and operating systems for industrial embedded systems. In 2021, he left the industry to resume his studies, completed his Master's degree in Computer Science in 2023, and started his PhD immediately afterward. His main research interests are hardware/software co-simulation using virtual prototypes and hardware verification. He is also deeply interested in operating systems, hardware platforms, and computer architectures, especially RISC-V.", "public_name": "Manfred Schl\u00e4gl", "guid": "770c5fec-a356-5bd3-aa16-ac44c230c6c0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YYN8DQ/"}, {"code": "TW7YDL", "name": "Daniel Gro\u00dfe", "avatar": "https://cfp.riscv-europe.org/media/avatars/TW7YDL_xYTVPx4.webp", "biography": "", "public_name": "Daniel Gro\u00dfe", "guid": "58d8bc6d-0200-5bfe-b1d2-017fe384c265", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TW7YDL/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWRKF/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWRKF/", "attachments": []}, {"guid": "3c70d259-ccc9-5bf6-89ba-08f236188f29", "code": "RZD9L9", "id": 338, "logo": null, "date": "2026-06-09T15:30:00+02:00", "start": "15:30", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-338-dasics-efficient-in-process-protection-with-hardware-assisted-dynamic-compartmentalization", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RZD9L9/", "title": "DASICS: Efficient In-process Protection with Hardware-assisted Dynamic Compartmentalization", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Hardware-assisted in-process compartmentalization is an effective method for addressing security threats within complex software applications. This paper proposes DASICS, an efficient design of hardware-assisted in-process compartmentalization, including flexible permission management, sufficient security metadata protection, complete resource access control, and little hardware-to-software ABI modification requirements. DASICS divides the process into trusted and untrusted region and uses boundary registers and user-level interrupts to achieve dynamic permission management, thereby avoiding the overhead of privilege-level switching in traditional methods. \r\n    We implemented a hardware prototype of DASICS on the RISC-V XiangShan out-of-order processor and validated its effectiveness on FPGA. Experimental results show that DASICS incurs an average performance overhead of only 1.53% in SPECint2006 tests while effectively defending against common vulnerabilities such as stack/heap overflows and control-flow hijacking in security test suite.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "W8VPMZ", "name": "Tianyue Lu", "avatar": null, "biography": "Associate professor\r\nInstitute of Computing Technology, Chinese Academy of Sciences\r\nResearch interests: computer architecture, memory system, memory security", "public_name": "Tianyue Lu", "guid": "2233a7e3-2bff-543f-a2d9-9d90327d9f63", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/W8VPMZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RZD9L9/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RZD9L9/", "attachments": []}, {"guid": "fca33c7e-0b1a-58c5-b98a-decd11fec21c", "code": "RQP9GP", "id": 351, "logo": null, "date": "2026-06-09T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-351-memory-protection-for-mmu-less-risc-v-current-status-of-spmp-and-vspmp", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RQP9GP/", "title": "Memory Protection for MMU-less RISC-V: Current Status of SPMP and vSPMP", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "As RISC-V expands into embedded critical domains like IoT and automotive automotive require predictable isolation mechanisms. Traditional MMU-based virtualization is often impractical for these resource-constrained environments due to the latency of page-table walks and significant memory overhead. In contrast, MPU-style region-based protection offers deterministic access checks with minimal footprint, making physical memory protection essential for secure, mixed-criticality systems.\r\n\r\nWhile RISC-V PMP provides such mechanisms at machine privilege level, modern embedded software stacks, including RTOSes, separation kernels, and lightweight hypervisors, require similar capabilities at supervisor level. The proposed Supervisor-mode Physical Memory Protection (SPMP) extensions address this gap by allowing supervisor software to define access permissions over physical memory regions, enabling robust compartmentalization of software components in systems without virtual memory.\r\n\r\nVirtualization further increases the need for such mechanisms. Embedded hypervisors are increasingly used to consolidate multiple operating systems or software domains on a single microcontroller-class platform while maintaining strict isolation guarantees. To support this model, SPMP is being extended to interact with the RISC-V Hypervisor extension through a two-stage protection approach (vSPMP), enabling the hypervisor to enforce global isolation while allowing guest operating systems to manage their own protection domains.\r\n\r\nThis talk presents the current status of the SPMP and SPMP for Hypervisor specifications, their architectural design and rationale, and their integration with the RISC-V privilege architecture. We will discuss the design rationale, implementation considerations, and potential deployment scenarios in secure IoT microcontrollers and automotive mixed-criticality systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "VLKK3H", "name": "joseosyx", "avatar": null, "biography": "", "public_name": "joseosyx", "guid": "eaa9238b-0692-557d-be51-84be46b8316e", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VLKK3H/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RQP9GP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RQP9GP/", "attachments": []}, {"guid": "76a46a7c-6394-555e-a6ed-b714883befb1", "code": "3JPLFW", "id": 134, "logo": null, "date": "2026-06-09T15:50:00+02:00", "start": "15:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-134-a-decoupled-iopmp-architecture-open-source-implementation-with-distributed-bridges-for-multi-master-socs", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3JPLFW/", "title": "A Decoupled IOPMP Architecture: Open-Source Implementation with Distributed Bridges for Multi-Master SoCs", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper presents a distributed Input-Output Physical Memory Protection (IOPMP) architecture featuring a decoupled I/O bridge and checker. The architecture enables distributed placement of I/O bridges to accommodate multi-master SoC configurations while sharing a single centralized checker, significantly reducing area overhead. The design is implemented in a 7nm process, with a single I/O bridge occupying less than 1200 \u00b5m\u00b2. It incurs less than 0.2% performance overhead under 4KB large-packet transmission. The code has been merged into the OpenXiangShan Git repository and is available as open-source hardware.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "7XL3PW", "name": "Hongtuo Yuan", "avatar": "https://cfp.riscv-europe.org/media/avatars/7XL3PW_n5FwVwR.webp", "biography": "", "public_name": "Hongtuo Yuan", "guid": "3f37fce0-09cc-55f6-a454-55fdc18105d4", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7XL3PW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3JPLFW/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3JPLFW/", "attachments": []}], "Poster Island B": [{"guid": "4a885012-ad1f-5617-9cad-0bf6b2c73863", "code": "FLFBGM", "id": 336, "logo": null, "date": "2026-06-09T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-336-an-open-source-risc-v-vm-level-tee-architecture-implemented-on-xiangshan-processor", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FLFBGM/", "title": "An Open-Source RISC-V VM-Level TEE Architecture Implemented on XiangShan Processor", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Trusted Execution Environments (TEEs) are essential for cloud security, with Confidential Virtual Machines (CVMs) as the prevailing approach. While proprietary solutions dominate deployments, the RISC-V ecosystem lacks mature open-source CVM implementations despite CoVE progress. This paper presents a VM-level TEE architecture on the open-source XiangShan RISC-V processor, featuring physical isolation of Enclave Management Tasks via dedicated secure cores. We implement bitmap-based page-granularity memory isolation and multi-key memory encryption for fine-grained access control and software-defined full-memory cryptographic protection. Evaluation on FPGA prototypes demonstrates minimal EMS area overhead (<1% of SoC area).", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "J3PA8H", "name": "Wenhao Wang", "avatar": "https://cfp.riscv-europe.org/media/avatars/J3PA8H_6KZQEKO.webp", "biography": "", "public_name": "Wenhao Wang", "guid": "0248a4e5-d0de-5c77-b174-2ad7802d7567", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/J3PA8H/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FLFBGM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FLFBGM/", "attachments": []}, {"guid": "c0569c58-de18-5c19-ac99-242dbf3163f3", "code": "H87VUG", "id": 266, "logo": null, "date": "2026-06-09T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-266-cage-v-confidential-computing-architecture-supporting-guest-enclaves-for-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/H87VUG/", "title": "CAGE-V: Confidential Computing Architecture supporting Guest Enclaves for RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Confidential VMs enable cloud service providers to operate a secure and trustworthy multi-tenant cloud infrastructure.\r\nWhile confidential VMs ensure comprehensive protection for cloud workloads, such heavy-weight isolation is often omitted for serverless applications that co-locate thousands of cloud workers within the same process to optimize FaaS overheads through efficient context switches.\r\nIn this work, we present CAGE-V, a novel confidential computing architecture that supports lightweight enclave-based isolation for individual cloud workers running inside confidential VMs.\r\nGuest enclaves support fast context switches within the confidential VM, as TLB entries are tagged with Domain Identifiers, eliminating overheads that stem from TLB flushes.\r\nWe present a CAGE-V prototype, consisting of a hardware extension for the CORE-V CVA6 processor and a small security monitor, and evaluate our design in terms of system performance, demonstrating a minor performance impact.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3EWEJR", "name": "Moritz Waser", "avatar": "https://cfp.riscv-europe.org/media/avatars/3EWEJR_ENdlMQF.webp", "biography": "Moritz Waser is a PhD student in the Secure Systems (SESYS) group at ISEC, Graz University of Technology.\r\nHis research interests include memory safety, confidential computing, capability systems and hardware security.", "public_name": "Moritz Waser", "guid": "67ab44fa-5683-58d1-9c5a-ffec5341a39f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3EWEJR/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/H87VUG/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/H87VUG/", "attachments": []}, {"guid": "7c191131-bb85-50f9-9b10-072c189de889", "code": "RT7JWV", "id": 334, "logo": null, "date": "2026-06-09T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-334-a-low-latency-real-time-risc-v-mcu-for-tee", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RT7JWV/", "title": "A Low Latency Real-Time RISC-V MCU for TEE", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "In modern embedded security architectures, the Trusted Execution Environment (TEE) serves as the fundamental tool for isolation, ensuring that critical assets in applications like Electric Vehicles (EVs) and robotics remain protected from compromised software. However, restricted by current RISC-V specifications for MCUs, implementing this isolation typically imposes a severe penalty on real-time performance due to the prolonged software prologue required for context switching. To resolve this, we present a lightweight 2-mode (M-mode and U-mode) secure-domain-aware RISC-V MCU architecture designed for security-sensitive, real-time applications. This architecture introduces a hardware-managed \"Trusted State\" (TS) used to dynamically filter valid enhanced Physical Memory Protection (ePMP) entries in U-mode. To eliminate register preservation overhead, the MCU features a dedicated \"Snapshot Buffer\" for every General Purpose Register (GPR) and Control and Status Register (CSR) subject to backup. Crucially, the hardware captures the execution context into this buffer in a single cycle, allowing the CPU to immediately begin executing the Interrupt Service Routine (ISR). The captured data is then pushed to an SP-based Data Local Memory (DLM) via a 128-bit wide data-path in the background. By overlapping this memory write with the ISR's preamble execution, this design effectively hides the context save time, ensuring the system is seamlessly prepared for nested interrupts. This architecture guarantees hardware-enforced isolation while satisfying the real-time requirement.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "WHTKQZ", "name": "Paul Shan-Chyun Ku", "avatar": "https://cfp.riscv-europe.org/media/avatars/WHTKQZ_7OhVixG.webp", "biography": "Dr. Ku works for Andes Technology Corporation and is enthusiastic about processor and platform security. He currently serves the IOPMP TG as the chair (Jul.2022 - now) and the TEE TG as the vice-chair (Apr.2021 - Mar.2022), and has presented several times in RISC-V Summits. \r\nWith 20+ years of experience in the semiconductor industry, he has participated in over a dozen ASIC projects, particularly in SoC design, optimization, and security.\r\nHe majored in Computer Engineering, was granted a Ph.D., and became an adjunct associate professor at National Tseng Hua University, focusing on processor security, parallel algorithms, and algorithm analysis.", "public_name": "Paul Shan-Chyun Ku", "guid": "01041668-0821-5e2e-ae1d-032c3d7ed935", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WHTKQZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RT7JWV/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RT7JWV/", "attachments": []}, {"guid": "2fb2a8cf-ac8f-5932-b8fa-92c363d0d3f0", "code": "BVHAVM", "id": 215, "logo": null, "date": "2026-06-09T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-215-enhancing-boot-time-security-in-risc-v-leveraging-keccak-hardware-accelerator", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BVHAVM/", "title": "Enhancing Boot Time Security in RISC-V Leveraging Keccak Hardware Accelerator", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Secure boot verifies the integrity and authenticity of code before execution; otherwise, it terminates the boot process. In contrast, measured boot produces verifiable evidence of code integrity at boot time, for example using the Device Identifier Composition Engine (DICE). However, in both mechanisms, hashing large code is the main performance bottleneck. This work combines secure boot and DICE-based measured boot, implements the design on a CVA6-based RISC-V platform, incorporates post-quantum cryptography for quantum-resistant secure boot, and accelerates computationally intensive hash computations through a custom Keccak hardware accelerator.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "KFLXUW", "name": "Utku Budak", "avatar": null, "biography": "My name is Utku Budak. I am a research assistant and PhD candidate at the Chair of Security in Information Technology, working in cooperation with Siemens.", "public_name": "Utku Budak", "guid": "8ea8751e-147b-55de-891d-33b23b3f87ea", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KFLXUW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BVHAVM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BVHAVM/", "attachments": []}, {"guid": "9ac5f25e-ab84-5306-9422-493f3cfc9e54", "code": "M8ABDU", "id": 250, "logo": null, "date": "2026-06-09T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-250-towards-a-secure-risc-v-platform-the-environment-around-the-cva6-core", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/M8ABDU/", "title": "Towards a Secure RISC-V Platform: The Environment Around the CVA6-Core", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The rising adoption of RISC-V in real-world applications raises the requirement of security solutions within its processors. Secure boot enables the product owner to control which software may be booted on it, preventing execution of malicious software. That requires a hardware root-of-trust, typically in conjunction with public key cryptography, establishing the infrastructure to verify software. We propose a secure boot concept for the widely adopted CVA6 core with revocation capabilities. We also modernized the CVA6 software stack to be able to continue the verification steps in later software stages and leverage modern security hardware extensions.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BYXKTY", "name": "Lukas F\u00fcreder", "avatar": null, "biography": "", "public_name": "Lukas F\u00fcreder", "guid": "8f89fe2e-ac6f-5185-85e4-cdce1266da8e", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BYXKTY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/M8ABDU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/M8ABDU/", "attachments": []}, {"guid": "ab4ba901-dff3-573f-a9e0-823cabbe8f30", "code": "NA9Q9H", "id": 61, "logo": null, "date": "2026-06-09T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-61-ace-atomic-cryptography-extension-for-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NA9Q9H/", "title": "ACE: Atomic Cryptography Extension for RISC-V", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The Atomic Cryptographic Extension (ACE) is an ISA extension to enable secure cryptographic implementations. ACE separates key provisioning from key usage, enabling distinct environments to perform the two functions. For example, keys could be delivered to user software by a TEE applet. Unlike existing round-based AES extensions, which inherently expose key material, ACE performs cryptographic operations atomically. Keys are associated with metadata that ties them to specific algorithms and usage policies. Keys and metadata are bonded to each other by writing them in Context Registers (CRs). The contents of CRs can only be exported in encrypted and authenticated form for secure re-import, enabling secure context switches and VM migrations. ACE is work in progress of the High Assurance Cryptography (HAC) TG of RISC-V International.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "MRDXSP", "name": "Roberto Avanzi, Ruud Derwig, Luis Fiolhais, and Radim Krcm\u00e1r", "avatar": null, "biography": "Representatives from Qualcomm, Synopsys, and an Independent Researcher who are actively contributing the the RISC-V High-Assurance Cryptography task group.", "public_name": "Roberto Avanzi, Ruud Derwig, Luis Fiolhais, and Radim Krcm\u00e1r", "guid": "2e324314-126b-5d55-8566-9d8d0ace6fd6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MRDXSP/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NA9Q9H/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NA9Q9H/", "attachments": []}, {"guid": "e345cef4-6f75-53ec-8993-8971d0ec989b", "code": "ZBWEM7", "id": 361, "logo": null, "date": "2026-06-09T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-361-anssi-ipecc-accelerated-ecc-on-cva6-risc-v-soc-integration-and-benchmarking", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWEM7/", "title": "ANSSI IPECC-Accelerated ECC on CVA6 RISC-V SoC: Integration and Benchmarking", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "IPECC, an open-source side-channel-resistant ECC hardware accelerator developed by the French national agency ANSSI, is integrated into the CVA6 RISC-V SoC and prototyped on a Genesys 2 (XC7K325T) FPGA. Using the libecc cryptographic library, we evaluate eight signature scheme/curve combinations in three configurations: software-only execution, hardware acceleration without countermeasures, and fully protected hardware acceleration. With all countermeasures active, IPECC reduces ECDSA P-256 signature latency from 1.13 s to 180 ms (a 6.3x speedup), reaching 7.8x for Schnorr-based schemes and scaling up to 9.1x for P-521. On the FPGA target, the countermeasure overhead varies drastically from +3% (hash-dominated EdDSA) to +279% (Schnorr-based schemes). We demonstrate that this variance is fundamentally driven by the physical True Random Number Generator (TRNG) latency and each protocol\u2019s specific reliance on scalar multiplication. In its compact P-256 configuration, the accelerator occupies only 4.2% of the FPGA LUT fabric (3,602 LUTs, 12 DSP48E1). This platform provides a reproducible basis for benchmarking ECC acceleration and side-channel countermeasures on RISC-V SoCs.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "MJMRGD", "name": "IGHILAHRIZ Billal", "avatar": null, "biography": "", "public_name": "IGHILAHRIZ Billal", "guid": "38db4628-5263-53d3-96e0-18b6f0b3bc07", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MJMRGD/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWEM7/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWEM7/", "attachments": []}, {"guid": "f6ad02cf-871a-5e96-b7c8-a9417a07712f", "code": "QGKMZ7", "id": 65, "logo": null, "date": "2026-06-09T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-65-improving-chacha20-by-risc-v-vector-extension-design-and-engineering-implementation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QGKMZ7/", "title": "Improving ChaCha20 by RISC-V Vector Extension: Design and Engineering Implementation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "ChaCha20 is a high-performance stream cipher widely deployed in TLS and SSH, typically combined with Poly1305 for authenticated encryption. This paper presents a practical vectorized implementation of ChaCha20 using the RISC-V Vector (RVV) extension, with complete engineering code in the Go ecosystem. We outline how ChaCha20's add--xor--rotate structure maps to RVV instructions and describe a fully vectorized design covering register allocation, rotation implementation, and 64-byte block processing. Experiments on a real RISC-V 64 platform (Spacemit X60) show up to 1.5X throughput improvement on large data blocks and a 35.58% geometric mean speedup over the generic Go implementation. The implementation is suitable for direct integration into open-source cryptographic stacks on RVV-enabled RISC-V platforms.", "description": "The paper is organized as follows: Section 2 reviews the ChaCha20 algorithm; Section 3 introduces the RVV extension and its key instructions for ChaCha20; Section 4 details the vectorized design and engineering implementation; Section 5 presents the experimental results and performance analysis; Section 6 discusses future work; Section 7 concludes the paper.", "recording_license": "", "do_not_record": false, "persons": [{"code": "TBFZHL", "name": "Meng Zhuo", "avatar": "https://cfp.riscv-europe.org/media/avatars/TBFZHL_6SxWZ9a.webp", "biography": "RISC-V Engineer, mainly focus on Go compiler/toolchains developement", "public_name": "Meng Zhuo", "guid": "85629119-46ca-51a1-aa62-6819f146d3a2", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TBFZHL/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QGKMZ7/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QGKMZ7/", "attachments": []}, {"guid": "7bd78d15-a0e7-513c-bde4-b28a701cb697", "code": "WEQNRM", "id": 206, "logo": null, "date": "2026-06-09T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-206-pqc4emrtd-post-quantum-cryptography-for-resource-constrained-risc-v-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WEQNRM/", "title": "PQC4eMRTD: Post Quantum Cryptography for Resource Constrained RISC-V Systems", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The PQC4eMRTD is a CSA (Coordination and Support Action) project funded by the European Commission, which focuses on monitoring and influencing the standardization space of Post Quantum Security with a particular focus on machine readable travel documents (MRTDs) such as national identification cards, passports and other personal documents. These types of documents include tiny microprocessors which interact with RFID devices in order to read sensitive personal information (e.g. biographic and biometric data) stored securely on the document, and allows the authentication of a person. Existing documents use conventional cryptographic algorithms which will be vulnerable to quantum computer attacks, especially considering the long validity period of such documents. For this reason, there is an interest in planning their migration to post quantum cryptographic algorithms in a standardized way. This abstract focuses on the work performed in the project within RISC-V systems, which extends to other types of resource constrained systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3CQN3V", "name": "Leonidas Kosmidis", "avatar": "https://cfp.riscv-europe.org/media/avatars/3CQN3V_e3qlH0a.webp", "biography": "Dr. Leonidas Kosmidis is the Group Leader of the Hardware Dependability for Embedded Systems (HADES) group at the Barcelona Supercomputing Center (BSC) and Faculty member at the Universitat Polit\u00e8cnica de Catalunya (UPC). His research interests include hardware and software design for high performance safe and secure embedded systems, and particularly GPUs. He was the recipient of the RISC-V Educator of the Year Award in 2019 and he is involved in several standardisation efforts around RISC-V, hardware design and GPUs for safety critical systems.", "public_name": "Leonidas Kosmidis", "guid": "01439899-bacf-5b96-bad9-5f213b8ac00b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3CQN3V/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WEQNRM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WEQNRM/", "attachments": []}, {"guid": "2e49773e-797c-5b62-86a3-f2179c4a9ce2", "code": "PB9JGQ", "id": 58, "logo": null, "date": "2026-06-09T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-58-cost-benefit-analysis-of-a-22nm-asic-ml-kem-accelerator-for-risc-v-secure-elements", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PB9JGQ/", "title": "Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V Secure Elements", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper provides a quantitative analysis of the costs and benefits of integrating a dedicated hardware accelerator for the Post Quantum Cryptography (PQC) algorithm ML-KEM into a 32-bit RISC-V SoC. We compare a software-only implementation on the CV32E40P core against a full-hardware datapath offloading the entire algorithm. We implemented the system on a 22 nm ASIC chip, and we measured the results: the dedicated hardware achieves a 139x speed-up over the software baseline. This performance gain requires an area overhead of 301 kGE, representing only a 6% increase in the total SoC silicon footprint. This study provides a data-driven assessment of the silicon-to-latency trade-off for Post-Quantum Cryptography (PQC) in resource-constrained RISC-V systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BT8HDF", "name": "Stefano Di Matteo", "avatar": "https://cfp.riscv-europe.org/media/avatars/BT8HDF_mdi9SnE.webp", "biography": "Stefano Di Matteo received his M.Sc. (2019) and Ph.D. (2023) respectively in Electronic Engineering and Information Engineering from the University of Pisa. He is currently a tenure-track researcher in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction Set Extensions for PQC", "public_name": "Stefano Di Matteo", "guid": "d588454d-5a07-56ea-883a-2b426ee778aa", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BT8HDF/"}, {"code": "UMVFWV", "name": "Ivan Sarno", "avatar": null, "biography": "", "public_name": "Ivan Sarno", "guid": "60b2051a-bbbf-5dd1-89c6-85fdeb3f7b66", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UMVFWV/"}, {"code": "TUKUZV", "name": "Emanuele Valea", "avatar": null, "biography": "", "public_name": "Emanuele Valea", "guid": "45210441-fc95-5da8-aab7-b5f818a8d404", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TUKUZV/"}, {"code": "LWR8VL", "name": "Hack", "avatar": null, "biography": null, "public_name": "Hack", "guid": "ad7d5d66-3631-59db-8a75-160bda4a70b8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/LWR8VL/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PB9JGQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PB9JGQ/", "attachments": []}, {"guid": "325905dc-0eb6-5131-a7c9-09324c114c3c", "code": "NEMJHQ", "id": 124, "logo": null, "date": "2026-06-09T14:00:00+02:00", "start": "14:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-124-integrating-aes-cryptographic-acceleration-with-risc-v-cryptography-extensions-in-32-bit-processors", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NEMJHQ/", "title": "Integrating AES Cryptographic Acceleration with RISC-V Cryptography Extensions in 32-bit processors", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This work introduces a compatible acceleration approach for AES encryption that retains the standardized ISA interface while enhancing execution time for AES-128 on 32-bit processors, including the key-schedule phase. By reformulating the behavior of existing Zk instructions without altering their opcodes, we preserve binary and source compatibility with software written for Zkne, without the performance losses of having to perform key expansion only by software. The result is an integration strategy suitable for constrained IoT or automotive devices that delivers improved throughput with reduced area overhead, enabling systems to realize the intended benefits of RISC-V\u2019s cryptographic extension without sacrificing portability and standarization.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3RQBEV", "name": "Francisco J. Romero", "avatar": null, "biography": "", "public_name": "Francisco J. Romero", "guid": "12190d64-65cd-56e6-993a-dccf87f70d95", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3RQBEV/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NEMJHQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NEMJHQ/", "attachments": []}, {"guid": "026e9167-8367-5da1-8dc3-b8a241c5d607", "code": "SXGTPT", "id": 39, "logo": null, "date": "2026-06-09T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-39-circe-cross-integrated-risc-v-cryptographic-extension", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SXGTPT/", "title": "CIRCE: CROSS Integrated RISC-V Cryptographic Extension", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Post-Quantum Cryptography (PQC) is moving from algorithm selection to deployment, where performance, energy, and portability are key constraints, especially on embedded and IoT-class processors. Many PQC schemes stress general-purpose cores with large arithmetic workloads and heavy memory traffic. Instruction-set extensions (ISE) offer a practical middle ground: they speed up dominant kernels while preserving programmability.\r\nIn this context, we target post-quantum digital signatures, which remain under active evaluation, as reflected by NIST's 2023 call for additional schemes. We focus on CROSS, a code-based signature built from zero-knowledge proofs and the Restricted Syndrome Decoding Problem, and present CIRCE: a RISC-V\u2013integrated extension connected through the Core-V eXtension Interface (CV-X-IF). CIRCE supports both R-SDP and R-SDP(G), runs across all official parameter sets without hardware retuning, and achieves an average 2x speed-up on a Zynq UltraScale+ FPGA with an ultra-compact footprint (down to 800 LUTs / 100 FFs).", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "Q8U9UR", "name": "Valeria Piscopo", "avatar": "https://cfp.riscv-europe.org/media/avatars/Q8U9UR_QacOgBH.webp", "biography": "Valeria Piscopo received the B.Sc. and M.Sc. degrees in Electronic Engineering from Politecnico di Torino, in 2021 and 2024 respectively. Since November 2024, she is a Ph.D student in\u00a0Electrical, Electronic and Communications Engineering at Politecnico di Torino. Her research activity is centered on the design of secure hardware accelerators for Post-Quantum Cryptography and their integration in RISC-V ecosystems.", "public_name": "Valeria Piscopo", "guid": "07221515-74c8-5364-89b8-6cd42cbb2224", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Q8U9UR/"}, {"code": "SKL3A3", "name": "aledolme", "avatar": "https://cfp.riscv-europe.org/media/avatars/SKL3A3_1t8jlo3.webp", "biography": "Ph.D. researcher in Electrical/Electronic Engineering with strong organizational skills and high motivation. Experienced in hardware/software co-design for embedded systems, including RISC-V SoC integration, custom accelerator interfaces, RTL development (SystemVerilog), FPGA prototyping, and embedded C. Solid background in Post-Quantum Cryptography implementations and optimization, with a performance-driven mindset and enthusiasm for new technical challenges.", "public_name": "aledolme", "guid": "c4cbac77-8c68-5b53-93c8-eafb9d01666d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SKL3A3/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SXGTPT/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SXGTPT/", "attachments": []}, {"guid": "d70a7f6f-bc7d-5344-8858-325cc6fd6801", "code": "QLUGPK", "id": 59, "logo": null, "date": "2026-06-09T15:30:00+02:00", "start": "15:30", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-59-compiler-aided-autovectorization-of-pqc-on-risc-v-vector-extensions", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QLUGPK/", "title": "Compiler-Aided Autovectorization of PQC on RISC-V Vector Extensions", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Post-Quantum Cryptography (PQC) is rapidly becoming a security requirement, and ML-KEM (FIPS 203) is emerging as a foundational primitive for future secure systems. On RISC-V platforms, performance evaluations frequently emphasize custom extensions or dedicated accelerators, while the optimization potential of the standard ISA remains comparatively underexplored. This paper establishes a rigorous performance baseline for the main computational kernels of ML-KEM using only the standard RISC-V Vector Extension (RVV). Rather than relying on handwritten assembly, we apply targeted C-level program transformations that systematically enable effective compiler autovectorization, achieving up to a 10\u00d7 reduction in instruction count for NTT while preserving portability across all RVV-compliant implementations.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "UMVFWV", "name": "Ivan Sarno", "avatar": null, "biography": "", "public_name": "Ivan Sarno", "guid": "60b2051a-bbbf-5dd1-89c6-85fdeb3f7b66", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UMVFWV/"}, {"code": "BT8HDF", "name": "Stefano Di Matteo", "avatar": "https://cfp.riscv-europe.org/media/avatars/BT8HDF_mdi9SnE.webp", "biography": "Stefano Di Matteo received his M.Sc. (2019) and Ph.D. (2023) respectively in Electronic Engineering and Information Engineering from the University of Pisa. He is currently a tenure-track researcher in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction Set Extensions for PQC", "public_name": "Stefano Di Matteo", "guid": "d588454d-5a07-56ea-883a-2b426ee778aa", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BT8HDF/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QLUGPK/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QLUGPK/", "attachments": []}, {"guid": "58891d1b-f759-5651-af80-c5641cd5b8a3", "code": "ZE8LDR", "id": 368, "logo": null, "date": "2026-06-09T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-368-performance-characterization-and-profiling-of-hqc-autovectorization-on-risc-v-vector-cores", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZE8LDR/", "title": "Performance Characterization and Profiling of HQC Autovectorization on RISC-V Vector cores", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The emergence of quantum computers threatens traditional cryptographic schemes, requiring the development of post-quantum algorithms. In this paper, we study the performance of the Hamming Quasi-Cyclic (HQC) scheme, the new Key Encapsulation Method (KEM) ratified by NIST in March 2025. We analyze different implementation approaches for the Sargantana RV64GBV core using the standard RISC-V bit-manipulation (B) and vector (V) extensions. We compare reference implementations against auto-vectorized code and then provide an overview of how to analyze and profile these implementations using RAVE.", "description": "This study analyzes the performance characteristics of the HQC post-quantum Key Encapsulation Mechanism on a RISC-V RV64 processor with vector extensions. Multiple polynomial multiplication kernel implementations used in HQC on the Sargantana RV64GBV core are evaluated. Auto-vectorization and cycle-accurate hardware simulation enable comparison of scalar and vectorized implementations across various HQC security levels. Furthermore, the RAVE emulator framework profiles vector execution to identify key performance bottlenecks.", "recording_license": "", "do_not_record": false, "persons": [{"code": "MJPDKW", "name": "Vito Cucinelli", "avatar": "https://cfp.riscv-europe.org/media/avatars/MJPDKW_gBHwVgC.webp", "biography": "", "public_name": "Vito Cucinelli", "guid": "ef75f7b1-f2fc-5dc2-810e-8bff886b0901", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MJPDKW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZE8LDR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZE8LDR/", "attachments": []}, {"guid": "6a574f46-80cd-5c02-a480-7a494c0ca286", "code": "ACRS3G", "id": 40, "logo": null, "date": "2026-06-09T15:50:00+02:00", "start": "15:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-40-chimera-cryptographic-hardware-for-integrated-multipurpose-engine-on-risc-v-with-ascon", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ACRS3G/", "title": "CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "As the NIST Lightweight Cryptography (LWC) standard, ASCON is pivotal for securing IoT ecosystems. This work presents CHIMERA, a multipurpose cryptographic engine for RISC-V, supporting AEAD and Hashing. We propose two architectural paradigms integrated via the Core-V eXtension Interface (CV-X-IF): a high-performance Complete Round (CR) version utilizing a state-register bank, and a minimalist Bitwise Rotation Unit (BRU) version focusing on Instruction Set Extensions (ISE). Our designs suit throughput-critical workloads, delivering up to 6x speed-up, as well as footprint-constrained deployments on ASIC and FPGA.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "VYHAT9", "name": "Enrico Manfredi", "avatar": "https://cfp.riscv-europe.org/media/avatars/VYHAT9_P2oGmgi.webp", "biography": "", "public_name": "Enrico Manfredi", "guid": "00b24060-58bc-5528-aad0-6a34c1d4e170", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VYHAT9/"}, {"code": "SKL3A3", "name": "aledolme", "avatar": "https://cfp.riscv-europe.org/media/avatars/SKL3A3_1t8jlo3.webp", "biography": "Ph.D. researcher in Electrical/Electronic Engineering with strong organizational skills and high motivation. Experienced in hardware/software co-design for embedded systems, including RISC-V SoC integration, custom accelerator interfaces, RTL development (SystemVerilog), FPGA prototyping, and embedded C. Solid background in Post-Quantum Cryptography implementations and optimization, with a performance-driven mindset and enthusiasm for new technical challenges.", "public_name": "aledolme", "guid": "c4cbac77-8c68-5b53-93c8-eafb9d01666d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SKL3A3/"}, {"code": "Q8U9UR", "name": "Valeria Piscopo", "avatar": "https://cfp.riscv-europe.org/media/avatars/Q8U9UR_QacOgBH.webp", "biography": "Valeria Piscopo received the B.Sc. and M.Sc. degrees in Electronic Engineering from Politecnico di Torino, in 2021 and 2024 respectively. Since November 2024, she is a Ph.D student in\u00a0Electrical, Electronic and Communications Engineering at Politecnico di Torino. Her research activity is centered on the design of secure hardware accelerators for Post-Quantum Cryptography and their integration in RISC-V ecosystems.", "public_name": "Valeria Piscopo", "guid": "07221515-74c8-5364-89b8-6cd42cbb2224", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Q8U9UR/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ACRS3G/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ACRS3G/", "attachments": []}, {"guid": "d299390c-a054-50c2-8344-98c8e5998edd", "code": "ZZQYRH", "id": 94, "logo": null, "date": "2026-06-09T16:00:00+02:00", "start": "16:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-94-horcrux-a-post-quantum-cryptography-instruction-set-extension", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZQYRH/", "title": "HORCRUX: a Post-Quantum Cryptography Instruction Set Extension", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper introduces HORCRUX, an open RISC-V instruction set extension for post-quantum cryptography (PQC). A modular PQ-ALU, integrated through the Core-V eXtension Interface (CV-X-IF) accelerates the core kernels shared by hash-, lattice-, and code-based schemes, including Keccak processing, sampling, modular/polynomial arithmetic, finite-field operations, and coefficient compression. The design targets NIST-standardized algorithms (ML-KEM, ML-DSA, SLH-DSA, HQC) and additional candidates under evaluation. We release the complete hardware/software stack as open source and report 65 nm ASIC post-synthesis results: with a compact footprint of ~26.3 kGE and energy savings up to 99.5%, the extension provides a practical route to energy-efficient PQC on RISC-V with minimal integration effort.", "description": "We present a PQC instruction-set extension that prioritizes kernel-level reuse over per-algorithm specialization. The design identifies the recurring computational patterns that dominate PQC workloads and maps them onto a compact set of custom operations executed by a dedicated PQC arithmetic unit. The same accelerated building blocks support NIST-standardized schemes as well as a wider set of candidate designs, without requiring RTL modifications to the host CPU.\r\nHORCRUX is implemented in a 65 nm CMOS ASIC flow at 100 MHz, with a synthesized area of 26.3 kGE (less than 2% of the host SoC). Each custom instruction is validated through dedicated micro-tests to capture realistic switching activity; post-synthesis power is estimated with Synopsys PrimePower and combined with measured cycle counts to derive energy per operation. Across the full kernel suite, the proposed instructions deliver approximately 5\u00d7 average speedup over the software baseline and 47% average energy reduction, up to 99.5% for Karatsuba primitve. Overall, HORCRUX achieves a compact, PQC-ISE that provides consistent acceleration and energy savings across heterogeneous PQC families.", "recording_license": "", "do_not_record": false, "persons": [{"code": "Q8U9UR", "name": "Valeria Piscopo", "avatar": "https://cfp.riscv-europe.org/media/avatars/Q8U9UR_QacOgBH.webp", "biography": "Valeria Piscopo received the B.Sc. and M.Sc. degrees in Electronic Engineering from Politecnico di Torino, in 2021 and 2024 respectively. Since November 2024, she is a Ph.D student in\u00a0Electrical, Electronic and Communications Engineering at Politecnico di Torino. Her research activity is centered on the design of secure hardware accelerators for Post-Quantum Cryptography and their integration in RISC-V ecosystems.", "public_name": "Valeria Piscopo", "guid": "07221515-74c8-5364-89b8-6cd42cbb2224", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Q8U9UR/"}, {"code": "SKL3A3", "name": "aledolme", "avatar": "https://cfp.riscv-europe.org/media/avatars/SKL3A3_1t8jlo3.webp", "biography": "Ph.D. researcher in Electrical/Electronic Engineering with strong organizational skills and high motivation. Experienced in hardware/software co-design for embedded systems, including RISC-V SoC integration, custom accelerator interfaces, RTL development (SystemVerilog), FPGA prototyping, and embedded C. Solid background in Post-Quantum Cryptography implementations and optimization, with a performance-driven mindset and enthusiasm for new technical challenges.", "public_name": "aledolme", "guid": "c4cbac77-8c68-5b53-93c8-eafb9d01666d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SKL3A3/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZQYRH/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZQYRH/", "attachments": []}, {"guid": "1f508d0d-5351-5e7e-a3b7-2cb3a5a62dab", "code": "3Y7HQP", "id": 173, "logo": null, "date": "2026-06-09T16:10:00+02:00", "start": "16:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-173-quantum-computing-simulation-on-risc-v-vector-and-multithreaded-evaluation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3Y7HQP/", "title": "Quantum Computing Simulation on RISC-V: Vector and Multithreaded Evaluation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Classical quantum computing simulation is computationally demanding due to exponential state-vector growth.This work evaluates parallelization strategies on the RISC-V SpacemiT K1 using the RISC-V Vector Extension (RVV v1.0) and OpenMP. The dominant qubit-wise multiplication kernel was implemented in four variants: Sequential, OpenMP (MIMD), RVV vectorized (SIMD), and hybrid (OpenMP+RVV). Benchmarks up to 30 qubits 2<sup>30</sup> show size-dependent behavior: SIMD benefits small systems, multithreading improves medium scales, and large systems become memory-bound. The hybrid configuration achieves a peak speedup of 72.1\u00d7 at 16 qubits and maintains 34.7\u00d7 at 30 qubits, demonstrating the benefits of vector extensions and multi-core parallelism for quantum computing simulation workloads.", "description": "Classical simulation of quantum circuits remains an essential tool for developing and validating quantum algorithms before they can run on real quantum hardware. However, the exponential growth of the quantum state vector quickly makes these simulations computationally demanding, requiring efficient use of modern hardware architectures.\r\n\r\nIn this work, we explore how RISC-V platforms can accelerate quantum simulation by combining vectorization and multithreaded parallelism. A quantum circuit simulator was implemented in C with a focus on optimizing the qubit-wise multiplication kernel, which represents the dominant computational cost in many simulations. Several implementations were evaluated, including a sequential baseline, a multithreaded version using OpenMP, a vectorized implementation using the RISC-V Vector Extension (RVV), and a hybrid approach combining both techniques.\r\n\r\nExperiments were conducted on a Banana Pi BPI-F3 platform based on the RISC-V SpacemiT K1 processor, with simulations scaling up to 30 qubits. The results show that different optimization strategies become more effective depending on the problem size and memory behavior of the system. The hybrid OpenMP+RVV configuration achieves the best overall performance, reaching a peak speedup of 72.1\u00d7 and maintaining strong acceleration even for the largest simulations tested.\r\n\r\nThese results highlight the potential of RISC-V architectures for accelerating demanding scientific workloads such as quantum circuit simulation.", "recording_license": "", "do_not_record": false, "persons": [{"code": "ANMDHM", "name": "Rebeca Rasco Flores", "avatar": null, "biography": "Rebeca Rasco Flores holds a BSc in Health Engineering from the University of Seville and an MSc in Mechatronics Engineering from the University of M\u00e1laga. She is currently a Research Fellow in the Department of Computer Architecture at the University of M\u00e1laga, where she is pursuing a PhD in Mechatronics Engineering. Her research focuses on the optimization and acceleration of quantum simulators on high-performance architectures, with a particular interest in RISC-V vector extensions and multi-core parallelism. Her work aims to bridge the gap between advanced classical computing and the efficient simulation of quantum circuits.", "public_name": "Rebeca Rasco Flores", "guid": "e641082e-44ff-5fc3-bb0d-0ca6a64fd735", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ANMDHM/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3Y7HQP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3Y7HQP/", "attachments": []}], "Poster Island C": [{"guid": "a5bf0cb1-12a3-58b6-9cd2-2ec450cbda18", "code": "Z8GZYW", "id": 373, "logo": null, "date": "2026-06-09T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-373-rvv-tips-tricks", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/Z8GZYW/", "title": "RVV Tips & Tricks", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The RISC-V vector extension introduces SIMD instructions to RISC-V, however many known patterns in other SIMD extensions don't translate 1-to-1.\r\nTherefore, the goal of this document is to share various RVV tips and tricks as well as some common pitfalls.\r\nIt should help people familiar with other SIMD ISAs to figure out how to efficiently express many common patterns in RVV.\r\nWe collected these paradigms while porting various software and algorithms to RVV.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CN8THZ", "name": "Olaf Bernstein", "avatar": null, "biography": "", "public_name": "Olaf Bernstein", "guid": "5fa80e7e-55ea-53d4-8108-9b61a00dc290", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CN8THZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/Z8GZYW/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/Z8GZYW/", "attachments": []}, {"guid": "ff60227e-0318-5537-8041-80d85f2a4d07", "code": "8QKTQW", "id": 106, "logo": null, "date": "2026-06-09T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-106-locality-aware-sparse-matrix-multiplication-on-risc-v-rvv", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8QKTQW/", "title": "Locality-Aware Sparse Matrix Multiplication on RISC-V RVV", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Sparse matrix\u2013dense matrix multiplication (SpMM) is a fundamental workload in high-performance computing and emerging edge workloads, yet its performance is typically memory-bound due to irregular and indirect memory accesses. While the RISC-V Vector Extension (RVV) provides flexible data-parallel execution, efficiently exploiting it for sparse workloads remains challenging.\r\n\r\nThis work evaluates an iterative SpMM kernel on an RVV-enabled RISC-V processor (Spacemit X60, 8 cores) and investigates the combined impact of locality-aware data layout and explicit vectorization. We compare scalar, compiler-vectorized, library-based, and manual intrinsic implementations. Additionally, we apply Morton (Z-order) reordering to improve spatial locality in memory.\r\n\r\nExperimental results show that vectorization alone provides limited benefits in memory-bound regimes. However, when combined with Morton reordering, manual RVV vectorization achieves the best performance. Microarchitectural analysis confirms reduced cache misses and improved IPC, although the workload remains fundamentally bandwidth-limited.\r\n\r\nThe study highlights the importance of data layout co-design when targeting sparse workloads on emerging RISC-V platforms.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "JWDEWN", "name": "Andrea Herrer\u00edas Le\u00f3n", "avatar": null, "biography": "", "public_name": "Andrea Herrer\u00edas Le\u00f3n", "guid": "0fd53e9f-ef27-59ac-aa9b-45e15a4f5544", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JWDEWN/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8QKTQW/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8QKTQW/", "attachments": []}, {"guid": "753c2a2e-ac1b-5aa1-8ded-7c87f6dbfbcb", "code": "QUURJD", "id": 216, "logo": null, "date": "2026-06-09T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-216-accelerating-myers-bit-vector-alignment-with-risc-v-vector-intrinsics", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QUURJD/", "title": "Accelerating Myers\u2019 Bit-Vector Alignment With RISC-V Vector Intrinsics", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Pairwise sequence alignment is a key component of many bioinformatics workflows and is often a performance bottleneck. Recent advances in sequencing technologies have improved accuracy, while also increasing the need for accelerators that can efficiently handle long reads. Myers\u2019 bit-vector algorithm is well suited to acceleration, and AVX-512 has enabled high-performance implementations, such as SeqMatcher. However, these solutions rely on a fixed register width and AVX-512-specific instructions, which creates a scalability ceiling and limits portability. We implement Myers\u2019 algorithm using RISC-V Vector (RVV) intrinsics and focus on the addition step, which we identify as the main bottleneck in our vectorized kernel. We evaluate two RVV addition alternatives across LMUL values and dataset sizes on a Banana Pi and find that the iterative carry-propagation variant achieves up to 10.29x speedup over the scalar baseline.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EWW87F", "name": "Elena Espinosa", "avatar": null, "biography": "", "public_name": "Elena Espinosa", "guid": "aab791bc-7310-541a-aa37-562f673778f9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EWW87F/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QUURJD/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QUURJD/", "attachments": []}, {"guid": "ea7b1261-b535-55be-a567-420fa7d25b84", "code": "NFYQCV", "id": 152, "logo": null, "date": "2026-06-09T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-152-accelerating-llm-inference-on-edge-risc-v-cpus-via-vector-extension-instructions-and-flash-attention", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NFYQCV/", "title": "Accelerating LLM Inference on Edge RISC-V CPUs via Vector Extension Instructions and Flash Attention", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "In this work, we optimize LLM inference on edge RISC-V CPUs using vector extension instructions. We leverage 4-bit vector load and efficient 8-bit dot-product instructions to accelerate quantized and repacked 4-bit kernels in llama.cpp. In addition, we implement RVV support for tiled flash attention, which further improves performance in the prefill stage. Experimental results show that the proposed optimizations achieve 1.76x-2.14x speedup over the upstream implementation while maintaining near-linear scaling for prefill workloads on an RVV-enabled multi-core platform.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "AFYFGP", "name": "Yueh-Feng Lee", "avatar": null, "biography": "Dr. Yueh-Feng Lee received his Ph.D. degree in computer science from National Chiao Tung University. He previously worked at Mediatek and Industrial Technology Research Institute. His areas of focus include AI compiler and runtime, hypervisor technology, and embedded systems.", "public_name": "Yueh-Feng Lee", "guid": "5495c2b9-dec1-57cd-8f2f-4cecac740177", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AFYFGP/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NFYQCV/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NFYQCV/", "attachments": []}, {"guid": "e71223e3-2a7c-5bb8-92da-2b07d3f3d6cc", "code": "QB3TNY", "id": 258, "logo": null, "date": "2026-06-09T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-258-why-edges-matter-a-case-study-on-performance-improvements-for-openblas-gemm-on-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QB3TNY/", "title": "Why Edges Matter: A Case Study on Performance Improvements for OpenBLAS GEMM on RISC-V", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Matrix multiplication (GEMM) sits at the heart of scientific computing, data analytics, and modern AI workloads. While much attention is given to peak throughput and ideal matrix sizes, real-world performance often hinges on the \u201cedges\u201d i.e., non-ideal dimensions, cache boundaries, and vector tail cases that quietly dominate execution time. In this paper, we present a practical case study of optimizing GEMM in OpenBLAS for RISC-V vector architectures. We show how careful handling of edge conditions, cache reuse, and vectorization strategy can deliver measurable performance gains. Techniques include maximizing cache and register reuse with single-pass data traversal, swapping operands and deferring transposition for easier storage, combining full- and half-vector operations with scalar instructions to efficiently handle irregular dimensions, and leveraging strided segmented load/store vector intrinsics to sustain throughput even in non-ideal layouts. These optimizations are not just academic; small inefficiencies in GEMM propagate directly into AI inference latency and energy. By focusing on edge cases and architectural nuance, we can unlock meaningful improvements for real-world workloads. These optimizations give substantial gains; for example, a 6 x 3072 \u00d7 3072 SGEMM MatMul efficiency improves from 23.5% to 68.7% of the peak.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "Q3CSBZ", "name": "Chip Kerchner", "avatar": "https://cfp.riscv-europe.org/media/avatars/Q3CSBZ_5h9qzHM.webp", "biography": "Sr. Staff Performance Engineer, Infrastructure - Tenstorrent", "public_name": "Chip Kerchner", "guid": "c45255e3-bc7e-502a-adc5-aa8478e0cacd", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Q3CSBZ/"}, {"code": "FSJUJT", "name": "Rama Malladi", "avatar": null, "biography": "", "public_name": "Rama Malladi", "guid": "2b5fdeb3-4370-5e23-bb04-c098bc1c8ef8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FSJUJT/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QB3TNY/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QB3TNY/", "attachments": []}, {"guid": "3ceda00f-8647-591f-a59d-1449b07bb4d4", "code": "WHMPM8", "id": 144, "logo": null, "date": "2026-06-09T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-144-onnx-runtime-convolution-acceleration-on-risc-v-via-rvv", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WHMPM8/", "title": "ONNX Runtime Convolution Acceleration on RISC-V via RVV", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Inference engines are specialized software systems designed to execute pre-trained Machine Learning models. ONNX Runtime (ORT) emerges as a leading open-source inference engine for the Open Neural Network Exchange (ONNX) format, allowing models to be deployed regardless of the framework in which they were trained.\r\n        While ORT provides a flexible architecture for deploying models across diverse hardware, it currently lacks architecture-specific optimizations for RISC-V. Consequently, computationally intensive tasks such as the convolution operation\u2014which accounts for the majority of inference time in Convolutional Neural Networks (CNNs)\u2014suffer from hardware underutilization by relying on standard scalar instructions. In this paper, we address this gap by proposing an optimized convolution implementation leveraging the RISC-V Vector Extension (RVV) and integrating it as a custom Execution Provider in ORT. We evaluate our solution on a Banana Pi BPI-F3 board across six standard reference CNN models. Experimental results show that our RVV-accelerated implementation achieves speedups of up to 3x compared to the official scalar ORT release, significantly improving CNN inference performance on RISC-V platforms.", "description": "Our paper proposes an implementation of convolution acceleration in ONNX Runtime for RISC-V using the RISC-V Vector Extension (RVV). The paper explains the context of the contribution and details the two vectorization strategies integrated into ONNX Runtime. Experiments were conducted on a Banana Pi BPI-F3 board, a reference RISC-V hardware for this type of evaluation.", "recording_license": "", "do_not_record": false, "persons": [{"code": "GBHFMV", "name": "Jose Sanchez-Yun", "avatar": "https://cfp.riscv-europe.org/media/avatars/GBHFMV_gaODdEa.webp", "biography": "Jose Sanchez-Yun received his B.S. degree in Computer Engineering from the University of Cordoba in 2022, and his M.S. degree in Software Engineering and Artificial Intelligence from the University of Malaga in 2024. He is currently pursuing a Ph.D. degree at the University of Malaga. His research interests include the development of RISC-V ISA extensions for neural network optimization and the vectorization of time series analysis algorithms.", "public_name": "Jose Sanchez-Yun", "guid": "efb1b4ea-4dbb-5504-a472-60f1cb78266e", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GBHFMV/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WHMPM8/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WHMPM8/", "attachments": []}, {"guid": "c9cc8abc-c6d7-51a5-9b6b-fe63c8a55ee6", "code": "XTDV7A", "id": 56, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/XTDV7A/RISCV2026_11_4GMz1fb.jpeg", "date": "2026-06-09T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-56-risc-v-vector-1-0-code-generation-in-mlir-xdsl", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XTDV7A/", "title": "RISC-V Vector 1.0 code Generation in MLIR-xDSL", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The fragmented RISC-V ecosystem demands portable, high-performance code generation for the Vector Extension (RVV 1.0). Upstream MLIR (LLVM 22.0) lacks two critical lowering stages needed for this: it cannot flatten dynamic memref ma- trix references into C pointers, nor emit Vector-Length-Agnostic (VLA) RVV intrinsics. This paper closes that gap with a six-stage hybrid MLIR\u2013xDSL compilation workflow that automatically generates parameterized, hardware-aware C micro- kernels for GEMM entirely in Python, without modifying the MLIR C++ codebase. On a COTS BananaPi F3 board (SpaceMiT K1, 256-bit RVV 1.0), we show: (i) isolated micro-kernels match or exceed hand-written reference code (0.98\u00d7\u2013 1.05\u00d7), peaking at 16.2 GFLOPS at the optimal 16\u00d715 tile; (ii) on BERT-Large transformer layers (B1\u2013B5), generated micro-kernels consistently surpass OpenBLAS, reaching up to 12.2 GFLOPS against the baseline\u2019s 5.1 GFLOPS (a 2.4\u00d7 speedup) and maintaining an average 15\u201327% performance advantage across all layer dimensions.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "AMPMN3", "name": "Jie Lei", "avatar": "https://cfp.riscv-europe.org/media/avatars/AMPMN3_LYoUG1P.webp", "biography": "", "public_name": "Jie Lei", "guid": "081434fe-49f1-5dc4-be23-cd073763edbc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AMPMN3/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XTDV7A/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XTDV7A/", "attachments": [{"title": "Poster PDF", "url": "/media/eu-summit-2026/submissions/XTDV7A/resources/RISCV2026_11_h2nfUZP.pdf", "type": "related"}]}, {"guid": "bf3e005e-0c67-57c0-a6e4-4f646c723e9c", "code": "8BXPC9", "id": 298, "logo": null, "date": "2026-06-09T14:00:00+02:00", "start": "14:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-298-ai-inference-on-bare-metal-risc-v-microcontrollers-a-comparison-of-executorch-and-iree-mlir", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8BXPC9/", "title": "AI inference on bare-metal RISC-V Microcontrollers: A comparison of ExecuTorch and IREE/MLIR", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "We have previously demonstrated that it is practical to bring up ExecuTorch on a low power bare metal microcontroller.  ExecuTorch is a project derived from the PyTorch AI framework for inference on embedded devices using traditional eager (\u201cinterpreted\u201d) evaluation of AI models.  In this paper, we provide a short overview of how to run ExecuTorch on a bare metal microcontroller.  We then illustrate the features of 32-bit RISC-V [4] which make it attractive for use in edge AI applications, using the Open Hardware Foundation\u2019s CORE-V CV32E40Pv2 microcontroller as deployed in a real world design by two of the co-authors and their colleagues at <redacted>.  We have now ported IREE for the same platform.  IREE is a Linux Foundation experimental project, which uses lazy (\u201ccompiled\u201d) evaluation of AI models, with LLVM MLIR as an intermediate representation.  We give a short overview of how to run IREE on a bare metal microcontroller, and then assess what aspects of 32-bit RISC-V make it attractive for IREE.  We conclude by comparing the feasibility of using IREE instead of ExecuTorch and an assessment on the performance of both when carrying out AI inference.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HYYVCZ", "name": "Jeremy Bennett", "avatar": "https://cfp.riscv-europe.org/media/avatars/HYYVCZ_nWhCO2g.webp", "biography": "Jeremy Bennett is Chief Executive of Embecosm, an international open source consultancy specializing in compiler tool chains and AI tooling.  He is a former academic and author of the standard text book \"Introduction to Compiling Techniques: A first course using ANSI C, Lex and YACC\"  (McGraw-Hill 1990, 1995, 2003).  Dr Bennett holds an MA and PhD from Cambridge University.  He is aFellow of the British Computer Society, Fellow of the Royal Society of Arts, Member of the IET and a Chartered Engineer.", "public_name": "Jeremy Bennett", "guid": "e1e15f02-9ddd-5e84-9117-00ea0825615a", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HYYVCZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8BXPC9/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8BXPC9/", "attachments": []}, {"guid": "22c9b3fd-8fae-5838-928d-5ffefd33c537", "code": "VPNYEP", "id": 214, "logo": null, "date": "2026-06-09T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-214-from-profiling-to-performance-optimizing-small-language-models-on-risc-v-architectures", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VPNYEP/", "title": "From Profiling to Performance: Optimizing Small  Language Models on RISC\u2011V Architectures", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Small Language Models (SLMs) are increasingly critical for edge AI, yet their performance on RISC-V requires rigorous profiling to identify architectural bottlenecks. This work evaluates the performance of SLMs including Gemma3, Llama-3.2, Qwen-2.5, DeepSeek, and Phi-3.5 on the Tenstorrent Ascalon RISC-V Core. We developed a profiling methodology to analyze workload distribution, which revealed that Matrix Multiplication (MatMul) contributes ~90% of total compute across all evaluated models. Given the computational complexity of running full-model emulations, we extract these critical kernels for targeted benchmarking. Our implementation on the HAPS platform achieves significant performance leaps over standard baselines. FP32 execution, utilized for maximum precision, was optimized by transitioning from traditional SGEMM to a new high-performance implementation. Simultaneously, INT8 performance, targeted for efficient inference, was accelerated by migrating from standard RVV to a specialized IGEMM (with a VQDOT) implementation.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "FSJUJT", "name": "Rama Malladi", "avatar": null, "biography": "", "public_name": "Rama Malladi", "guid": "2b5fdeb3-4370-5e23-bb04-c098bc1c8ef8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FSJUJT/"}, {"code": "Q3CSBZ", "name": "Chip Kerchner", "avatar": "https://cfp.riscv-europe.org/media/avatars/Q3CSBZ_5h9qzHM.webp", "biography": "Sr. Staff Performance Engineer, Infrastructure - Tenstorrent", "public_name": "Chip Kerchner", "guid": "c45255e3-bc7e-502a-adc5-aa8478e0cacd", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Q3CSBZ/"}, {"code": "CB8LYV", "name": "Jose Arnau", "avatar": null, "biography": null, "public_name": "Jose Arnau", "guid": "62c7cc58-319f-5b1e-a82b-f5e6b9a2864f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CB8LYV/"}, {"code": "9KLNMW", "name": "Dongjie Xie", "avatar": null, "biography": null, "public_name": "Dongjie Xie", "guid": "cafe532e-18b5-5c4f-9286-325e2d8b3191", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9KLNMW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VPNYEP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VPNYEP/", "attachments": []}, {"guid": "ac304296-bf16-5630-be14-ff8dae4b77d0", "code": "A77QAQ", "id": 98, "logo": null, "date": "2026-06-09T14:20:00+02:00", "start": "14:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-98-priority-aware-scheduling-of-multi-model-multi-precision-dnn-inference-on-multi-cores-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A77QAQ/", "title": "Priority-Aware Scheduling of Multi-Model, Multi-Precision DNN Inference on Multi-Cores RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Efficient deployment of Deep Learning (DL) models on RISC-V-based multi-core platforms remains a significant challenge, especially when multiple models with heterogeneous structures and precision requirements must run concurrently. Existing frameworks offer optimized execution for single-model inference but lack support for multi-model scheduling, as well as priority-based resource allocation.\r\nIn this work, we extend the capabilities of such frameworks by formalizing the problem of multi-model, multiprecision inference scheduling on constrained many-core architectures like Parallel Ultra-Low Power (PULP). We define a scheduling space where multiple Deep Neural Networks (DNNs), varying in size, type and precision, compete for limited computing and memory resources. We introduce a simple, priority-aware scheduling layer that allocates cores and memory tiles across models, aiming to either minimize overall inference latency or find a tradeoff satisfying each model\u2019s deadline.\r\nTo demonstrate the effectiveness of our approach, we leverage the existing Deployment Oriented to memoRY (DORY) framework, and apply a greedy scheduling strategy. We conducted experiments with several models across several tasks and showed that even basic scheduling policies can significantly improve latency, core utilization, and memory efficiency over static and sequential baselines.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "7WAN78", "name": "PGA", "avatar": null, "biography": "", "public_name": "PGA", "guid": "ae59bb4c-a6cd-5bb6-ac87-1443cca187e0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7WAN78/"}, {"code": "HGSFVS", "name": "GARREAU", "avatar": null, "biography": null, "public_name": "GARREAU", "guid": "43d2bd1d-75f5-5bb0-b1a3-c7fcef83da25", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HGSFVS/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A77QAQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A77QAQ/", "attachments": []}, {"guid": "5dada2e6-daf0-5da3-95af-54f5e2bea998", "code": "PUPQJF", "id": 185, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/PUPQJF/-1_RGHK6ut_kMwEyoW.webp", "date": "2026-06-09T15:30:00+02:00", "start": "15:30", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-185-end-to-end-ml-graph-compiler-fused-with-triton-kernel-compiler-for-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PUPQJF/", "title": "End-to-End ML Graph Compiler Fused with Triton Kernel Compiler for RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "RISC-V AI acceleration faces a combinatorial explosion: hundreds of kernel variations across shapes, data types, and vendor platforms create unsustainable complexity. We present an end-to-end compilation solution fusing ML graph compilation with Triton DSL kernel compilation in a unified MLIR-based framework targeting RISC-V scalar (RV64IM) and vector (RVV) instruction sets.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "8KELAE", "name": "Hualin Wu", "avatar": "https://cfp.riscv-europe.org/media/avatars/8KELAE_1MIniy4.webp", "biography": "Co-founder & CTO of Terapines Technology. More than 15 years compiler design and development experience in Andes, S3 Graphics, Imagination and Terapines. Specialized in CPU, GPU, GPGPU, AI compilers based on MLIR, LLVM and GCC.", "public_name": "Hualin Wu", "guid": "72f89f90-063f-509b-a673-6d748d39b1fc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/8KELAE/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PUPQJF/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PUPQJF/", "attachments": []}, {"guid": "96ca7c8a-fb3b-5c29-82e4-10962cc58f65", "code": "CH97A7", "id": 352, "logo": null, "date": "2026-06-09T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-352-end-to-end-ai-compilation-for-risc-v-a-multi-level-optimization-approach", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CH97A7/", "title": "End-to-End AI Compilation for RISC-V: A Multi-Level Optimization Approach", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "With the rapid evolution of RISC-V extensions such as Vector, Matrix, and other custom instructions, RISC-V platforms are becoming capable of executing modern AI models. However, achieving high-performance deployment while maintaining a unified software stack across diverse extensions remains a key challenge. **This paper introduces Buddy Compiler, an end-to-end AI compiler designed to provide a unified interface for AI model integration, multi-level compilation optimizations, and extensible code generation targeting diverse RISC-V extensions.** Buddy Compiler adopts a multi-level architecture consisting of a frontend, middle-section, and backend, enabling reusable high-level optimizations while supporting specialized backends for RISC-V architectures. The frontend provides a graph infrastructure that interfaces with mainstream AI frameworks and converts imported models into a unified representation expressed with high-level MLIR dialects. The middle-section is built on MLIR and performs multi-level compilation optimizations, including operator fusion, memory access optimization, and vectorization. The backend implements dedicated MLIR dialects for RISC-V extensions, such as RVV, IME, AME, and Gemmini, and performs target-specific code generation. Through multi-level compilation, Buddy Compiler and its runtime system enable efficient deployment of AI models on RISC-V platforms, achieving performance comparable to manually optimized implementations such as llama.cpp.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3ESJ8E", "name": "Hongbin Zhang", "avatar": "https://cfp.riscv-europe.org/media/avatars/3ESJ8E_M230h23.webp", "biography": "Hongbin Zhang is a postdoctoral researcher at the Institute of Software, Chinese Academy of Sciences (ISCAS). He received his Ph.D. degree from the University of Chinese Academy of Sciences. His research focuses on AI system software and compiler technology. He leads the RuyiAI system software team at ISCAS. He launched the Buddy Compiler community and has served as a community mentor for the LFX RISC-V Mentorship and OSPP open-source programs. He is a member of the Technical Steering Committee (TSC) of RISC-V International and serves on the Governing Board of CHIPS Alliance.", "public_name": "Hongbin Zhang", "guid": "3eebde66-20ec-5a35-8a69-5084eac5f260", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3ESJ8E/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CH97A7/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CH97A7/", "attachments": []}, {"guid": "8f30712b-f6b7-5bb3-8c6d-1d5b47c531c6", "code": "HAZPKR", "id": 55, "logo": null, "date": "2026-06-09T16:00:00+02:00", "start": "16:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-55-code-size-reduction-by-advanced-near-addressing-modes", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HAZPKR/", "title": "Code size reduction by advanced near addressing modes", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "To enable debugging and calibration of real time systems, which are in interaction with the real plant, the software used on those systems often has a huge number of global variables. The huge number of global variables exceed the range addressable relative to the global pointer. Therefore, addressing these variables normally needs two instructions. Other CPU architectures commonly used in the real time control systems domain address these by various near addressing modes. This results in significant code size reductions and performance boost. This paper discusses different variants to add such near addressing features to the RISC-V ISA. The impact on the code size is evaluated with different representative workloads", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "ZAMZGQ", "name": "Kajetan N\u00fcrnberger", "avatar": null, "biography": "Before working in the automotive microcontroller area Kajetan N\u00fcrnberger has worked in the domain of safety critical aerospace software in an industrial and university environment. He is familiar with various CPU architectures and focused on the HW SW interface. Within Infineon he has contributed to the definition of different automotive controllers with respect to compute architecture SW and tooling.", "public_name": "Kajetan N\u00fcrnberger", "guid": "ae18e1e5-85a9-5d05-977a-8a968877aaa1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZAMZGQ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HAZPKR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HAZPKR/", "attachments": []}, {"guid": "7b957fd4-9b62-5fde-973e-911b33d88169", "code": "DMVSJ8", "id": 102, "logo": null, "date": "2026-06-09T16:10:00+02:00", "start": "16:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-102-atesor-a-multi-stage-llm-based-framework-for-autonomous-risc-v-software-porting", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DMVSJ8/", "title": "ATESOR: A Multi-Stage LLM-based Framework for Autonomous RISC-V Software Porting", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The RISC-V instruction set architecture (ISA) has seen rapid adoption over the past few years. Despite\r\nthis growth, the software ecosystem remains a major challenge to broader adoption. In contrast to x86 and ARM platforms, where precompiled binaries are widely available, RISC-V developers often face a significant software availability gap. Consequently, many packages, libraries, or applications must be built from source, requiring substantial expertise in build systems and target architectures. This process is largely manual and time-consuming, creating a significant barrier to widespread adoption of the RISC-V. To address this critical gap, this paper presents ATESOR, a multi-stage LLM-based framework for autonomous RISC-V software porting. The framework uses large language models to plan build requirements, compile packages, debug failures, and test generated binaries in RISC-V sandboxed environments. ATESOR supports both containerized RISC-V environment and native execution on RISC-V hardware such as the Banana Pi BPI-F3 and Milk-V Pioneer, provided by Cloud-V. ATESOR is trained on an internal dataset of more than 500 manually ported packages spanning build systems including CMake, Make, Ninja, and Go. For 100 CMake and Go-based packages, ATESOR demonstrated a 80% successful porting rate and experiment completed in approximately 1.5 hours, corresponding to an average porting time of about 54 seconds per package.", "description": "Software porting often requires deep expertise in target architectures, build systems, and toolchain integration, skills that are not widely available and impose significant manual effort\r\nand time costs. To address these challenges, this paper introduces ATESOR, multi-stage, LLM-based framework for autonomous RISC-V software porting. ATESOR uses LLMs with tool-use capabilities to execute a four-stage pipeline: (1) analysis and planning of architecture specific requirements, (2) autonomous generation of build plans and corresponding patches, (3) execution\r\nof the build in a RISC-V sandbox environment with automated issue resolution, and (4) verification of build steps and resulting binaries to ensure correctness and reproducibility. \r\n\r\nTo the best of our knowledge, ATESOR is the first LLM-based framework specifically designed for RISC\u0002V software porting. The system is trained on an internal dataset comprising over 500 manually ported\r\npackages, libraries, and applications, covering a variety of build systems including CMake, Make, and\r\nGo, enabling robust learning of architecture-specific\r\nbuild patterns and porting strategies.", "recording_license": "", "do_not_record": false, "persons": [{"code": "QT3KEB", "name": "Akif Ejaz", "avatar": "https://cfp.riscv-europe.org/media/avatars/QT3KEB_z6SSMiO.webp", "biography": "Akif has done in BS in Computer Engineering from ITU Lahore, Pakistan. He has 3+ years of experience in the semiconductor industry, specializing in RISC-V software.  His work spans multiple OSes, RTOSes, and microkernel RISC-V enablement. Currently working as Systems/Firmware Engineer at 10xEngineers. He recently joined the Eclipse Foundation as a ThreadX RTOS committer. He is also a core member and developer of Cloud-V platform.", "public_name": "Akif Ejaz", "guid": "bc8ef02a-5464-5994-882d-e03909e1b9b1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QT3KEB/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DMVSJ8/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DMVSJ8/", "attachments": []}], "Poster Island D": [{"guid": "dc2c774c-df88-5a0e-9239-773990347a3d", "code": "XMBLRH", "id": 91, "logo": null, "date": "2026-06-09T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-91-rise-and-yocto-building-a-risc-v-board-farm", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XMBLRH/", "title": "RISE and Yocto: Building a RISC-V Board Farm", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The Yocto Project is an open-source collaboration providing the tools which developers and organizations need to create custom embedded systems for a variety of architectures. This nominally includes both 32- and 64-bit RISC-V platforms, but until recently, official support and testing has been limited to emulated systems and a community-managed board-support layer (targeting hardware compliant with RVA22 and earlier) called meta-riscv. With the impending mass-availability of RVA23-compliant development boards and growing community interest, the RISE Project aims to ensure that Yocto is ready, by providing developer support for triaging RISC-V specific issues, while simultaneously improving test coverage and board support in the meta-riscv layer. To this end, a set of RVA22-based development boards have been deployed alongside some periodic build and test pipelines implemented with Forgejo and Labgrid, allowing early prototyping of longer-term validation workflows that Yocto and the community can build upon in the future. The foundation that this provides will ensure that as more organizations investigate RISC-V platforms for inclusion in their projects, a proven and reliable level of support will be waiting for them.", "description": "This talk will cover the latest in RISC-V support within the Yocto Project ecosystem, including the current state, future plans, and how the wider community can get involved. It could also serve as a BoF or partial BoF format with other speakers.", "recording_license": "", "do_not_record": false, "persons": [{"code": "L33CTT", "name": "Trevor Gamblin", "avatar": "https://cfp.riscv-europe.org/media/avatars/L33CTT_0BGX322.webp", "biography": "Trevor is an embedded systems developer at BayLibre, where he works on everything from the Yocto Project, to automation with CI and kernel development.", "public_name": "Trevor Gamblin", "guid": "99577e79-95ee-5381-b277-a6503ca628df", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/L33CTT/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XMBLRH/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XMBLRH/", "attachments": []}, {"guid": "1239cf87-03f7-5dad-8c31-addda3406e76", "code": "TAK7KZ", "id": 204, "logo": null, "date": "2026-06-09T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-204-deep-dive-into-upstream-risc-v-boot-chain", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TAK7KZ/", "title": "Deep Dive into Upstream RISC-V Boot Chain", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "While porting Freedesktop SDK to the EBC7700 for my FOSDEM'26 talk [1], I encountered some UEFI boot issues, which motivated me to dig deeper and uncover all the mysteries about the RISC-V boot chain. This talk looks in-depth at the RISC-V boot chain, both on the virtualised QEMU target, as well as practical hardware examples. Starting from their boot ROMs and how fusing/strapping may select the boot sources, usually containing some form of an SPL, like the one from U-Boot. Such SPL, in turn, loads U-Boot proper, which contains OpenSBI, implementing the Supervisor Binary Interface, in so-called FW_DYNAMIC form, meaning it does not require any platform-specific configuration parameters because all required information is passed by the previous booting stage at runtime. OpenSBI gets executed first and stays resident. The handover to the U-Boot boot loader, which implements the UEFI specification, marks the next boot stage. It may either directly load the Linux kernel, an optional initial RAM disk and the device tree, particularly useful during bring-up/development, or launch a UEFI boot loader like systemd-boot or GRUB. Handover to the Linux kernel marks the last and final stage in the boot chain. This talk not only looks at the software involved, but also how it may be built, deployed and debugged. As usual, I complete my talk with a live demo.\r\n\r\n[1] https://fosdem.org/2026/schedule/event/LX3NNU-upstream-embedded-linux-on-risc-v-sbcs", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "ZJKYLZ", "name": "Marcel Ziswiler", "avatar": "https://cfp.riscv-europe.org/media/avatars/ZJKYLZ_RQqFpR7.webp", "biography": "In 2024 Marcel Ziswiler joined Codethink as a software engineer. Before, he worked\r\nmore than 13 years at Toradex spearheading their Embedded Linux adoption. His\r\nintroduction of an upstream first policy led to being a top 10 U-Boot as well as Linux\r\nkernel Arm SoC contributor. He has broad experience in designing real-time and\r\nmobile applications for industrial systems. He holds a Certificate in Embedded Systems\r\nTechnologies from the UCI and a CS Master from the ETHZ. He spoke at several\r\ninternational conferences including all ELCs starting 2019 and FOSDEMs starting 2025.", "public_name": "Marcel Ziswiler", "guid": "50f0e8ee-0874-5b3c-9531-59366975a8c4", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZJKYLZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TAK7KZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TAK7KZ/", "attachments": []}, {"guid": "c13083fc-fc6b-53f9-bd43-d8c86a4a195d", "code": "9G3V9G", "id": 172, "logo": null, "date": "2026-06-09T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-172-implementation-of-open-ran-software-in-a-risc-v-platform", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9G3V9G/", "title": "Implementation of Open RAN software in a RISC-V platform", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The use of open-source stacks with the Open~RAN (Radio Access Network) architecture has been predominantly restricted to x86 and ARM architectures. This work presents the first successful porting of the srsRAN Project to RISC-V, targeting the low-cost Banana Pi BPI-F3 (SpacemiT K1 SoC)  board. We describe the cross-compilation toolchain, the removal of AVX/NEON dependencies in favour of a scalar C fallback, and a preliminary performance evaluation across two 5G NR FDD scenarios. Profiling with Linux perf identifies key data-parallel physical layer (PHY) bottlenecks, establishing primary targets for RVV 1.0 vectorisation. Results show that RISC-V offers promising real-time MIMO performance for a single user, even with a scalar fallback, suggesting that vectorisation will elevate it to highly competitive levels.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "S3CLBQ", "name": "Javier Hormigo", "avatar": null, "biography": "", "public_name": "Javier Hormigo", "guid": "b1d6b59c-e79f-5e42-9e7a-4a406e55f2b5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/S3CLBQ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9G3V9G/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9G3V9G/", "attachments": []}, {"guid": "6f0605f9-9fb9-5da3-805d-40cf9ddc1022", "code": "NJKQXQ", "id": 141, "logo": null, "date": "2026-06-09T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-141-openeuler-for-rva23-building-a-risc-v-server-os-with-ecosystem-partners", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NJKQXQ/", "title": "openEuler for RVA23: Building a RISC-V Server OS with Ecosystem Partners", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "In early 2026, the openEuler community, together with the Institute of Software, Chinese Academy of Sciences (ISCAS) and industry partners, released the openEuler 24.03 LTS SP3 for RISC-V server bring-up. The release aligns with ongoing RISC-V Server Platform efforts and adds practical support for RVA23-related vector and virtualization features across toolchains, user-space components, and the kernel. A central part of this work is RVCK (RISC-V Common Kernel), a shared kernel baseline designed to reduce duplicated per-vendor enablement work and improve reuse across platforms. This talk presents the engineering lessons behind that effort, including cross-vendor coordination, upstream collaboration, and the challenges of building a reusable software baseline for server-class RISC-V systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "YZZQUW", "name": "Jingwei Wang", "avatar": "https://cfp.riscv-europe.org/media/avatars/YZZQUW_2MATUen.webp", "biography": "Wang Jingwei is an engineer at the Institute of Software, Chinese Academy of Sciences and a member of the openEuler Technical Committee. He is a RISC-V advocate focused on building the RISC-V software ecosystem based on openEuler and related Linux distributions.", "public_name": "Jingwei Wang", "guid": "45d943d8-1e3e-57f5-b05d-25632f654f93", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YZZQUW/"}, {"code": "CRDTNB", "name": "Sheng Qu", "avatar": null, "biography": "", "public_name": "Sheng Qu", "guid": "636573b7-dfb3-5ed4-afb4-ca0fd4db9b50", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CRDTNB/"}, {"code": "3TY3VN", "name": "YANJUN WU", "avatar": "https://cfp.riscv-europe.org/media/avatars/3TY3VN_zcvjIJw.webp", "biography": "Chief Engineer of Institute of Software, Chinese Academy of Sciences", "public_name": "YANJUN WU", "guid": "70167bc1-8155-5cac-9b3d-db5acdfc36cc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3TY3VN/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NJKQXQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NJKQXQ/", "attachments": []}, {"guid": "54064af4-8e87-582e-95a0-12a7412857e5", "code": "L98NW8", "id": 82, "logo": null, "date": "2026-06-09T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-82-openkylin-empowering-the-risc-v-ai-ecosystem", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/L98NW8/", "title": "openKylin: Empowering the RISC-V AI Ecosystem", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "In the AI era, the RISC-V architecture represents a transformative force due to its inherent modularity and extensibility. However, the transition from hardware potential to a production-ready AI ecosystem is fraught with challenges, primarily the fragmentation of hardware-software interfaces and the relative immaturity of the AI software ecosystem. As a leading Tier-1 operating system community, openKylin serves as the critical architectural glue, addressing these obstacles by empowering the RISC-V AI landscape through foundational OS construction, software stack optimization, and application innovation. By harmonizing hardware diversity with a unified software infrastructure, openKylin not only lowers the barrier to AI deployment but also defines a scalable roadmap for RISC-V across multi-scenario environments, transforming RISC-V into a premier, open-standard architecture for the global AI revolution.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "QEMQBE", "name": "Wenzhu Wang", "avatar": "https://cfp.riscv-europe.org/media/avatars/QEMQBE_l8t9sEC.webp", "biography": "A member of the openKylin Technical Committee, where he leads the RISC-V and RISC-V AI SIGs. An active contributor to the global RISC-V community, he is dedicated to advancing the RISC-V software ecosystem and hardware-software co-design within openKylin. His research interests focus on next-generation operating systems and high-performance RISC-V implementations for AI workloads.", "public_name": "Wenzhu Wang", "guid": "6c2ba39b-c4b8-5cbb-890c-e98da99334da", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QEMQBE/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/L98NW8/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/L98NW8/", "attachments": []}, {"guid": "8f726f21-04c6-57eb-958c-0e204888a3df", "code": "K9TL88", "id": 69, "logo": null, "date": "2026-06-09T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-69-ruyisdk-package-manager-a-unified-package-management-and-development-environment-for-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/K9TL88/", "title": "RuyiSDK Package Manager - A Unified Package Management and Development Environment for RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "New RISC-V CPU cores are released every year, and while these cores typically conform to standardized RISC-V ISA profiles, vendors frequently introduce additional proprietary extensions. This growing diversity makes it difficult for developers to accurately determine the exact instruction sets supported by a specific CPU core, thereby complicating the selection of appropriate toolchains, firmware, and operating system images. The RuyiSDK Package Manager addresses this challenge by aggregating information on RISC-V CPUs, MCUs, and development boards together with their corresponding toolchains, firmware, and system images. It establishes a comprehensive mapping between CPU architectures, development boards, and required software resources. This mapping is maintained in a structured packages index, which provides a unified, metadata-driven representation of RISC-V hardware and software resources, along with associated download links. This paper presents the overall architecture and design of the RuyiSDK Package Manager, focusing on three core components: package management, virtual environment isolation, and device provisioning. The system currently supports most commercially available RISC-V development boards. Beyond toolchain integration, it lays the foundation for IDE integration and other developer utilities. By streamlining access to software resources and standardizing development workflows, the system lowers the barrier to entry for RISC-V software development, facilitates developer onboarding, and improves visibility into software support across heterogeneous RISC-V platforms.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EZ3QYW", "name": "Weilin Cai", "avatar": "https://cfp.riscv-europe.org/media/avatars/EZ3QYW_CI3kbXV.webp", "biography": "", "public_name": "Weilin Cai", "guid": "65df2538-8b23-5a1a-9bef-87883d50ddd8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EZ3QYW/"}, {"code": "KNTSHY", "name": "Yunxiang Luo", "avatar": "https://cfp.riscv-europe.org/media/avatars/KNTSHY_n86SpHx.webp", "biography": "Email: luoyunxiang@iscas.ac.cn\r\nIntelligent Software Research Center (ISRC), Institute of Software, Chinese Academy of Sciences (ISCAS)", "public_name": "Yunxiang Luo", "guid": "b618a00a-b794-5236-b4c3-63f3604bfcc9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KNTSHY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/K9TL88/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/K9TL88/", "attachments": [{"title": "poster", "url": "/media/eu-summit-2026/submissions/K9TL88/resources/1_Ruyi_Package_Manag_8x3iL0V.pdf", "type": "related"}]}, {"guid": "e7ed2999-f93d-5280-ae87-1dd9af15b20b", "code": "XDQWMR", "id": 68, "logo": null, "date": "2026-06-09T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-68-sail-riscv-wasm-a-browser-native-risc-v-toolchain-and-debugging-workbench", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XDQWMR/", "title": "Sail-RISCV-WASM A Browser-Native RISC-V Toolchain and Debugging Workbench", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper presents Sail-RISCV-WASM, which addresses three common limitations of existing browser-based RISC-V tools: fragmented capabilities, limited configurability, and disconnected build/debug pipelines. The system uses `sail-riscv` as its semantic baseline and compiles it to WebAssembly, forming a three-layer architecture in a pure browser environment: a Sail decode/execute layer, a toolchain layer (gas/ld/objdump), and a metadata layer based on the RISC-V UDB. Based on this architecture, the paper defines two core workflows. The first is configuration-sensitive online encode/decode with instruction metadata navigation for cross-configuration behavior comparison. The second is an in-browser assemble-to-ELF, execute, and interactive debugging loop, supporting instruction-level stepping, source-line stepping, synchronized source/disassembly views, and register/memory tracing. Results show that the system provides a complete single-page flow from exploration to build to diagnosis, with strong extension coverage and configuration flexibility.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "UVDGJA", "name": "Mingzhu Yan", "avatar": null, "biography": "", "public_name": "Mingzhu Yan", "guid": "c842762e-d281-5fe0-bd6b-d031940076c9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UVDGJA/"}, {"code": "KNTSHY", "name": "Yunxiang Luo", "avatar": "https://cfp.riscv-europe.org/media/avatars/KNTSHY_n86SpHx.webp", "biography": "Email: luoyunxiang@iscas.ac.cn\r\nIntelligent Software Research Center (ISRC), Institute of Software, Chinese Academy of Sciences (ISCAS)", "public_name": "Yunxiang Luo", "guid": "b618a00a-b794-5236-b4c3-63f3604bfcc9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KNTSHY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XDQWMR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XDQWMR/", "attachments": [{"title": "poster", "url": "/media/eu-summit-2026/submissions/XDQWMR/resources/3_Sail-RISCV-WASM_A__Il0I59V.pdf", "type": "related"}]}, {"guid": "052ed75b-a3a4-58d8-8e47-559658b3df23", "code": "9GW78U", "id": 339, "logo": null, "date": "2026-06-09T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-339-roriv-porting-the-rtos-rodos-on-risc-v-for-future-satellite-missions", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9GW78U/", "title": "RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This work implements two ports of the Real-Time Operating System RODOS on RISC-V. Specifically, the RV32E_ZICSR ISA variant is supported for QEMU. This enables easy development and testing. The other port targets the BeagleV-Ahead board, which is an open-source RISC-V single board computer. RODOS provides benchmarks that give a rough estimate of the performance. These benchmarks are carried out on the BeagleV-Ahead board and compared to results of already existing ports. Our benchmarks show that this RISC-V port on the BeagleV-Ahead is about 20\\% faster than other boards like an STM32F4. This shows that RISC-V is a promising platform for future applications of RODOS.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EYMWSH", "name": "Jonathan Hager", "avatar": "https://cfp.riscv-europe.org/media/avatars/EYMWSH_z6mOXWZ.webp", "biography": "", "public_name": "Jonathan Hager", "guid": "6dc28d50-4553-5d9a-9c4f-cd2c510af428", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EYMWSH/"}, {"code": "USBHZD", "name": "Andreas Theiner", "avatar": null, "biography": "", "public_name": "Andreas Theiner", "guid": "cfe99341-987a-59fc-b67c-94055b0c0062", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/USBHZD/"}, {"code": "AAV8QY", "name": "Matthias Jung", "avatar": "https://cfp.riscv-europe.org/media/avatars/AAV8QY_vDHNrsT.webp", "biography": "He received the Diploma and PhD degree in electrical engineering from the Technische Universit\u00e4t Kaiserslautern, Germany, in 2011 and 2017, respectively. From 2011 to 2017 he was a researcher at the Microelectronic Systems Design Research Group of RPTU Kaiserslautern. Since 2017 he is with the Fraunhofer Institute for Experimental Software Engineering in Kaiserslautern as Expert Engineer for virtual hardware engineering. In 2018, he received the EDAA Outstanding Dissertation Award for this work. At Fraunhofer IESE in Kaiserslautern, he has been leading many research and industrial projects in the area of embedded systems since 2017 and has published more than 100 papers in relevant journals and conference proceedings. Since 2023, he is professor at the University of W\u00fcrzburg. Matthias Jung's scientific focus is on embedded and autonomous systems, especially with a focus on memory architectures, functional safety, and virtual product development of embedded systems through virtual platforms and simulations.", "public_name": "Matthias Jung", "guid": "55ca3b8a-4681-561f-88ed-a49a66a56925", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AAV8QY/"}, {"code": "QFEVR7", "name": "Sergio Montenegro", "avatar": null, "biography": null, "public_name": "Sergio Montenegro", "guid": "aced0087-1730-54b3-b493-725798cc1105", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QFEVR7/"}, {"code": "3LBMCD", "name": "Andreas N\u00fcchter", "avatar": "https://cfp.riscv-europe.org/media/avatars/3LBMCD_dANXO0E.webp", "biography": "", "public_name": "Andreas N\u00fcchter", "guid": "ae8e90a4-99d0-5288-bee0-9586082c8e31", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3LBMCD/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9GW78U/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9GW78U/", "attachments": []}, {"guid": "d6649b88-782e-5fa6-86ea-6983c23b7ba2", "code": "YAEZRU", "id": 37, "logo": null, "date": "2026-06-09T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-37-revisiting-x86-64-to-risc-v-binary-translation-a-hardware-software-co-design-path", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YAEZRU/", "title": "Revisiting x86-64 to RISC-V Binary Translation: A Hardware/Software Co-Design Path", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "RISC-V is rapidly emerging as an open and extensible ISA, yet its adoption in desktop and server environments remains constrained by the dominance of the x86-64 software ecosystem. Dynamic binary translation (DBT) provides a practical mechanism for executing legacy x86-64 binaries on RISC-V without source code, but purely software-based DBT often incurs substantial overhead. In this work, we investigate a hardware/software co-designed approach for user-level x64-to-RV64 translation. We begin with a fine-grained characterization of runtime instruction behavior from SPEC CPU 2017 benchmarks, and extract micro-operation (\u03bcop) information for different instruction variants on a representative x86 microarchitecture. By correlating dynamic execution profiles with \u03bcop-level complexity, we introduce a quantitative model of semantic inflation, which exposes the semantic gap introduced by cross-ISA translation by discounting the inherent execution complexity of CISC instructions. This model enables us to systematically identify instruction variants that exhibit disproportionate expansion and reveals the underlying causes of this bloat. Based on these insights, we propose targeted hardware extensions to mitigate translation overhead. We implement the proposed approach in a Box64-based prototype and evaluate it through QEMU-based simulation. Experimental results demonstrate a significant reduction in the number of translated instructions, indicating a practical path toward near-native cross-ISA execution efficiency.", "description": "A semantic-inflation-driven hardware\u2013software co-design approach for x64-to-RV64 binary translation.", "recording_license": "", "do_not_record": false, "persons": [{"code": "SAUZMK", "name": "Xieyuan Wu", "avatar": null, "biography": "A master's student at Tsinghua University", "public_name": "Xieyuan Wu", "guid": "b3179752-5c0e-539b-a946-91392d87e1a8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SAUZMK/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YAEZRU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YAEZRU/", "attachments": []}, {"guid": "b26df540-9769-5686-9d02-833fecf315f7", "code": "7FMCFX", "id": 157, "logo": null, "date": "2026-06-09T14:00:00+02:00", "start": "14:00", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-157-unlocking-high-performance-avx2-emulation-with-rvv-1-0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7FMCFX/", "title": "Unlocking High-Performance AVX2 Emulation with RVV 1.0", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The x86-64 instruction set has a long history of backwards compatibility, and a lot of performance-intensive software, most of which may never be ported to RISC-V. While existing emulators support the Advanced Vector Extensions (AVX) extension, none do so using the RISC-V Vector (RVV) extension directly. We implemented AVX and AVX2 support in Placeholder using RVV 1.0 and compare performance with existing implementations that don't utilize RVV 1.0. Additionally, we measure the performance benefit of enabling AVX2 support in benchmarks and compare it with the performance benefit in x86-64 hardware.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "Q7DETG", "name": "Paris Oplopoios", "avatar": null, "biography": "", "public_name": "Paris Oplopoios", "guid": "679f3ef4-cb08-5382-9d22-69ed2b56de2f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Q7DETG/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7FMCFX/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7FMCFX/", "attachments": []}, {"guid": "a3466bb8-45bd-5f5c-a6c8-3122b42c411b", "code": "RGDVRL", "id": 142, "logo": null, "date": "2026-06-09T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-142-beyond-the-basics-elevating-eclipse-threadx-to-a-first-class-rtos-for-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RGDVRL/", "title": "Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "As RISC-V moves from experimental silicon to mass-market industrial applications, the availability of proven, safety-certified Real-Time Operating Systems (RTOS) is a key enabler for adoption. Eclipse ThreadX (formerly Azure RTOS) has long been a cornerstone of the embedded industry. Yet, its immature support for the RISC-V ISA, particularly 64-bit implementations, remained a barrier for high-performance adoption.\r\n\r\nIn this session, you will learn how 10xEngineers, in collaboration with the Eclipse ThreadX project team, brought first-class RISC-V support to the ThreadX kernel. You will go on a deep dive into the architectural challenges of porting the kernel's core components to both RV32 and RV64, including context switching, interrupt nesting, and timer management tailored for the RISC-V privileged architecture. You will also explore the practical enablement of this port on the SpacemiT K1 SoC (Banana Pi BPI-F3), bridging the gap between virtual prototyping in QEMU and physical hardware deployment. Finally, you will gain insights into the low-level kernel modifications required for RISC-V compliance and discover a roadmap for deploying ThreadX in the next generation of RISC-V embedded systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "LEXHEZ", "name": "Fr\u00e9d\u00e9ric Desbiens", "avatar": "https://cfp.riscv-europe.org/media/avatars/LEXHEZ_rNju7b8.webp", "biography": "Fr\u00e9d\u00e9ric Desbiens manages the Embedded and IoT programs at the Eclipse Foundation, Europe's largest open-source organisation. In this role, he helps the community drive innovation at the intersection of devices, software, and open collaboration. A passionate advocate for open source, Fr\u00e9d\u00e9ric works with developers, companies, and researchers to advance the Internet of Things and edge computing. He is also the project lead for Eclipse ThreadX, the first open source real-time operating system (RTOS) certified for safety-critical applications.\r\n\r\nBefore joining the Eclipse Foundation, he held various technical and leadership roles at Pivotal, Cisco, and Oracle. Fr\u00e9d\u00e9ric holds an MBA in Electronic Commerce, a BASc in Computer Science, and a BEd from Universit\u00e9 Laval in Qu\u00e9bec City, Canada.\r\n\r\nHe is the author of Building Enterprise IoT Solutions using Eclipse IoT Technologies: An Open-Source Approach to Edge Computing (Apress, 2022).", "public_name": "Fr\u00e9d\u00e9ric Desbiens", "guid": "75395b25-8d23-5c0a-9298-4761e38244d9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/LEXHEZ/"}, {"code": "QT3KEB", "name": "Akif Ejaz", "avatar": "https://cfp.riscv-europe.org/media/avatars/QT3KEB_z6SSMiO.webp", "biography": "Akif has done in BS in Computer Engineering from ITU Lahore, Pakistan. He has 3+ years of experience in the semiconductor industry, specializing in RISC-V software.  His work spans multiple OSes, RTOSes, and microkernel RISC-V enablement. Currently working as Systems/Firmware Engineer at 10xEngineers. He recently joined the Eclipse Foundation as a ThreadX RTOS committer. He is also a core member and developer of Cloud-V platform.", "public_name": "Akif Ejaz", "guid": "bc8ef02a-5464-5994-882d-e03909e1b9b1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QT3KEB/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RGDVRL/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RGDVRL/", "attachments": []}, {"guid": "908ff491-8739-5285-946c-82e84ccd932e", "code": "SFZSB9", "id": 78, "logo": null, "date": "2026-06-09T14:20:00+02:00", "start": "14:20", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-78-rust-on-risc-v-alignment-and-friction-at-the-hardware-software-boundary", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SFZSB9/", "title": "Rust on RISC-V: Alignment and Friction at the Hardware-Software Boundary", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Rust is increasingly discussed in embedded and safety-aware systems, yet it remains uncommon in serious RISC-V projects. For teams working in C and assembly, the question is whether Rust meaningfully complements the RISC-V ecosystem at all.\r\n\r\nThis talk offers an engineering-level exploration of that question. Rather than a migration guide or code-heavy tutorial, it examines where Rust aligns with low-level RISC-V work - and where real friction remains.\r\n\r\nTopics include:\r\n- How Rust\u2019s abstractions translate in bare-metal contexts,\r\n- Toolchain realities, including LLVM constraints and custom ISA extension workflows,\r\n- Practical limits around vector extension,\r\n- Incremental adoption strategies for mixed C/Rust systems,\r\n- Build reproducibility and multi-target configuration,\r\n- Off-hardware testing and separation of logic from hardware layers.\r\n\r\nThe goal is to give engineers enough practical insight to judge whether Rust has a place in their RISC-V workflow. This is an exploratory talk, not a language tutorial - no prior Rust experience is required or assumed.", "description": "This session is aimed at hardware and low-level software engineers working in C and assembly who are curious about Rust but skeptical of its practical fit in RISC-V projects.\r\n\r\nThe talk does not attempt to teach the language. Instead, it provides a structured evaluation of where Rust currently stands in relation to RISC-V workflows. The focus is on architectural and tooling considerations rather than syntax or implementation details.\r\n\r\nThe goal is to support informed technical decision-making rather than promote adoption. As RISC-V systems grow in complexity, the choice of language and tooling becomes a practical engineering decision. This talk frames that decision in concrete terms.", "recording_license": "", "do_not_record": false, "persons": [{"code": "SNKFYT", "name": "David de Rosier", "avatar": "https://cfp.riscv-europe.org/media/avatars/SNKFYT_RxUD2wk.webp", "biography": "David is a software engineer and system architect working in correctness - and latency-critical systems. His background spans academic research in parallel computing, low-level programming in RISC-V and MIPS assembly and embedded C and Rust, and active involvement in both the Rust and RISC-V communities as a speaker and mentor. He is a member of the Safety Critical Rust Consortium.", "public_name": "David de Rosier", "guid": "8197e9bd-0034-56ab-80ac-c00cdef9d404", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SNKFYT/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SFZSB9/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SFZSB9/", "attachments": []}, {"guid": "35f46e7e-c7bf-57b2-8d38-51afdb72eba4", "code": "33798M", "id": 30, "logo": null, "date": "2026-06-09T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-30-creator-a-risc-v-web-simulator-based-on-sail-specification-language", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/33798M/", "title": "CREATOR: A RISC-V web simulator based on Sail specification language", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper introduces a new version of the CREATOR tool. CREATOR is a web-based simulator that lets users code, compile, and execute assembly-language programs. The architectures that can be simulated in CREATOR are MIPS and RISC-V. Until now, CREATOR allowed the simulation of the RISC-V architecture with a reduced instruction set (RISC-V IMFD), but this has changed thanks to Sail. Sail is an instruction specification language used by RISC-V to define both its architecture and the entire instruction set. This language has enabled the development of a complete RISC-V architecture simulator for web environments, without requiring any installation. It also allows users to develop their own instructions for research purposes or to adapt the implementation of existing ones for their own industrial purposes. This simulator also integrates an editable cache memory module into its architecture to explore the functioning of the architecture in greater depth. The tool includes a multi-file code-editing module that allows users to import, export, and edit assembly-language programs; an integrated compiler; and a program-debugging module during execution. To develop this simulator for web environments, the simulator implementation in Sail was exported to a high-level language (C), and the exported code was transpiled with Emscripten to generate executable code for web environments while maintaining performance, as if it were a native application.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "WJRYAE", "name": "Juan Carlos Cano Resa", "avatar": "https://cfp.riscv-europe.org/media/avatars/WJRYAE_SR8Rc3Q.webp", "biography": "", "public_name": "Juan Carlos Cano Resa", "guid": "75222d5d-1ba9-5702-85ea-2faf1d3ea0af", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WJRYAE/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/33798M/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/33798M/", "attachments": []}, {"guid": "a2df8dec-396e-560f-82dd-4ea97468708a", "code": "8ALWHG", "id": 374, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/8ALWHG/superscalar_4YAcjuP_MRnM6eK.webp", "date": "2026-06-09T15:50:00+02:00", "start": "15:50", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-374-freess-a-web-based-educational-simulator-for-a-risc-v-inspired-superscalar-processor-tomasulo-style", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8ALWHG/", "title": "FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor Tomasulo-Style", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "FREESS (Free Educational Superscalar Simulator) is an open-source teaching environment for instruction-level parallelism in a RISC-V-inspired superscalar processor. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering in a Tomasulo-style machine. The simulator exposes the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation, so the evolution of the hardware state can be followed on screen and reproduced on paper. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed easily, enabling direct comparison among alternative superscalar organizations. The tool has supported Advanced Computer Architecture teaching for about fifteen years and is publicly available on GitHub.", "description": "Educational Tool for SUPERSCALAR RISC-V teaching.\r\nAvailable (and runnable) in GitHub or standalone in portable C.", "recording_license": "", "do_not_record": false, "persons": [{"code": "789VLD", "name": "Roberto Giorgi", "avatar": "https://cfp.riscv-europe.org/media/avatars/789VLD_4qwKdNG.webp", "biography": "Roberto Giorgi is an Associate Professor in the Department of Information Engineering at the University of Siena, Italy (qualified for Full Professorship). He received his PhD in Computer Engineering and his Master\u00e2\u20ac\u2122s in Electronics Engineering, both summa cum laude, from the University of Pisa. He coordinated the 4-year TERAFLUX (Future and Emerging Technologies) and 3-year AXIOM (H2020) projects, was a Work Package leader in Embedded Reconfigurable Architecture, and contributed to HiPEAC and SARC. He participated in ChARM, developing software for ARM-based embedded system performance evaluation. Selected as an ICT/HPC expert by the European Commission, he has authored over 160 scientific papers. His research focuses on Computer Architecture, including Embedded Systems, Multiprocessors, Memory Performance, Workload Characterization, and Reconfigurable Computing. He is a Lifetime Member of ACM and a Senior Member of IEEE and the IEEE Computer Society.", "public_name": "Roberto Giorgi", "guid": "dcd3f311-eedd-56f9-8e2e-6ca755ddafa5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/789VLD/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8ALWHG/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8ALWHG/", "attachments": []}], "Devzone": [{"guid": "2d331c19-e5b6-5a97-9c4a-759981bcc18b", "code": "AVMPST", "id": 133, "logo": null, "date": "2026-06-09T10:30:00+02:00", "start": "10:30", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-133-risc-v-powered-quantum-sensor", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/AVMPST/", "title": "RISC-V POWERED QUANTUM SENSOR", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "Demo proposal presents a RISC-V powered quantum sensor designed for ultra-precise magnetic field measurements even at room temperature using nitrogen-vacancy (NV) center defects in diamond. Quantum magnetometers have a wide range of applications including localization, microscopy, and system control. With RISC-V processor being integrated into the developed system, the aim is to achieve world\u2019s most efficient sensor readout and unlock quantum sensing potential for widespread adoption. For the demonstrator, generic event-based architecture was developed, where the RISC-V plays a vital role in coordinating the hardware and provides a foundation for future miniaturization of the sensor electronics and readout ASIC design. The developed prototype enables pulsed optically detected magnetic resonance (ODMR) measurements, that provide significantly higher precision and improved experimental control in comparison to continuous-wave (CW) techniques. The goal is to showcase RISC-V powered quantum sensor with EDI (Institute of Electronics and Computer Science, Latvia) integrated setup incorporating analogue electronics for generating and sampling microwaves, digital electronics for pre-processing and control, and application-level software for users. However, even if hardware issues arise, the live demonstrator will showcase the complete RISC-V-powered quantum sensing system using the PolarFire SoC Video Kit based sensor platform. Open-source RISC-V processor grants more freedom for future ASIC implementation of the measurement system.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BZJVMS", "name": "agata.kusnina", "avatar": "https://cfp.riscv-europe.org/media/avatars/BZJVMS_PYvsOEY.webp", "biography": "", "public_name": "agata.kusnina", "guid": "dcff8530-63ae-5aba-a9bc-1b46f9228fcb", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BZJVMS/"}, {"code": "7TFRE9", "name": "Marks", "avatar": null, "biography": "", "public_name": "Marks", "guid": "c3d16bfe-c706-5bcb-940c-8e439fc4d64b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7TFRE9/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/AVMPST/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/AVMPST/", "attachments": []}, {"guid": "aad92f09-7fbe-57d6-bce4-d30c4d4c3fbb", "code": "Q97WYM", "id": 217, "logo": null, "date": "2026-06-09T11:00:00+02:00", "start": "11:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-217-libero-a-flexible-lightweight-gdb-based-visualization-tool-for-risc-v-vector-extensions", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/Q97WYM/", "title": "LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "The RISC-V Vector (RVV) extension introduces powerful yet complex semantics for data-parallel execution, including dynamically sized vectors, per-lane masking, and flexible element widths and groupings. While these features offer high performance and portability, they also complicate debugging, as existing tools, such as GDB, do not present RVV registers in a configuration-aware manner. Consequently, raw and verbose register dumps must be manually interpreted relative to the current vector register state. With register widths of up to 65,536 bits this quickly becomes impractical, making it difficult to understand effects of individual instructions and spot values of interest efficiently.\r\n\r\nThis demo presents LIBERO, a lightweight visualization tool integrated directly into GDB through its Python API. LIBERO augments GDB\u2019s Text User Interface (TUI) with a custom register view that continuously displays vector contents alongside the relevant configuration state during program execution. LIBERO allows users to select which vector registers to display and automatically renders them based on the width specified in the status register. By embedding these capabilities into GDB, LIBERO enables developers to reason about RVV code more efficiently while preserving the familiar GDB workflow.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EKB7FY", "name": "Jakob Sch\u00e4ffeler", "avatar": "https://cfp.riscv-europe.org/media/avatars/EKB7FY_xNXw81F.webp", "biography": "", "public_name": "Jakob Sch\u00e4ffeler", "guid": "f1db1715-92bb-5d6b-a1bb-918a5f5cc812", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EKB7FY/"}, {"code": "MEBVPT", "name": "Carsten Trinitis", "avatar": null, "biography": "Carsten is Professor for Computer Architecture and Operating Systems at TU Munich's Heilbronn campus.\r\n\r\nCarsten is also deputy spokesman of Gesellschaft f\u00fcr Informatik (GI)'s special interest group on \"Ethics in Informatics\", GI liaison lecturer at TU Munich, and member of the Zuse Society's board of directors.\r\n\r\nFrom 2013 to 2019 he was elected member of GI's board of directors.\r\n\r\nHis research interests comprise high performance computer architectures, microprocessor architectures, multi- and many-core architectures as well as the adaptation of numerical simulation codes to these architectures, with a focus on RISC-V.", "public_name": "Carsten Trinitis", "guid": "52e85d0e-97e1-5fbd-bb52-d075ef9e220c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MEBVPT/"}, {"code": "VT3TAD", "name": "Kun Qin", "avatar": null, "biography": "", "public_name": "Kun Qin", "guid": "26d33f2b-ae3b-51ff-95c9-e6fad705ddb7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VT3TAD/"}, {"code": "HB9CRX", "name": "Nima Baradaran Hassanzadeh", "avatar": null, "biography": null, "public_name": "Nima Baradaran Hassanzadeh", "guid": "91367bfa-e140-5132-9183-acc246d48602", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HB9CRX/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/Q97WYM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/Q97WYM/", "attachments": []}, {"guid": "0ecb59cc-d658-531c-98f5-49c006ab0d2b", "code": "YQDVJU", "id": 117, "logo": null, "date": "2026-06-09T13:00:00+02:00", "start": "13:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-117-ml-kem-on-a-22-nm-asic-protected-unprotected-and-hardware-accelerated-implementations", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YQDVJU/", "title": "ML-KEM on a 22\u202fnm ASIC: Protected, Unprotected, and Hardware-Accelerated Implementations", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "Post-Quantum Cryptography is becoming a key building block for future secure systems, as quantum computers threaten widely deployed public-key cryptographic algorithms. In response, the NIST standardization process has selected new quantum-resistant schemes, among which ML-KEM plays a central role for key establishment. Deploying these algorithms efficiently on embedded processors is therefore a critical step toward practical adoption, particularly because embedded systems face strict constraints in terms of computational resources, memory footprint, and energy consumption. At the same time, they are more exposed to physical threats, making resistance to side-channel attacks a key requirement. These constraints make RISC-V especially attractive: its open instruction set and extensibility allow experimentation with software optimizations as well as hardware acceleration for PQC. To explore these aspects, CEA has developed VASCO3, a 22 nm ASIC chip designed to experimentally evaluate PQC implementations and side-channel countermeasures directly on silicon. The chip integrates a RISC-V\u2013based System-on-Chip (SoC) together with several ML-KEM hardware accelerators, enabling the study of different hardware/software partitioning strategies around an embedded RISC-V CPU. In this demonstration, we present a comprehensive exploration of ML-KEM. We first showcase a pure software implementation running on the RISC-V, then progressively introduce hardware acceleration and a fully dedicated ML-KEM accelerator. We also demonstrate protected implementations based on first-order masking, including a masked software version and a masked hardware-assisted design.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BT8HDF", "name": "Stefano Di Matteo", "avatar": "https://cfp.riscv-europe.org/media/avatars/BT8HDF_mdi9SnE.webp", "biography": "Stefano Di Matteo received his M.Sc. (2019) and Ph.D. (2023) respectively in Electronic Engineering and Information Engineering from the University of Pisa. He is currently a tenure-track researcher in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction Set Extensions for PQC", "public_name": "Stefano Di Matteo", "guid": "d588454d-5a07-56ea-883a-2b426ee778aa", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BT8HDF/"}, {"code": "TUKUZV", "name": "Emanuele Valea", "avatar": null, "biography": "", "public_name": "Emanuele Valea", "guid": "45210441-fc95-5da8-aab7-b5f818a8d404", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TUKUZV/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YQDVJU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YQDVJU/", "attachments": []}, {"guid": "c3cb9a9f-c983-51d2-9576-2c1e14db2e6d", "code": "FZ3AYJ", "id": 53, "logo": null, "date": "2026-06-09T13:30:00+02:00", "start": "13:30", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-53-osoc-mambo-robot-risc-v-processor-chip-showcase-using-open-source-ip-eda-and-pdk", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FZ3AYJ/", "title": "OSOC Mambo Robot: RISC-V processor chip showcase using open-source IP, EDA, and PDK", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "The Mambo XiaoXin Robot uses the StarrySky C2-Pico open-source development board as its core controller, paired with ASR-PRO voice recognition module, forming a compact robotic system that integrates motion control, voice interaction, and intelligent response.\r\nThe StarrySky C2-Pico board is equipped with the RetroSoC chip independently developed by the ECOS(EDA, Chip, One Student One Chip, System) team. This chip is fabricated using the ICSprout 55 nm open-source PDK process flow and represents a technological achievement that combines the open instruction set RISC-V, open-source EDA, open-source IP, and open-source PDK. Its functionality and performance are benchmarked against the low- to mid-end products of ST\u2019s F1 series.\r\nInternally, the chip integrates the classic lightweight open-source RISC-V processor core PicoRV32, fully implementing the RV32IMC instruction set architecture, with a maximum clock frequency of up to 72 MHz. The chip includes 128 KB of on-chip SRAM, while the board further expands storage with 8 MB PSRAM and 16 MB SPI Flash, forming a multi-level memory system. In addition, the chip integrates a rich set of open-source peripheral drivers, including UART, SPI, I2C, PS/2, PWM, GPIO, timers, and more, meeting diverse embedded development requirements.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CKAT8F", "name": "Xiaoke Su", "avatar": "https://cfp.riscv-europe.org/media/avatars/CKAT8F_XRGfkWb.webp", "biography": "", "public_name": "Xiaoke Su", "guid": "664d6d48-1f6e-5994-b0b0-09988d77a5f1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CKAT8F/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FZ3AYJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FZ3AYJ/", "attachments": []}, {"guid": "94036816-516d-5ada-8517-4109d825d737", "code": "78MPFT", "id": 227, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/78MPFT/REPTILES_blue_font_HSK0XXD_Xj_ePxw75o.webp", "date": "2026-06-09T14:00:00+02:00", "start": "14:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-227-reptiles-repeated-tiles-of-sargantana", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/78MPFT/", "title": "REPTILES: Repeated tiles of Sargantana", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "This demo introduces Reptiles - Repeated Tiles of Sargantana, an open-source RISC-V multicore architecture designed to support research in HPC systems. Reptiles builds upon the OpenPiton manycore framework by integrating multiple Sargantana RISC-V cores and enhancing the memory hierarchy and interconnection network to improve scalability and performance. The goal is to provide an accessible and flexible platform for researchers to develop, experiment with, and optimize HPC workloads using open hardware.\r\n\r\nReptiles replicates Sargantana tiles within OpenPiton\u2019s architecture and introduces several architectural improvements. These include a configurable network-on-chip width (from 64 up to 704 bits), flexible cache block sizes, adjustable numbers of miss status holding registers (MSHRs), improved cache sizes and associativities, parallel SRAM access in the L2 and the last-level cache, and configurable number of memory controllers. The system also integrates the High-Performance Data Cache (HPDcache) as an L1 data cache and enhances the Sargantana core with broader support for RISC-V extensions, particularly the RISC-V Vector Extension (RVV 1.0). Additional improvements include debugging support, performance counter access in Linux, and enhanced RTL simulation features such as checkpointing.\r\n\r\nIn this demo we show a fully functional FPGA prototype of Reptiles with four Sargantana cores booting Linux and running OpenMP benchmarks such as the NAS Parallel Benchmarks, interactive UART console games, and graphical applications by performing X11 forwarding over SSH. Overall, Reptiles demonstrates that open-source RISC-V multicore systems can effectively support scalable HPC research and experimentation.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BJG9T9", "name": "Lluc Alvarez", "avatar": null, "biography": "", "public_name": "Lluc Alvarez", "guid": "cba421ca-7b92-5baa-8702-9b3ee14716e7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BJG9T9/"}, {"code": "WLABMZ", "name": "Serik Perez Gomez", "avatar": null, "biography": "", "public_name": "Serik Perez Gomez", "guid": "bf6987f1-d06d-5211-82d6-25b09c3703d9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WLABMZ/"}, {"code": "MGWWYW", "name": "Arnau Bigas Soldevila", "avatar": null, "biography": "", "public_name": "Arnau Bigas Soldevila", "guid": "2b32d040-06d1-579e-8c7e-b68ef50becd6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MGWWYW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/78MPFT/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/78MPFT/", "attachments": []}]}}, {"index": 3, "date": "2026-06-10", "day_start": "2026-06-10T04:00:00+02:00", "day_end": "2026-06-11T03:59:00+02:00", "rooms": {"Plenary": [{"guid": "4a378039-4954-53fa-bb57-5130199394a1", "code": "UCYLJC", "id": 252, "logo": null, "date": "2026-06-10T12:00:00+02:00", "start": "12:00", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-252-rvedge-vision-a-fully-open-ultra-efficient-on-device-ai-platform-for-smart-eyewear", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UCYLJC/", "title": "RVEdge-Vision: A Fully Open, Ultra-Efficient On-Device AI Platform for Smart Eyewear", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "Smart eyewear promises unobtrusive, context-aware human\u2013computer interaction by leveraging strategically placed multimodal sensors and on-device intelligence. However, integrating high-bandwidth sensing and machine learning inference within a compact and lightweight form factor remains challenging due to strict constraints in power consumption, memory footprint, and computational efficiency.This work presents RVEdge-Vision, an open hardware and software platform built on the RISC-V ecosystem that enables rapid prototyping and evaluation of next-generation smart glasses. The platform adopts a modular architecture supporting both frame-based and event-based vision sensors. To the best of our knowledge, this is the first open smart-glasses platform integrating event-based vision sensing in a glasses form factor, enabling ultra-efficient visual perception for wearable edge AI systems.\r\nThe system incorporates a hardware\u2013software co-designed power management framework optimized for battery-operated edge devices and continuous sensing workloads. As a reference implementation, we present a compact smart-glasses prototype that integrates multimodal sensing and on-device ML acceleration. The device can operate for several hours on a 300 mAh battery while sustaining real-time embedded vision workloads. A YOLOv8-based hand gesture recognition runs on-board with a few ms latency without relying on cloud connectivity. By releasing the platform as open hardware, OpenEdge RV aims to accelerate innovation within the RISC-V and open-edge AI communities, providing a reproducible foundation for research in wearable sensing, neuromorphic vision, and ultra-efficient on-device intelligence.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "ZFNG9D", "name": "Michele Magno", "avatar": "https://cfp.riscv-europe.org/media/avatars/ZFNG9D_lQPVCEM.webp", "biography": "", "public_name": "Michele Magno", "guid": "162a990c-6467-5e9e-8c61-e085ea4ee081", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZFNG9D/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UCYLJC/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UCYLJC/", "attachments": []}, {"guid": "fe425541-be0b-58ed-bfa5-6c215e1f7cf0", "code": "HC7JS8", "id": 57, "logo": null, "date": "2026-06-10T12:15:00+02:00", "start": "12:15", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-57-riviera-a-programmable-risc-v-edge-architecture-for-nfc-signal-processing", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HC7JS8/", "title": "RIVIERA: A Programmable RISC V Edge Architecture for NFC Signal Processing", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "RIVIERA core, developed within Chips-JU TRISTAN Project, is a valid alternative to State-of-Art DSP architectures used in NFC Readers downlink signal processing. Instead of relying on custom hardware, RIVIERA employs an open source RISC-V core and its ISA extension interface to implement a software defined-radio (SDR) architecture, thus moving processing to the extreme edge of an NFC communication system. The first RIVIERA prototype targets decoding of NFC Type A tags responses and is ready by-design to cover other NFC standards and rates. By replacing hardened logic functions with SW data processing supported by a general-purpose DSP accelerator, RIVIERA reduces pre-silicon engineering effort, enables continuous post silicon improvements, and facilitates portability across SoCs designs and technology nodes. This work demonstrates how application-specific custom RISC V ISA extensions can effectively and efficiently handle RF baseband workloads, paving the way for the adoption of SDR architectures in RF communications for the IoT mass market.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "KYWPTP", "name": "Luca Lingardo", "avatar": null, "biography": "", "public_name": "Luca Lingardo", "guid": "718fb949-afe4-5850-ad37-9e6189e79c48", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KYWPTP/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HC7JS8/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HC7JS8/", "attachments": []}, {"guid": "6c4aa5ad-3245-59a2-95dc-42756457b039", "code": "JKTENR", "id": 303, "logo": null, "date": "2026-06-10T12:30:00+02:00", "start": "12:30", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-303-accelerating-risc-v-innovation-with-open-mpact-tools-from-google", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JKTENR/", "title": "Accelerating RISC-V Innovation with open MPACT Tools from Google", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "The MPACT Tools portfolio provides open-source tools that increase the velocity of HW-SW co-design and development of RISC-V based systems.\r\n\r\nMPACT-Sim [1] is an ISS framework in C++ that makes it easier to create ISSs from scratch, and supports rapid changes in response to ISA design changes or user-needed functional enhancements. Using DSLs to describe the instruction set and encoding, it automatically generates instruction decoder source, and provides support for generating assemblers and disassemblers. MPACT-Sim enables rapid HW/SW co-design and early pre-Silicon software development.\r\n\r\nMPACT-RiscV [2] (built using MPACT-Sim) is a highly configurable RiscV ISS, with an interactive command interface for assembly level debugging and a customizable assembler which generates both relocatable and executable output files.\r\n\r\nTo demonstrate the practical impact of the MPACT ecosystem, we present the real-world case study of the CoralNPU machine learning core [3], which is focused on development and execution of ML kernels. The CoralNPU-MPACT ISS [4] development was significantly accelerated by leveraging the fundamental MPACT-Sim and MPACT-RiscV infrastructure, requiring only  limited modifications to support the additions to the CoralNPU's instruction set and memory access rules.\r\n\r\nThe CoralNPU UVM testbench [5] captures every retired instruction via the standardized RISC-V Verification Interface (RVVI) and steps the MPACT ISS model using a SystemVerilog DPI bridge. The testbench then retrieves golden reference values from the model to verify equivalence against the CoralNPU RTL, detecting functional bugs during development.", "description": "Summary\r\nThis submission will detail the use of 4 open-sourced tools to provide simulation and verification support for the CoralNPU, a RISC-V compliant, full-stack, open-source platform designed to address the core performance, fragmentation, and privacy challenges limiting powerful, always-on AI with low-power edge devices and wearables.\r\n\r\nImportance\r\nThe open-sourced tools provide immediate support for a wide range of Risc-V architecture extensions, and are easily adaptable to new variations, supporting their development from prototyping to design, and verification. The tools have been tested and are in active use.\r\n\r\nContributing to the Ecosystem\r\nThis work has contributed freely available tools for simulation and verification that can be used immediately, or customized to fit the requirements of new architectural variations.\r\n\r\nTarget Audience\r\nISA Architects, early software developers, designers and verification engineers.\r\n\r\nBibliography\r\n[1] Google LLC, \u201cGitHub - google/mpact-sim,\u201d GitHub, 2025. http://github.com/google/mpact-sim\r\n\r\n[2] Google LLC, \u201cGitHub - google/mpact-riscv,\u201d GitHub, May 08, 2023. http://github.com/google/mpact-riscv\r\n\r\n[3] B. Rutledge, \u201cIntroducing Coral NPU: a full-stack Platform for Edge AI,\u201d Googleblog.com, Oct. 15, 2025. https://developers.googleblog.com/introducing-coral-npu-a-full-stack-platform-for-edge-ai/\r\n\r\n[4] Google LLC, \u201cGitHub - google-coral/coralnpu-mpact: CoralNPU Behavior Simulator Based on MPACT-Sim,\u201d GitHub, 2025. https://github.com/google-coral/coralnpu-mpact\r\n\r\n[5] Google LLC, \u201ccoralnpu/tests/uvm at main \u00b7 google-coral/coralnpu,\u201d GitHub, 2025. https://github.com/google-coral/coralnpu/tree/main/tests/uvm", "recording_license": "", "do_not_record": false, "persons": [{"code": "SNZFYQ", "name": "Tor Jeremiassen", "avatar": null, "biography": "Tor Jeremiassen is a senior staff software engineer at Google LLC working on tools supporting architectural exploration, in particular, instruction level simulation frameworks. He brings with him 30 years of experience in writing simulators and frameworks for a variety of processors and application specific accelerators, particularly in the embedded space.\r\n\r\nTor earned a Ph.D. in Computer Science from the University of Washington, specializing in compile time optimizations to improve cache performance on shared memory multiprocessors. Tor also holds an M.S. in Computer Science from the University of Washington, and a B.S in Computer Science from the University of Texas at Austin.", "public_name": "Tor Jeremiassen", "guid": "d9b8a2d4-75f1-56b4-b762-4b7dce92c4e0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SNZFYQ/"}, {"code": "HTBKA7", "name": "Yenkai Wang", "avatar": null, "biography": "", "public_name": "Yenkai Wang", "guid": "ae2c0933-c0b6-509b-a5f4-38839ad345f3", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HTBKA7/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JKTENR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JKTENR/", "attachments": []}, {"guid": "30f1ce72-fdda-5c25-9f41-2585c6cd7a41", "code": "QVKCU9", "id": 51, "logo": null, "date": "2026-06-10T12:45:00+02:00", "start": "12:45", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-51-svm-a-synthesizable-approach-to-efficient-risc-v-cpu-verification", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QVKCU9/", "title": "SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "The growing complexity of RISC-V processors, driven by rapidly expanding ISA extensions and sophisticated microarchitectures, has made functional verification a dominant bottleneck. Contemporary CPU verification commonly relies on RTL co-simulation against a software reference model, but on hardware-assisted simulation platforms (e.g., FPGAs) this workflow is fundamentally limited by high-volume communication between the accelerated RTL and the host-executed reference, preventing verification throughput from scaling. This paper addresses this by eliminating the RTL-host interaction bottleneck and proposing a Synthesizable Verification Methodology (SVM). We re-architect a RISC-V reference model as synthesizable hardware and deploy it alongside the design under test on the same acceleration platform, enabling fully hardware-based co-simulation at near-native speeds (60 MHz on FPGAs) while preserving reference-model checking and debug observability.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "YQH9HR", "name": "Yinan Xu", "avatar": "https://cfp.riscv-europe.org/media/avatars/YQH9HR_i53vMOC.webp", "biography": "Yinan Xu is an Assistant Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He received his B.Eng. degree from the University of Chinese Academy of Sciences in 2019 and his Ph.D. degree from ICT, CAS in 2025. He is a core developer of the XiangShan open-source high-performance RISC-V processor, where he has pioneered several agile design and verification techniques that have been successfully integrated into the project. His work has been recognized with the CAS President\u2019s Special Award, the ICT Director\u2019s Special Award (Xia Peisu Award), and the National Scholarship. His research contributions have been published in leading venues such as MICRO, HPCA, DAC, and JCST. Notably, XiangShan and its agile design methodology were selected as one of 2022 IEEE Micro Top Picks, recognizing it as one of the year\u2019s most influential conference papers to computer architecture.", "public_name": "Yinan Xu", "guid": "922c0407-bbe2-5951-88cb-c4bb136b1b2d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YQH9HR/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QVKCU9/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QVKCU9/", "attachments": []}, {"guid": "f853b638-1855-5226-804d-21b2c1902af5", "code": "G7YSXG", "id": 27, "logo": null, "date": "2026-06-10T16:45:00+02:00", "start": "16:45", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-27-ultra-low-power-risc-v-core-retention-with-warm-restart-extension", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YSXG/", "title": "Ultra Low Power RISC-V core:  Retention with Warm Restart Extension", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "Energy saving is a top priority for STMicroelectronics products. For the STxP5 embedded CPU based on the RISC-V architecture, there is a particular focus on minimizing static power when the core is inactive. Additionally, it is important to optimize the CPU restart time, silicon area, implementation complexity, and software overhead. The Ultra Low Power Retention with Warm Restart Mode addresses these challenges by maximizing power savings and reducing drawbacks typically associated with resuming operation. This solution leverages the modular, scalable, customizable, and extensible nature of the RISC-V architecture by defining and implementing a custom RISC-V extension and tailored microarchitecture.", "description": "This paper details the concrete microarchitectural and system mechanisms used to realize the Ultra Low Power Retention with Warm Restart Mode on an in\u2011house RV32, 4\u2011stage RISC\u2011V core family. Beyond the abstract, it precisely defines the power partitioning strategy, where the core power domain is fully shut down while TCMs remain in retention, and explains the implications on context handling, including architectural, non\u2011architectural, and hardware\u2011updated read\u2011only registers.\r\n\r\nA central contribution is the XSTULP custom extension, mapped in the custom\u20110 opcode space, which introduces two atomic instructions, XSTULP.gtr and XSTULP.rtr. These instructions micro\u2011sequence optimized internal operations (register access, memory transfers with pre/post\u2011update of a hidden stack pointer XS) to perform complete context save/restore in hardware, while software only needs to prepare a retention stack in TCM and disable interrupts.\r\n\r\nThe paper also describes the request\u2013acknowledge protocol between the core and SoC, specific usage of RISC-V CSR, and the dedicated warm_restart_sequence that determines whether execution follows the normal boot flow or a warm restart path. Finally, the authors report quantitative KPIs (power, latency, area, software overhead) and outline the verification methodology, including UPF\u2011based dynamic tests and formal verification, demonstrating robustness of the proposed low\u2011power mode.", "recording_license": "", "do_not_record": false, "persons": [{"code": "BEZYZ7", "name": "Anne Merlande", "avatar": "https://cfp.riscv-europe.org/media/avatars/BEZYZ7_jZmP06O.webp", "biography": "Anne Merlande is a processor architect at STMicroelectronics in Grenoble, within the Computing and Compilers Center. As Senior Member of Technical Staff, her expertise field covers processor and system architecture, CPU microarchitecture and frontend design, low power and energy efficient subsystems, security and functional safety.\r\nShe graduated from Institut Sup\u00e9rieur d\u2019\u00c9lectronique de Paris in 1995 and joined STMicroelectronics in 1999, after four years as an ASIP designer at Matra. At STMicroelectronics, she has led the design of the ST200 processor families, acted as technical lead for ARM Cortex A subsystem frontend design, and led top level integration for automotive SoCs.\r\nShe currently works as Processor Architect on the STxP5 core family, with a particular focus on ultra low power operation, security, and functional safety.", "public_name": "Anne Merlande", "guid": "c3b38dfa-f182-5d88-b168-a984513cbf9e", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BEZYZ7/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YSXG/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YSXG/", "attachments": []}, {"guid": "ebe70dc3-1925-509b-801a-3e2aadd71909", "code": "8LUM7U", "id": 249, "logo": null, "date": "2026-06-10T17:00:00+02:00", "start": "17:00", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-249-risc-v-custom-instructions-for-automotive-control-and-dsp-algorithms-compliant-with-iso-26262", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8LUM7U/", "title": "RISC-V Custom Instructions for Automotive Control and DSP Algorithms Compliant with ISO 26262", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "The stringent safety requirements of the automotive industry necessitate compliance with standards like ISO 26262. Processor cores, often pre-certified to ASIL-B or ASIL-D, face certification risks when modified. This work focuses on the development of custom instructions that are integrated through Codasip\u2019s Bounded Customization (BC) without directly modifying the core\u2019s verified RTL. The paper details a workflow for this process and presents performance results demonstrating the acceleration achieved for key automotive and DSP algorithms, including Field Oriented Control (FOC). All extensions were consolidated into a unified custom processor, termed as the Motor Control with DSP (MCXD) core, featuring a scheduling algorithm that coordinates FOC and filtering routines. Synthesis showed an area increase of ~31%, while runtime and instruction count measurements demonstrated performance improvement of up to ~21%. These results validate that domain-specific acceleration can be achieved within the boundaries of ISO 26262.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "MDBXAS", "name": "Andreas Mauderer", "avatar": null, "biography": "Andreas Mauderer received the diploma degree in computer science from the University of Karlsruhe, Germany, in 2009. He received his PhD in computer science at the University of Tuebingen in 2014. He is working at Bosch since 2009 in the business unit Mobility Electronics in the field of Virtual Prototyping and on-chip processors for automotive ASICs. Furthermore, he is active in various publicly funded projects regarding these topics.", "public_name": "Andreas Mauderer", "guid": "0e9083d0-8130-54d2-b210-03ed10a9e0f8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MDBXAS/"}, {"code": "FMJZDN", "name": "Zdenek Prikryl", "avatar": "https://cfp.riscv-europe.org/media/avatars/FMJZDN_Lxiatjc.webp", "biography": "Zdenek received the PhD degree from the Brno University of Technology, Czechia, where he played a significant role in the research related to processor development automation. It enabled the creation of the processor development tools, Codasip Studio, that he has been driving ever since at Codasip. Zdenek has continued working as the chief architect of Codasip Studio for more than 12 years. He has also been the architect of diverse processor cores, including but not limited to 16/32-bit architectures for IoT, 32/64bit DSP-oriented architectures, or Linux capable architectures. All of these architectures were developed using Codasip Studio, and many of them were based on the RISC-V ISA. Zdenek has been also involved in embedded systems design (software and hardware) and driving R&D activities for many years.", "public_name": "Zdenek Prikryl", "guid": "1375b6be-d5c4-5c96-b78f-484814e20df8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FMJZDN/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8LUM7U/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8LUM7U/", "attachments": []}, {"guid": "392cca1d-3e10-57c3-b4c0-92728b3f16eb", "code": "WWT8EV", "id": 112, "logo": null, "date": "2026-06-10T17:15:00+02:00", "start": "17:15", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-112-proposal-of-state-sensitive-counter-sssscnt", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WWT8EV/", "title": "Proposal of State Sensitive Counter (Sssscnt)", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "PELT (Per-Entity Load Tracking) is an exponential decay-based per-entity load tracking algorithm in the Linux kernel. It significantly enhances the scheduler\u2019s load awareness accuracy, response latency, and energy efficiency. However, there are still drawbacks in load tracking: The load metrics that are used are not CPU-frequency invariant. The advent of CPU frequency scaling causes task physical runtime to fluctuate with frequency, which, if uncorrected, distorts util_avg and leads to scheduling misjudgments. To address this, the kernel employs hardware counters (e.g., Intel APERF/MPERF, ARMv8.4-AMU) to implement frequency invariance accounting, ensuring util_avg remains anchored to the CPU\u2019s maximum capacity, thereby maintaining load statistics accuracy and scheduling optimality in dynamic frequency environments.\r\nTargeting RISC-V architectures, this proposal introduces State sensitive Counters to fill the gap in PELT\r\nfrequency invariance support. Together, these counters enable the derivation of real-time operating frequency and normalized utilization without costly synchronous queries.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BUE3FF", "name": "Fengxue Zhang", "avatar": "https://cfp.riscv-europe.org/media/avatars/BUE3FF_wHoGCQf.webp", "biography": "As a senior Engineer in the Firmware Team at Alibaba Damo Academy, Esther specializes in system and power management software standards, with a focus on architecting and developing power management frameworks across diverse operating systems (OS) and firmware technologies. Her work drives innovation in energy-efficient computing and system optimization, aligning with industry-leading specifications to enhance hardware-software synergy.", "public_name": "Fengxue Zhang", "guid": "2680af86-12d6-5637-b79f-453b8a869fd0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BUE3FF/"}, {"code": "VVV3SP", "name": "Bohua Kou", "avatar": null, "biography": null, "public_name": "Bohua Kou", "guid": "41188342-6c08-5996-96f6-ba5a2d564ffb", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VVV3SP/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WWT8EV/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WWT8EV/", "attachments": []}, {"guid": "452e0646-8337-56ef-b136-a9266e186a1d", "code": "MUFY8Z", "id": 178, "logo": null, "date": "2026-06-10T17:30:00+02:00", "start": "17:30", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-178-a-proof-of-concept-risc-v-with-128-bit-extension", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MUFY8Z/", "title": "A Proof-of-Concept RISC-V with 128-bit Extension", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "Addressing ever-larger amounts of memory is a fact of (computerized) life. The authors of the RISC-V unpriviledge specification did recognize that and coined on less than one and a half page what could be a natural extension to 128-bit of the  32- and 64-bit RISC-V ISA. Given this RV128I draft, we (a) defined an ELF128 extension for binaries, (b) made gnu-based a cross-compilation environment able to use RV128I instructions and generate ELF128 binaries, (c) added support for this extension and ELF128 in QEMU, (d) added the necessary instructions and resources in the CVA6 processor.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "NNBQLT", "name": "Fr\u00e9d\u00e9ric P\u00e9trot", "avatar": "https://cfp.riscv-europe.org/media/avatars/NNBQLT_xbwBNUp.webp", "biography": "", "public_name": "Fr\u00e9d\u00e9ric P\u00e9trot", "guid": "699aa0ee-a323-5ce3-969f-6e30b2435cbf", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/NNBQLT/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MUFY8Z/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MUFY8Z/", "attachments": []}, {"guid": "f007ab18-11f1-546a-b432-d566671f9eff", "code": "R7MK7D", "id": 259, "logo": null, "date": "2026-06-10T17:45:00+02:00", "start": "17:45", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-259-an-open-source-cva6s-based-high-performance-cache-coherent-cluster-for-64b-automotive-mpus", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/R7MK7D/", "title": "An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "Driven by the need for zonal control architectures in software-defined vehicles, open-source RISC-V cores are becoming a compelling solution for automotive microprocessor units (MPUs). We introduce a 64b cache-coherent, tightly coupled cluster built upon the industry-backed OpenHW CVA6S+ core and HPDCache, capable of executing SMP Linux and RTOS kernels. A design space exploration of the core branch predictor identifies an embedded tournament configuration that reduces its area by 11.6% with no loss in accuracy. Evaluated on the Splash-3 benchmark suite, the cluster achieves a geometric mean speedup of 1.75\u00d7 over a single-core baseline, and a 1.21\u00d7 speedup over a prior implementation based on the scalar CVA6 and legacy cache subsystem. Synthesized in GlobalFoundries' 12 nm FinFET, the dual-core cluster incurs less than 1% per-core area overhead, with the coherent unit in the interconnect contributing only 35 kGE (1.5%) to the total cluster footprint.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "JX397U", "name": "Riccardo Tedeschi", "avatar": null, "biography": "Riccardo Tedeschi received his Master's Degree in Electronic Engineering from the University of Bologna in 2023. He is now pursuing a Ph.D. in Digital Systems Design within the Department of Electrical and Information Engineering (DEI) at the same university and is currently a visiting researcher at ETH Z\u00fcrich. His research centers on RISC-V architectures tailored for embedded platforms, particularly in the areas of performance optimization and reliability.", "public_name": "Riccardo Tedeschi", "guid": "20d5f36c-0fb5-5604-8741-4a2766bdb907", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JX397U/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/R7MK7D/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/R7MK7D/", "attachments": []}], "Poster Island A": [{"guid": "a6a2d105-c8bf-529a-8f39-09b7d837a9ef", "code": "NMX7W7", "id": 67, "logo": null, "date": "2026-06-10T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-67-an-efficient-approach-to-apply-the-risc-v-sail-model-to-chip-verification", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NMX7W7/", "title": "An Efficient Approach to Apply the RISC-V Sail Model to Chip Verification", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The Sail RISC-V Model can generate an executable file from its formal specification,. Currrently RISC-V tests only provides limited test cases and cannot comprehensively test your RISC-V implementation. Some chips may use self-developed simulators for testing, but they cannot obtain formal verification-based guarantees like RISC-V Sail Model, nor can they offer full configurability. This work introduces a new test framework that uses the RISC-V Sail Model as the ref model, ensuring the model's completeness and accuracy. To improve simulation performance, we choose to use Pydrofoil, which is an improved version of the Sail Model that delivers ultra-high performance. To enhance test compatibility and usability, we provide a set of simple test interfaces (including register access, memory access, etc.) and support customizing model configurations. Currently, it has successfully integrated tests for some open-source RISC-V implementations.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "UVDGJA", "name": "Mingzhu Yan", "avatar": null, "biography": "", "public_name": "Mingzhu Yan", "guid": "c842762e-d281-5fe0-bd6b-d031940076c9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UVDGJA/"}, {"code": "KNTSHY", "name": "Yunxiang Luo", "avatar": "https://cfp.riscv-europe.org/media/avatars/KNTSHY_n86SpHx.webp", "biography": "Email: luoyunxiang@iscas.ac.cn\r\nIntelligent Software Research Center (ISRC), Institute of Software, Chinese Academy of Sciences (ISCAS)", "public_name": "Yunxiang Luo", "guid": "b618a00a-b794-5236-b4c3-63f3604bfcc9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KNTSHY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NMX7W7/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NMX7W7/", "attachments": [{"title": "poster", "url": "/media/eu-summit-2026/submissions/NMX7W7/resources/An_Efficient_Approac_NyhA9tm.pdf", "type": "related"}]}, {"guid": "88a73616-d603-52cc-8a2a-b31846745915", "code": "WWSLLF", "id": 177, "logo": null, "date": "2026-06-10T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-177-sail-risc-v-and-spike-for-risc-v-vector-toward-consistent-golden-reference-behavior", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WWSLLF/", "title": "Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "In recent years, the executable specification generated from Sail-RISC-V has increasingly been considered as a successor to the widely used Spike ISA Simulator as golden reference for RISC-V, including the complex and highly configurable RISC-V Vector Extension (RVV). In this paper, we compare the RVV behavior of Sail-RISC-V against Spike using the automated testing framework RVVTS. While Sail-RISC-V largely matches Spike under positive testing (0.23% deviations), negative testing reveals substantially more deviations (3.73%), highlighting remaining issues in Sail-RISC-V\u2019s RVV instruction validity checking under dynamic configurations.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "YYN8DQ", "name": "Manfred Schl\u00e4gl", "avatar": null, "biography": "Manfred Schl\u00e4gl is a PhD student at the Institute for Complex Systems, JKU Linz, under Prof. Daniel Gro\u00dfe. For 15 years, he worked in industry, focusing mainly on low-level firmware and operating systems for industrial embedded systems. In 2021, he left the industry to resume his studies, completed his Master's degree in Computer Science in 2023, and started his PhD immediately afterward. His main research interests are hardware/software co-simulation using virtual prototypes and hardware verification. He is also deeply interested in operating systems, hardware platforms, and computer architectures, especially RISC-V.", "public_name": "Manfred Schl\u00e4gl", "guid": "770c5fec-a356-5bd3-aa16-ac44c230c6c0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YYN8DQ/"}, {"code": "TW7YDL", "name": "Daniel Gro\u00dfe", "avatar": "https://cfp.riscv-europe.org/media/avatars/TW7YDL_xYTVPx4.webp", "biography": "", "public_name": "Daniel Gro\u00dfe", "guid": "58d8bc6d-0200-5bfe-b1d2-017fe384c265", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TW7YDL/"}, {"code": "YV8HWQ", "name": "Katharina Ruep", "avatar": null, "biography": null, "public_name": "Katharina Ruep", "guid": "c5eec783-d9e0-5a5c-9c08-0df2e98a5339", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YV8HWQ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WWSLLF/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WWSLLF/", "attachments": []}, {"guid": "17aa0a73-fc33-5e72-9edf-c1bd760a3952", "code": "FYCK9P", "id": 295, "logo": null, "date": "2026-06-10T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-295-spike-rtl-two-technologies-for-fast-and-accurate-sw-rtl-co-simulation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FYCK9P/", "title": "Spike-RTL: Two technologies for fast and accurate SW-RTL co-simulation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The verification of integrated systems traditionally relies on detailed Register Transfer Level (RTL) simulations to ensure functional correctness before hardware implementation. While RTL simulation provides cycle-accurate behavior and can even achieve event-level precision when combinational delays are modeled, it suffers from extremely long execution times. Simulating complex software workloads such as booting an operating system may require several days of simulation time.\r\nInstruction Set Simulators (ISS) provide a faster alternative for software execution. In the RISC-V ecosystem, Spike is the reference ISS and can achieve simulation speeds several orders of magnitude faster than equivalent RTL processor models. However, replacing the processor RTL model with an ISS introduces temporal discrepancies that may affect the accuracy of system-level simulations. This work presents Spike-RTL, a HW/SW co-simulation framework that integrates the Spike ISS with RTL models of the remaining hardware components. The tool supports both Verilog simulation and C/SystemC HW models (e.g. generated using Verilator). Experimental results show simulation speedups of up to 40\u00d7 compared to Verilog simulation and 4\u00d7 compared to Verilator, while maintaining timing errors on the order of 10%. The framework also introduces configurable timing models for instruction execution, cache miss latency integration, and variable-granularity synchronization mechanisms between ISS and RTL components.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "TNRGBV", "name": "Eugenio Villar", "avatar": null, "biography": "Professor Eugenio Villar obtained his PhD in Electronics many years ago. Since 2002, he has been a Professor in the TEISA Department at the University of Cantabria, where he is responsible for the Embedded Systems Design (HW/SW) area within the Microelectronics Engineering Group. His research has always focused on the specification and design of electronic systems. He is currently working on the use of Artificial Intelligence in the co-design and simulation of model-driven systems. Professor Villar has authored over 100 papers published in national and international conferences and journals. He has participated in electronic systems design projects under European (FP and Horizon Europe) and transnational programs, such as Medea-Catrene, Artemis, ECSEL, KDT, and Chips JU. He is the University of Cantabria's representative in Chips JU and the Director of the Cantabria Chip Chair.", "public_name": "Eugenio Villar", "guid": "41710a72-0ab0-5e63-9a0e-b6a515ff5ecc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TNRGBV/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FYCK9P/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FYCK9P/", "attachments": []}, {"guid": "6fe372a4-e1a1-51aa-b0b9-41208eeca3bc", "code": "97EAVY", "id": 296, "logo": null, "date": "2026-06-10T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-296-simulation-driven-framework-for-custom-risc-v-hw-sw-co-development-and-debug", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/97EAVY/", "title": "Simulation-Driven Framework for Custom RISC-V HW/SW Co-Development and Debug", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Custom RISC\u2011V implementations increasingly require tight coupling between hardware and software development to ensure correctness, performance, and rapid iteration. This paper presents the RISC\u2011V Unified DB Instruction Set Simulator (RVUDB\u2011ISS), an open-source simulation\u2011driven framework that enables early\u2011stage HW/SW co\u2011development, configuration validation, and full\u2011stack debug prior to RTL availability. The ISS is automatically generated from a formally specified configuration, producing an implementation\u2011accurate model for custom RISC\u2011V cores and extensions. \r\n\r\nRVUDB\u2011ISS supports configuration\u2011optimized binaries, enforcement of architectural corner cases, and precise modeling of implementation\u2011defined behaviors. \r\nA key functionality is the ISS\u2019s integrated debug experience: developers can run custom workloads, halt execution at the first instruction, and attach standard tools such as GDB and VS Code to provide a familiar SW debug environment. This enables full symbolic debug of custom cores without hardware availability, significantly reducing time\u2011to\u2011bring up, and improving quality at bring up. \r\n\r\nOverall, RVUDB\u2011ISS demonstrates that simulation\u2011based debug for custom RISC\u2011V configurations enables earlier validation, higher code quality, and more reliable HW/SW co\u2011development compared to traditional pre and post\u2011silicon workflows.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "QJRTYE", "name": "Henrik Gustafsson", "avatar": null, "biography": "", "public_name": "Henrik Gustafsson", "guid": "205546bc-4a16-57e8-ab1b-1d9295a23be2", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QJRTYE/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/97EAVY/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/97EAVY/", "attachments": []}, {"guid": "49d2cda5-7f1b-538e-a39f-e89cfafa85a1", "code": "FWXFHU", "id": 209, "logo": null, "date": "2026-06-10T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-209-functional-verification-strategy-for-a-cva6-mmu", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FWXFHU/", "title": "Functional Verification Strategy for a CVA6 MMU", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Modern processors implement complex features that require unique verification strategies to exhaustively verify the feature and achieve coverage goals faster. The memory management unit (MMU) within the CVA6, with multiple level of table, page tables, lookaside buffers (TLBs), and physical memory protection (PMP) capabilities, is one such feature. It is highly configurable and complex, making an exhaustive verification a real challenge. It requires smart management of different page table entries (PTEs) and PMP entries, to simulate different types of exceptions, page faults and PMP access errors. This work is done using an Universal Verification Method (UVM) framework provinding an efficient means creating PMPs and PTEs, thus simplifying the verification of MMU.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CBJMU9", "name": "Tanuj Khandelwal", "avatar": null, "biography": "", "public_name": "Tanuj Khandelwal", "guid": "3e975a80-ff47-5d4c-8c84-2a5506fe6b2a", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CBJMU9/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FWXFHU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FWXFHU/", "attachments": []}, {"guid": "3e3de126-ee68-558f-8388-1edfd2f1d8ae", "code": "KBLECB", "id": 111, "logo": null, "date": "2026-06-10T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-111-functional-verification-strategy-of-the-core-v-floating-point-unit-cvfpu-for-risc-v-cores", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KBLECB/", "title": "Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Floating-point unit (FPU) verification is inherently challenging due to IEEE-754 corner cases, multiple rounding modes, exception handling, subnormal behavior, and the large input space introduced by mixed precision. The CORE-V Floating-Point Unit (CVFPU) released as open source, provides a highly configurable multi-format implementation but lacks an industrial-grade functional verification framework. This work addresses that gap by proposing a structured UVM-based verification strategy tailored to its configurable architecture. The approach integrates a variable-precision C++ reference model, directed and constrained-random stimulus, assertion-based checks, and coverage-driven closure.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "NRR8EJ", "name": "Ihsane Tahir", "avatar": null, "biography": "Ihsane Tahir received a M.S. degree in embedded systems from Grenoble INP - Esisar, Valence, France, in 2020. She subsequently joined CEA LIST as a research engineer. She then joined the OpenHW Foundation in 2026 as a hardware verification engineer. Her works include functional verification, FPGA prototyping and digital design.", "public_name": "Ihsane Tahir", "guid": "fe7b7cd0-e205-55a5-ab14-bdcbb7f4fabf", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/NRR8EJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KBLECB/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KBLECB/", "attachments": []}, {"guid": "5d9a2465-0435-5693-baf1-9fae8f8cdfde", "code": "XANKHZ", "id": 239, "logo": null, "date": "2026-06-10T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-239-reproducibility-in-open-source-risc-v-hw-flows", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XANKHZ/", "title": "Reproducibility in open-source RISC-V HW flows", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Open-source hardware is booming. To prevent fragmentation, encourage collaboration and reuse we propose the RISC-V to join forces with Reproducible Builds communities and concentrate innovation potential where its needed most: creation of new micro-architectures, IPs and their integration into new SoCs and applications. To facilitate this goal, we chose Guix, a rigorous solution for reproducible software artefacts. We apply it to dependency management & reproducibility problems in open-source hardware and show the validity of the approach, taking CVA6 as a running example. The end result - a fully reproducible collection of packaged tests, emulation, simulation and cycle-accurate models - shows a promising workflow that could (in future) scale to support larger RISC-V community with reusable software & hardware components for next-generation platforms.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "PMJQ7C", "name": "Petr Kourzanov", "avatar": "https://cfp.riscv-europe.org/media/avatars/PMJQ7C_iPjub3H.webp", "biography": "Having started personal journey in Uzbekistan, and professional career in Delft, Peter delved  into SW engineering (at TU/d) towards streaming and multimedia systems for CE (architecture & infrastructure group at Philips Research, NatLab). He developed a passion for fun PLs such as Icon, Scheme and Julia, which he applied in projects such a simulation modeling, virtual prototype environments and a joint project on SDR with Nokia. Dataflow compiler & middleware project got him further into the DSP algorithms and radio & radar transceivers - focus of the work at NXP Semiconductors for more than 10 years, resulting in IPs for, e.g., SAF85xx made with Julia and RoadLink SAF5400 made with SystemC and HLS. At IMEC since 2022, he focuses on SW/HW interfaces, simulation infra and on micro-arch modeling for RISC-V and CMOS2.0. Since 2019 he consults in efficient networking stack simulation, automation and nano-kernels such as Zephyr.", "public_name": "Petr Kourzanov", "guid": "80d6c342-cace-5a4f-add6-ea867fdb79e9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/PMJQ7C/"}, {"code": "88QGQ3", "name": "Anmol Xx", "avatar": null, "biography": null, "public_name": "Anmol Xx", "guid": "706f09be-4ac6-5681-a6b3-abb87fa33949", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/88QGQ3/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XANKHZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XANKHZ/", "attachments": []}, {"guid": "b5b231e8-4c91-572b-8cc1-a3f9989fc1a5", "code": "VVBBMK", "id": 319, "logo": null, "date": "2026-06-10T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-319-kepler-formal-open-logic-equivalence-checking-for-risc-v-ci-workflows", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VVBBMK/", "title": "kepler-formal: Open Logic Equivalence Checking for RISC-V CI Workflows", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The rapid expansion of the RISC-V ecosystem has led to an increasing number of open hardware projects hosted on collaborative platforms such as GitHub. While modern software development benefits from mature continuous integration and continuous deployment (CI/CD) methodologies, equivalent automated verification infrastructure remains limited for hardware design. In particular, formal verification tools such as logic equivalence checking (LEC) remain largely restricted to proprietary EDA solutions.\r\nThis work explores the use of lightweight open-source EDA tools as scalable verification agents for open hardware development workflows. We present an open-source logic equivalence checking tool designed to operate efficiently within CI environments for RISC-V projects. Built on a high-performance C++ infrastructure for netlist representation and analysis, the tool enables rapid equivalence verification between different RTL transformations and synthesized netlists. Experimental results on open RISC-V designs demonstrate that automated equivalence checks can be integrated into CI pipelines with execution times compatible with typical pull request validation workflows. This approach provides a practical first verification gate for open hardware repositories before deeper sign-off verification using commercial tools.", "description": "The rapid growth of the RISC-V ecosystem has led to an increasing number of open hardware projects developed collaboratively through platforms such as GitHub. While software development widely benefits from automated continuous integration (CI) workflows, equivalent verification infrastructure for hardware design remains limited, particularly for formal verification tasks such as logic equivalence checking (LEC). Most industrial LEC tools remain proprietary and difficult to integrate into distributed open development environments.\r\n\r\nThis work presents kepler-formal, an open-source logic equivalence checking tool designed to operate efficiently within CI pipelines for RISC-V hardware development. Built on top of the Naja infrastructure for hierarchical netlist representation and analysis, the tool enables fast equivalence verification between synthesized or transformed netlists. Runtime experiments on open RISC-V designs demonstrate that equivalence checks can be executed within seconds, making them suitable for automated pull-request validation workflows.\r\n\r\nThe tool is integrated into open silicon flows including OpenROAD where it acts as an automated verification gate during development. By enabling lightweight formal verification in collaborative workflows, this approach helps bridge modern software engineering practices and open hardware development.", "recording_license": "", "do_not_record": false, "persons": [{"code": "9B9GYC", "name": "Christophe Alexandre", "avatar": null, "biography": "With 20 years of experience in Electronic Design Automation (EDA), I began my journey with a PhD in microelectronics from Sorbonne University. In 2009, I co-founded Flexras Technologies, a startup specializing in FPGA prototyping tools, which was acquired by Mentor Graphics (now Siemens EDA) in 2015. There, I served as Chief Software Architect, leading global R&D teams and helping evolve our technology into a widely adopted product.In 2022, I co-founded a new venture: keplertech.io, an EDA startup built on the belief that Open Source can unlock innovation in one of the most closed and complex industries: integrated circuits and the tools used to design them. In a space dominated by a handful of major players, we aim to create meaningful opportunities for smaller, agile actors to thrive. I\u2019m passionate about building complex systems from scratch and bringing ideas to life in the real world.", "public_name": "Christophe Alexandre", "guid": "6ccf9d6f-77f5-5001-98dc-76d7ca81b249", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9B9GYC/"}, {"code": "SCUJEC", "name": "Noam Cohen", "avatar": "https://cfp.riscv-europe.org/media/avatars/SCUJEC_3FgDGKw.webp", "biography": "Noam Cohen is the Co-Founder and CTO of keplertech.io. Throughout his\r\ncorporate career, he led R&D teams at SNPS and Siemens, dedicated to compiler\r\ndevelopment for hardware prototyping and emulation, with a focus on optimizing\r\nsolutions to NP-hard problems such as partitioning, placement, and routing, and\r\nwith an emphasis on high performance computing. After 10 years with the EDA\r\nindustry leaders, he co-founded keplertech.io with the aim of introducing innovation\r\nin both technology and user experience to hardware design software tools.", "public_name": "Noam Cohen", "guid": "c4409411-d7c5-5957-90b8-ddb9cdd54193", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SCUJEC/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VVBBMK/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VVBBMK/", "attachments": []}, {"guid": "e6cf05d0-e48a-540a-8045-329572b9bfe2", "code": "QZVQMY", "id": 108, "logo": null, "date": "2026-06-10T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-108-risc-v-tournament-battle-of-hdls", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QZVQMY/", "title": "RISC-V Tournament: Battle of HDLs", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Hardware Description Languages (HDLs) have evolved from traditional Register Transfer Level (RTL) modeling over High-level Synthesis (HLS) towards todays generative approaches. Although modern HDLs often assert technical advantages, directly comparable evaluations across HDL paradigms remain scarce.\r\nThis work introduces a year-long, community-driven tournament, designed to enable reproducible comparison of HDLs under uniform conditions. A RISC-V microarchitecture is independently implemented in multiple HDLs and evaluated within a standardized, GitHub-based framework. Since the framework provides identical conditions, differences can be related to how an HDL enables hardware realization. To ensure the quality of this tournament, all results are public, reproducible, and objectively evaluated, providing transparent evidence of HDL-specific strengths and trade-offs. Through contribution, participants can systematically demonstrate the capabilities of their preferred HDL. The collected implementations can further be used as common reference basis for research, education, and reproducible comparison of HDL approaches.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "UCKCM8", "name": "Christoph Hazott", "avatar": null, "biography": "", "public_name": "Christoph Hazott", "guid": "85121382-5d8e-53fa-bd00-671c2a2f094d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UCKCM8/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QZVQMY/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QZVQMY/", "attachments": []}, {"guid": "c3a3beb2-70dc-5d7e-84a5-b7067929881a", "code": "8VDLDD", "id": 118, "logo": null, "date": "2026-06-10T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-118-loom-an-open-source-toolchain-for-automatic-fpga-emulation-of-simulation-grade-systemverilog", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8VDLDD/", "title": "Loom: An Open-Source Toolchain for Automatic FPGA Emulation of Simulation-Grade SystemVerilog", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Functional verification dominates modern SoC development effort, yet migrating simulation testbenches to FPGA emulation typically requires proprietary tools, expensive licenses, and\r\n  significant manual RTL adaptation-particularly for designs using DPI-C calls, multi-cycle timing blocks, or system tasks like $display and $finish. We present Loom, a fully open-source\r\n   toolchain that automatically transforms unmodified simulation-grade SystemVerilog into FPGA-synthesizable RTL with complete host communication infrastructure. Built on Yosys, Loom\r\n  applies five composable compiler passes-memory shadowing, reset extraction, DPI-C bridge instrumentation, scan chain insertion, and AXI-Lite emulation wrapping-to close the semantic\r\n  gap between simulation and emulation. We validate Loom end-to-end on a Snitch RISC-V core running on a Xilinx Alveo U250 with no manual source modifications, demonstrating DPI argument\r\n   passing, scan-based state capture/restore, and host memory preloading via PCIe XDMA.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "UYBFYB", "name": "Florian Zaruba", "avatar": null, "biography": "", "public_name": "Florian Zaruba", "guid": "897c9e45-be6b-595a-8a96-c26be82f4a50", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UYBFYB/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8VDLDD/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8VDLDD/", "attachments": []}, {"guid": "71d100b6-4cfa-5887-9827-1480ec0e36f2", "code": "NTCH3P", "id": 274, "logo": null, "date": "2026-06-10T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-274-coverage-directed-smoke-regression-optimization-via-greedy-set-cover-for-risc-v-verification", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NTCH3P/", "title": "Coverage-Directed Smoke Regression Optimization via Greedy Set Cover for RISC-V Verification", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "We present a coverage-driven framework that optimizes RISC-V smoke regressions by decomposing VCS coverage into feature-specific subsets via tag-based pattern matching, ranking tests via greedy set cover, and flagging runtime outliers. Applied to a 978-test production suite drawn from a larger regression pool of 10,000 tests, the framework cut smoke tests by 40% and peak test runtime by 63%, while improving coverage on key architectural features-including +64% (SMRNMI), +53% (timer), and +25% (counters)-with modest regressions on a few features (median <3%), all within project thresholds.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "NYULLP", "name": "Anish Jaltare", "avatar": null, "biography": "", "public_name": "Anish Jaltare", "guid": "b2413e69-8f71-5b2b-b9e7-d20fdb5a3087", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/NYULLP/"}, {"code": "9GVMZW", "name": "Shubham Singla", "avatar": null, "biography": "", "public_name": "Shubham Singla", "guid": "175584a5-2497-5e08-b4e1-170c99cfde08", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9GVMZW/"}, {"code": "7VGRPR", "name": "Abhishek Rajgadia", "avatar": null, "biography": "", "public_name": "Abhishek Rajgadia", "guid": "c74b6389-7244-51e0-b1af-425751d95c4b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7VGRPR/"}, {"code": "UVSUHJ", "name": "Radha Govindaradjou", "avatar": "https://cfp.riscv-europe.org/media/avatars/UVSUHJ_OZqxXiG.webp", "biography": "", "public_name": "Radha Govindaradjou", "guid": "cab6ea05-f2d1-5414-b6f0-8a82a9fc1902", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UVSUHJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NTCH3P/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NTCH3P/", "attachments": []}, {"guid": "80249c85-bdc1-5ace-af13-43796624ae34", "code": "87KRJS", "id": 280, "logo": null, "date": "2026-06-10T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-280-pre-silicon-robustness-assessment-of-risc-v-cores-using-bit-accurate-fpga-fault-injection", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/87KRJS/", "title": "Pre-silicon Robustness Assessment of RISC-V Cores using bit-accurate FPGA fault injection", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "FPGA fault injection (FFI) is a well-known technique for verification and robustness assessment of critical systems. However existing FFI tools for current generation FPGAs support only FPGA-specific fault models irrelevant for ASIC prototypes, and feature very coarse-grain analysis insufficient for localization of dependability bottlenecks in the design. To address these limitations have developed a bit-accurate FFI tool (BAFFI), capable of emulating ASIC (RTL) faults at the level of individual netlist cells. This paper explains how BAFFI can be used to obtain robustness estimates for RTL designs and exemplifies this through a case study of an open-source RISC-V SoC.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "KNAQQX", "name": "Ilya Tuzov", "avatar": null, "biography": "Ilya Tuzov received the Ph.D. degree in computer science from the Universitat Polit\u00e8cnica de Val\u00e8ncia (UPV), Valencia, Spain, in 2020. He is currently working at UPV as a researcher. His current research interest include fault-tolerant embedded systems, reconfigurable computing, automated verification and dependability benchmarking.", "public_name": "Ilya Tuzov", "guid": "a369f9bb-a939-5a19-8a92-34d0799a2dfc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KNAQQX/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/87KRJS/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/87KRJS/", "attachments": [{"title": "extended abstract with authors affiliations and acknowledgements (camera-ready version)", "url": "/media/eu-summit-2026/submissions/87KRJS/resources/ext_abstract_IlyaTuz_NxDBYgR.pdf", "type": "related"}]}, {"guid": "c5c0014f-ba1f-5b90-936f-9b67086d1b8f", "code": "33SLKJ", "id": 189, "logo": null, "date": "2026-06-10T14:00:00+02:00", "start": "14:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-189-adamut-rv-fpga-accelerated-risc-v-fuzzing-with-adaptive-mutation-operator-scheduling", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/33SLKJ/", "title": "AdaMut-RV: FPGA-Accelerated RISC-V Fuzzing with Adaptive Mutation Operator Scheduling", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The exponential growth in RISC-V processor complexity challenges traditional functional verification. Both directed testing and constrained-random simulation are inefficient for modern architectural designs. While hardware fuzzing has emerged as a powerful alternative for uncovering deep microarchitectural bugs, existing software-based fuzzers are severely bottlenecked by slow RTL simulation speeds and suboptimal mutation strategies that lack adaptive guidance.We propose AdaMut-RV, a high-throughput, FPGA-accelerated fuzzing framework specifically optimized for RISC-V processor verification. Unlike software-bound solutions, AdaMut-RV offloads both the processor and the fuzzer onto FPGA hardware, enabling MHz-scale execution speeds. The core innovation of AdaMut-RV is an intelligent mutation-operator scheduler based on the Multi-Armed Bandit (MAB) reinforcement learning algorithm. By categorizing AFL-inspired mutation operators into nine distinct classes, our scheduler dynamically prioritizes those that yield the highest coverage gains based on real-time hardware feedback. This dynamic scheduling mechanism accelerates the exploration of processor design spaces and critical corner-case logic. Preliminary results demonstrate that AdaMut-RV significantly outperforms state-of-the-art software-based fuzzers. It achieves higher Control and Status Register Coverage while reaching the same coverage targets at a significantly faster rate.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3SXEHG", "name": "Zheng Huazhong", "avatar": "https://cfp.riscv-europe.org/media/avatars/3SXEHG_qmCVyRi.webp", "biography": "I am Huazhong Zheng, a Master\u2019s student at the Institute of Computing Technology, Chinese Academy of Sciences. My research focuses on RISC-V processor fuzzing. Currently, I am working on adaptive mutation operator scheduling algorithms, enabling fuzzers to dynamically select more effective mutation strategies to improve coverage and vulnerability detection efficiency.", "public_name": "Zheng Huazhong", "guid": "ca838e5f-59e9-56d2-b18d-9dc83cd50959", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3SXEHG/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/33SLKJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/33SLKJ/", "attachments": []}, {"guid": "eb4deb09-6007-57ab-8bab-4756c9655eaf", "code": "JZAHPN", "id": 179, "logo": null, "date": "2026-06-10T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-179-a-hardware-software-heterogeneous-framework-for-agile-risc-v-verification-with-model-based-processor-fuzzing", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JZAHPN/", "title": "A Hardware-Software Heterogeneous Framework for Agile RISC-V Verification with Model-Based Processor Fuzzing", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Processor designs are increasingly complex, making verification a critical challenge in the chip development process. Traditional verification techniques, heavily reliant on software simulations and random test inputs, often fail to effectively identify complex corner cases, leading to slow convergence and high verification costs. To address these challenges, we propose a heterogeneous hardware-accelerated RISC-V verification framework that integrates FPGA acceleration with a domain-specific generative model. This framework generates semantically-aware RISC-V instruction sequences and executes them in parallel with a reference model, providing real-time coverage collection and differential checking. The system improves verification efficiency by generating high-quality test inputs and reducing the time required for coverage convergence. Experimental results show that our framework outperforms existing fuzzers in terms of both coverage and speed, achieving up to 1.27\u00d7 higher coverage and accelerates verification by up to 107\u00d7(Cascade) to 3343\u00d7(DifuzzRTL) compared to state-of-the-art fuzzers, with consistently lower convergence difficulty.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CFSSKA", "name": "Juncheng Huo", "avatar": "https://cfp.riscv-europe.org/media/avatars/CFSSKA_sRhhFcm.webp", "biography": "", "public_name": "Juncheng Huo", "guid": "447588a4-5b38-5c74-bf3e-da2444b71a09", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CFSSKA/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JZAHPN/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/JZAHPN/", "attachments": []}, {"guid": "d990547b-1842-5595-83c7-d1a20a86301b", "code": "GJMGHA", "id": 187, "logo": null, "date": "2026-06-10T14:20:00+02:00", "start": "14:20", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-187-ucagent-an-end-to-end-agent-for-block-level-functional-verification", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GJMGHA/", "title": "UCAgent: An End-to-End Agent for Block-Level Functional Verification", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Functional verification remains a critical bottleneck in modern IC development cycles. However, traditional methods, including constrained-random and formal verification, struggle to keep pace with the growing complexity of modern semiconductor designs.\r\n\r\nWhile recent advances in Large Language Models (LLMs) have shown promise in code generation and task automation, significant challenges hinder the realization of end-to-end functional verification automation.\r\nThese challenges include (i) limited accuracy in generating Verilog/SystemVerilog verification code, (ii) the fragility of LLMs when executing complex, multi-step verification workflows, and (iii) the difficulty of maintaining verification consistency across specifications, coverage models, and test cases throughout the workflow.\r\n\r\nTo address these challenges, we propose UCAgent, an end-to-end agent that automates hardware block-level functional verification based on three core mechanisms.\r\nFirst, we establish a pure Python verification environment using Picker and Toffee to avoid relying on LLM-generated SystemVerilog verification code.\r\nSecond, we introduce a configurable 31-stage fine-grained verification workflow to guide the LLM, where each stage is verified by an automated checker.\r\nFurthermore, we propose a Verification Consistency Labeling Mechanism (VCLM) that assigns hierarchical labels to LLM-generated artifacts, improving the reliability and traceability of verification.\r\n\r\nExperimental results show that UCAgent can complete end-to-end automated verification on multiple modules, including the UART, FPU, and integer divider modules, achieving up to 98.5\\% code coverage and up to 100\\% functional coverage. UCAgent also discovers previously unidentified design defects in realistic designs, demonstrating its practical potential.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BLGYT3", "name": "Junyue Wang", "avatar": null, "biography": "", "public_name": "Junyue Wang", "guid": "4a12dedc-9898-55a3-8faa-82579205795f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BLGYT3/"}, {"code": "HS7FYC", "name": "YanPi", "avatar": null, "biography": "", "public_name": "YanPi", "guid": "773d3cbc-b13e-5993-9ec2-067e3cad348b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HS7FYC/"}, {"code": "93CSMG", "name": "Fangyuan Song", "avatar": null, "biography": "", "public_name": "Fangyuan Song", "guid": "f94b9c74-33e3-58d5-92bd-04fe7ec43691", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/93CSMG/"}, {"code": "QPVBVM", "name": "yaozhicheng", "avatar": null, "biography": null, "public_name": "yaozhicheng", "guid": "f4007301-6eaa-59b6-841e-50c4a973ece6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QPVBVM/"}, {"code": "7HUQQW", "name": "wangsa", "avatar": null, "biography": null, "public_name": "wangsa", "guid": "481d728e-061a-5ec2-80de-2ef3e44cc8c4", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7HUQQW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GJMGHA/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GJMGHA/", "attachments": []}, {"guid": "11742d87-aa7a-5f3e-8576-419cf382e911", "code": "DMYH7U", "id": 181, "logo": null, "date": "2026-06-10T15:30:00+02:00", "start": "15:30", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-181-fully-automated-risc-v-architecturalexploration-with-chipyard-and-a-deca", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DMYH7U/", "title": "Fully Automated RISC-V ArchitecturalExploration with Chipyard and A-DECA", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The increasing demand for domain-specific architectures from various domains such as Artificial Intelligence (AI),High Performance Computing (HPC), and automotive systems is reshaping modern System on Chip (SoC) design,requiring faster iteration cycles and deeper hardware/software integration.  While the open ISA RISC-V enablesunprecedented architectural flexibility, it also dramatically expands the design space across system, micro-architectural,and implementation levels. Efficiently navigating this complexity remains a key challenge for both academia and industry.The A-DECA framework is a design space exploration framework developed within the SoC Planner project to accelerateproductive SoC design. A-DECA enables a structured and modular exploration from high-level architectural configurationdown to synthesis-aware micro-architectural evaluation, effectively bridging the gap between system-level modeling andimplementation constraints.Our methodology leverage the open-source RISC-V design flow Chipyard to develop a hardware/software co-designsolution that supports automated configuration generation, parameter tuning, and quantitative performance, power, areatrade-off analysis. By reducing manual exploration effort and formalizing early-stage architectural planning, A-DECAsignificantly improves design productivity and accelerates pre-silicon decision-making. The framework reinforces theopen-source chip design ecosystem and lays the foundation for scalable, chiplet-oriented RISC-V architectures. Its plannedopen-source release aims to further enable reproducible research, industrial adoption, and collaborative innovation infull-flow RISC-V SoC development.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "AVGQV8", "name": "Lilia Zaourar", "avatar": null, "biography": "", "public_name": "Lilia Zaourar", "guid": "e0e2d5d9-1c18-5e8f-ac68-306045fc536c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AVGQV8/"}, {"code": "FXEVLY", "name": "Bruno Bodin", "avatar": null, "biography": null, "public_name": "Bruno Bodin", "guid": "eec8631f-e234-5c88-a872-55b6f0569a9b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FXEVLY/"}, {"code": "ZBYQTZ", "name": "Bruno Bodin", "avatar": null, "biography": null, "public_name": "Bruno Bodin", "guid": "abdda3d1-7825-5023-a221-c8b39a95e2b7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZBYQTZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DMYH7U/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DMYH7U/", "attachments": []}, {"guid": "abf8d8d2-dec9-5bf7-9275-1c3565024d25", "code": "BREVML", "id": 278, "logo": null, "date": "2026-06-10T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-278-llm-driven-multi-agent-framework-for-automated-risc-v-verification-stimulus-generation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BREVML/", "title": "LLM-Driven Multi-Agent Framework for Automated RISC-V Verification Stimulus Generation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Writing verification stimulus for RISC-V processors requires deep expertise across ISA specifications, microarchitectural implementation, and test framework APIs. We present an LLM-driven multi-agent framework that transforms a brief natural-language scenario description into a comprehensive, executable RISC-V test generator. Five specialized AI agents form a sequential enrichment\r\npipeline: an ISA expert expands intent into architecturally complete scenarios, an RTL analyst reads hardware source code to inject microarchitecture-targeted stress patterns, a framework specialist maps steps to concrete API calls, a builder synthesizes deployable code, and a validator ensures correctness through static checks and instruction-set-simulator execution. On the RISC-V Svadu extension, a 3-line scenario yields 490 lines of validated, simulation-passing code in under 13 minutes\u2014a \u223c40\u00d7 speedup versus an estimated\u223c8 hours of manual effort.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CZ9LJ9", "name": "Kavya Sri Endukuri", "avatar": null, "biography": "", "public_name": "Kavya Sri Endukuri", "guid": "14a3a031-b623-5d62-b553-51baedbcb73b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CZ9LJ9/"}, {"code": "79T8CQ", "name": "Nicholas Matus", "avatar": "https://cfp.riscv-europe.org/media/avatars/79T8CQ_uBaF0gH.webp", "biography": "Sr. Engineer at Tenstorrent. \r\n\r\nPreviously open sourced Riescue, a direct test framework and compliance test generator. I'm using this experience and leveraging AI to create RISC-V stimulus", "public_name": "Nicholas Matus", "guid": "610f70b9-46ca-523f-9ea2-bd4f461a7146", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/79T8CQ/"}, {"code": "UVSUHJ", "name": "Radha Govindaradjou", "avatar": "https://cfp.riscv-europe.org/media/avatars/UVSUHJ_OZqxXiG.webp", "biography": "", "public_name": "Radha Govindaradjou", "guid": "cab6ea05-f2d1-5414-b6f0-8a82a9fc1902", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UVSUHJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BREVML/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BREVML/", "attachments": []}, {"guid": "35ba1dab-9995-517a-aa8d-b4c1ac7248e5", "code": "FFPCHP", "id": 329, "logo": null, "date": "2026-06-10T15:50:00+02:00", "start": "15:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-329-concolic-execution-guided-hybrid-whitebox-fuzzing-for-risc-v-processors", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FFPCHP/", "title": "Concolic Execution Guided Hybrid Whitebox Fuzzing for RISC-V Processors", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Verification remains a key bottleneck in the design of modern RISC-V processors, particularly for deep corner cases that are difficult to reach with conventional verification techniques. Coverage-guided hardware fuzzing provides fast exploration, but often relies on coarse-grained coverage feedback and blind mutation, leading to shallow exploration. Symbolic and concolic methods offer control path reasoning, but their practicality is limited by path explosion and high solver cost on realistic RTL processor designs.\r\nWe present a concolic execution guided hybrid whitebox fuzzing framework for RISC-V processors with FPGA acceleration. The framework combines RTL static analysis, concolic solving, and high-throughput fuzzing to balance exploration of hard-to-trigger deep processor behaviors with fuzzing efficiency. It extracts the processor control-flow graph from RTL, instruments synthesizable control path monitoring, and uses the collected path conditions to steer test generation toward high-value unexplored paths. We further map the DUT and fuzzer on FPGA programmable logic, while running concolic engine and SMT solver on the on-board ARM processor to accelerate the hybrid whitebox fuzzing process through an end-to-end heterogeneous architecture.\r\nWe evaluate the approach on open-source RISC-V processors, including CVA6, Ibex, and PicoRV32. Results show that our approach can achieve 1.33x higher coverage than SOTA fuzzers and explore deep corner coverage points that are difficult to trigger with existing approaches.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "YSWUEA", "name": "Zijian Jiang", "avatar": "https://cfp.riscv-europe.org/media/avatars/YSWUEA_8yT5Dlj.webp", "biography": "", "public_name": "Zijian Jiang", "guid": "bc5aef4e-34a5-537c-a9d3-cb5b52e70aab", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YSWUEA/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FFPCHP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FFPCHP/", "attachments": []}, {"guid": "0b09d144-6ffc-5997-accc-e9d8aecea75c", "code": "RP8QNP", "id": 235, "logo": null, "date": "2026-06-10T16:00:00+02:00", "start": "16:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-235-scalable-symbolic-quick-error-detection-using-lightweight-processor-level-abstraction", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RP8QNP/", "title": "Scalable Symbolic Quick Error Detection using Lightweight Processor-Level Abstraction", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Symbolic Quick Error Detection (SQED) streamlines processor verification by checking a microarchitecture-agnostic self-consistency property using bounded model checking (BMC). While effective in detecting bugs without manual property specification, SQED suffers from severe scalability limitations due to state explosion in complex designs. This paper introduces RDM-SQED to mitigate this bottleneck by reducing the resource-intensive duplicate mode with a lightweight Processor-Level Abstraction (PLA). The PLA captures software-visible behaviors through a concise set of Elementary Instructions (EIs). To further constrain the verification logic, we propose a recursive refinement algorithm that generates a minimal EI set. Experimental evaluation on an out-of-order RISC-V processor demonstrates that RDM-SQED significantly outperforms existing variants in both scalability and bug\r\ndetection efficiency, successfully identifying bugs that cause timeouts in other methods.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "XHATSH", "name": "Yufeng Li", "avatar": null, "biography": "I am currently an Assistant Research Fellow at the Center for Advanced Computer Systems, Institute of Computing Technology, Chinese Academy of Sciences. My research interests include formal methods, hardware-software model checking, and deep integration of hardware and software. I completed my Ph.D. in Software Engineering at the Institute of Software, Chinese Academy of Sciences in 2024, and received my Bachelor's degree in Statistics from Northeast Normal University in 2017.", "public_name": "Yufeng Li", "guid": "0ab58422-8443-5be8-b813-8700ad45bae6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/XHATSH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RP8QNP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RP8QNP/", "attachments": []}, {"guid": "511f311e-42b6-57e2-b32d-447082cdf48f", "code": "CBLJYX", "id": 255, "logo": null, "date": "2026-06-10T16:10:00+02:00", "start": "16:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-255-ai-driven-testlist-generation-for-risc-v-core-verification", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CBLJYX/", "title": "AI-Driven Testlist Generation for RISC-V Core Verification", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Verifying modern RISC-V cores requires qualifying every merge request (MR) against a large and evolving test space spanning ISA extensions, micro-architectural features, and system-level scenarios. Manually selecting appropriate tests for each MR is time-consuming and error-prone, and does not scale with the rate of RTL changes. This work presents an AI-driven testlist generator that automatically derives MR-specific regression lists for a production RISC-V core verification environment. The tool analyzes Git diffs for an MR, infers impacted features using a combination of static rules and large language models (LLMs), and synthesizes targeted regressions across multiple test generators. The resulting flow reduces MR-qualification effort, improves repeatability, and provides a concrete path toward coverage-driven, closed-loop test selection for RISC-V core verification.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "WKX3LL", "name": "Vikas Dubey", "avatar": null, "biography": "", "public_name": "Vikas Dubey", "guid": "e3e2ec48-32ef-5ddb-a017-439d842a0eb7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WKX3LL/"}, {"code": "7VGRPR", "name": "Abhishek Rajgadia", "avatar": null, "biography": "", "public_name": "Abhishek Rajgadia", "guid": "c74b6389-7244-51e0-b1af-425751d95c4b", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7VGRPR/"}, {"code": "9GVMZW", "name": "Shubham Singla", "avatar": null, "biography": "", "public_name": "Shubham Singla", "guid": "175584a5-2497-5e08-b4e1-170c99cfde08", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9GVMZW/"}, {"code": "UVSUHJ", "name": "Radha Govindaradjou", "avatar": "https://cfp.riscv-europe.org/media/avatars/UVSUHJ_OZqxXiG.webp", "biography": "", "public_name": "Radha Govindaradjou", "guid": "cab6ea05-f2d1-5414-b6f0-8a82a9fc1902", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UVSUHJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CBLJYX/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/CBLJYX/", "attachments": []}], "Poster Island B": [{"guid": "1f82c1b9-c432-50c3-856a-be049befa988", "code": "LZ7U8Y", "id": 289, "logo": null, "date": "2026-06-10T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-289-using-risc-v-e-trace-for-effective-insights-for-risc-v-vector-optimizations", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LZ7U8Y/", "title": "Using RISC-V E-Trace for effective insights for RISC-V Vector Optimizations", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "RISC-V E-Trace is a powerful tool for observing the execution of a CPU. Optimizing code to use RISC-V Vector instructions brings novel challenges, and gaining real-time insight into the code as it executes helps quickly iterate to better solutions. The ability of E-Trace to capture runtime \"vector length\" (vl CSR) and instruction execution, together with its very compressed nature makes it an ideal choice as a tracing format. This keeps traces small, allows live-streaming E-Trace data for post-processing, and ultimately allows the software developer to easily understand the utilization of the vector unit. The end result is a very powerful workflow allowing fast iteration and development of low-level optimized software, with the execution of the code underpinned by QEMU and the RISC-V E-Trace format.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "DD9UV8", "name": "Harry van Haaren", "avatar": "https://cfp.riscv-europe.org/media/avatars/DD9UV8_66Ch1Zn.webp", "biography": "Harry has worked in software for 15+ years, with experience in real-time audio processing and open-source projects like OpenAV productions, to datacenter networking SIMD optimizations for DPDK, and now works with Openchip to advance the software ecosystem of Risc-V Vector instructions. As a data-driven technologies he's passionate about tooling to help achieve success, and has presented at many conferences on the topic. He holds 4 patents in the datacenter domain, and many open source contributions.\r\n\r\nIn his spare time Harry can be found playing badminton or sim-racing, with 24 hour races being the favorite!", "public_name": "Harry van Haaren", "guid": "2d2d4075-5e54-5317-b816-1d2e2db38d16", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DD9UV8/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LZ7U8Y/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LZ7U8Y/", "attachments": []}, {"guid": "bf076eff-8138-5819-b5f2-820f73697fe9", "code": "ESQB3N", "id": 156, "logo": null, "date": "2026-06-10T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-156-open-e-trace-infrastructure-tooling-for-evaluation-analysis-and-research", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ESQB3N/", "title": "Open E-Trace Infrastructure: Tooling for Evaluation, Analysis, and Research", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Tracing allows capturing timing sensitive behavior that would be obscured by other means of extraction that rely on code running on the HART itself, such as debugging hardware or instrumentation. The ratified specification \u201cEfficient Trace for RISC-V\u201d (E-Trace) defines a highly compressed yet relatively simple RISC-V-specific instruction and data tracing format. In combination with the program binary, E-Traces allow the complete reconstruction of a program\u2019s execution path. We present an open source Rust library and CLI tool that allows both inspection of traces via an intuitive text interface and converting traces to other formats for analysis by downstream tools. While proprietary solutions for consuming E-Traces exist, this is, to our knowledge, the first open source tool suitable for use in production. Our tooling makes E-Trace-based augmentation of CI flows feasible. Based on traces collected during program execution, the CLI tool enables additional checks and metrics (e.g., coverage). Engineers may also use the tool to gain a better understanding of a failure. Use-case-specific checks may be implemented using the library. We also developed a QEMU plugin that enables experimenting with and evaluating such CI and development flows before any hardware investment, significantly lowering the entry barrier. The plugin serves as a configurable trace encoder, controlled solely by plugin arguments, that produces a trace file on the host.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3PBURS", "name": "Julian Ganz", "avatar": null, "biography": "Research Assistant at FZI Forschungszentrum Informatik", "public_name": "Julian Ganz", "guid": "517dc444-8cb3-5550-99d8-d61f9bf2c966", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3PBURS/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ESQB3N/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ESQB3N/", "attachments": []}, {"guid": "6e29ff5c-90c3-5e8b-9b79-ee7014acecd3", "code": "LWYLAF", "id": 149, "logo": null, "date": "2026-06-10T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-149-c-trace-an-open-source-risc-v-trace-encoder-and-its-ecosystem", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LWYLAF/", "title": "C-Trace: An Open-Source  RISC-V Trace Encoder and its Ecosystem", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Embedded tracing is essential for validating reliability, optimizing performance, and debugging complex embedded software. Despite rapid innovation in the RISC-V ecosystem, open and interoperable trace solutions have remained limited. C-Trace, developed in the context of the European TRISTAN project , addresses this gap with an open-source trace encoder and an extensible ecosystem approach. C-Trace introduces a modular trace-encoder architecture designed for efficient, continuous \u201clive\u201d observation. Beyond standard program-flow tracing, it supports hardware-assisted instrumentation that can automatically emit trace messages on access to selected control/status registers (CSRs) or on configurable watchpoints. This enables trace streams that carry richer runtime context (e.g., program counter, timestamps, direct data, and selected performance counters) and can support application use cases such as worst-case execution time (WCET) estimation, timing optimization, test-case prioritization, and integration-level coverage measurement. In addition to off-chip export, C-Trace can forward trace-triggered events internally to an on-chip CPU, enabling watchdog, runtime verification, or control-flow integrity (CFI) checking functionality. Finally, C-Trace is provided under a dual-licensing model (CERN-OHL-S and a non-copyleft commercial option) to balance open collaboration with industrial IP needs.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HPYJC9", "name": "Alexander Weiss", "avatar": "https://cfp.riscv-europe.org/media/avatars/HPYJC9_ueNgQX5.webp", "biography": "", "public_name": "Alexander Weiss", "guid": "613db330-e8ea-5d22-bbe9-dd1ce5fd954f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HPYJC9/"}, {"code": "VDLKLP", "name": "Simon Wegener (AbsInt)", "avatar": null, "biography": "Simon Wegener completed his Master\u2019s degree in computer science at the University of Saarland. He joined AbsInt in 2011, specializing in static analysis of binary code. Since then, he has contributed to a multitude of German and European research projects and authored or co-authored a number of peer-reviewed publications on timing analysis for safety-critical embedded systems. As part of TRISTAN, and together with five project partners, he worked on a tracing ecosystem for RISC-V.", "public_name": "Simon Wegener (AbsInt)", "guid": "20fcc662-2135-5f8c-99ec-5210911c0baf", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VDLKLP/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LWYLAF/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LWYLAF/", "attachments": []}, {"guid": "ca90569e-dd9d-57ba-82eb-f97318e39f58", "code": "DVVW8V", "id": 86, "logo": null, "date": "2026-06-10T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-86-window-level-telemetry-for-runtime-performance-and-reliability-monitoring-in-risc-v-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DVVW8V/", "title": "Window-Level Telemetry for Runtime Performance and Reliability Monitoring in RISC-V Systems", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "RISC-V\u2013based processors and ML accelerators are increasingly targeted for latency-sensitive domains such as automotive Software-Defined Vehicle platforms and edge systems, where runtime observability is essential for performance validation and early fault diagnosis. Although RISC-V standardizes architectural and hardware performance monitoring counters, raw cumulative snapshots do not directly provide window-level deltas or streaming metrics required for real-time analytics. To bridge this gap, we present a monitoring tool that implements a window-level telemetry pipeline to enable real-time observability. It converts cumulative counters into per-window delta values, selects a curated metric set, and computes derived metrics. The resulting telemetry is recorded simultaneously as CSV and structured logs (NDJSON) and streamed to external consumers via ZeroMQ for runtime processing. The approach is validated using a cycle-level gem5 RISC-V simulation, demonstrating 2\u20133 ms host-side processing per 10 ms window with minimal overhead. The modular design incorporates a source-agnostic acquisition layer, allowing the input backend to be replaced by hardware performance counters with minimal changes to the core processing and output interfaces.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "ZBETVH", "name": "Arda \u00d6zt\u00fcrk", "avatar": null, "biography": "", "public_name": "Arda \u00d6zt\u00fcrk", "guid": "273c0b69-12ec-58b6-876a-553a8064b7cf", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZBETVH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DVVW8V/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DVVW8V/", "attachments": [{"title": "Poster", "url": "/media/eu-summit-2026/submissions/DVVW8V/resources/RISC-V_Summit_Poster_4cDyWw0.pdf", "type": "related"}]}, {"guid": "abb350fb-bef5-5a61-bed3-7e693a4b09e8", "code": "RWGSHJ", "id": 302, "logo": null, "date": "2026-06-10T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-302-retrace-ex-interactive-trace-analysis-framework-for-risc-v-hardware-optimization", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RWGSHJ/", "title": "RETrace EX: Interactive Trace Analysis Framework for RISC-V Hardware Optimization", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Identifying the optimal hardware configuration for running complex workloads on edge devices is critical for reducing cost and maximizing performance. Tailoring hardware designs to specific applications significantly increases resource efficiency, which is essential to meet the strict performance constraints. Unfortunately, exploring the design space at the hardware-level is difficult due to the complexity of the hardware design processes. \r\nWe present RETrace EX, an interactive analysis framework for identifying profitable hardware optimizations from system-level execution traces. The tool automatically identifies custom ISA extensions and estimates their performance impact as well as the expected area cost. To adjust the optimization goal for arbitrary systems and design capabilities, the user can choose from a range of preset scoring functions or specify a custom one. Applied to a wide range of representative embedded and edge artificial intelligence workloads, we are able to identify individual custom instructions that yield expected performance improvements of up to 32 % for Embench and 60 % for MLPerf Tiny benchmarks. The framework is provided as open source.", "description": "This submission presents a new user-friendly framework to identify and design profitable custom RISC-V extensions.", "recording_license": "", "do_not_record": false, "persons": [{"code": "GZR397", "name": "Jan Zielasko", "avatar": "https://cfp.riscv-europe.org/media/avatars/GZR397_b6h1QVU.webp", "biography": "Jan Zielasko is a PhD student at the University of Bremen and a researcher at the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). His research focuses on Virtual Prototype-driven tracing, analysis, verification and hardware optimization.", "public_name": "Jan Zielasko", "guid": "d39b427a-60be-5129-9398-f24e60ba7089", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GZR397/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RWGSHJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RWGSHJ/", "attachments": []}, {"guid": "96259fc7-5009-5eee-8b66-baeb08bc638c", "code": "PTSN7C", "id": 224, "logo": null, "date": "2026-06-10T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-224-holographic-execution-a-hyperdimensional-computing-approach-for-robust-risc-v-instruction-decoding", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PTSN7C/", "title": "Holographic Execution: A Hyperdimensional Computing Approach for Robust RISC-V Instruction Decoding", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The evolution of modern computing towards emerging paradigms, such as In-Memory Computing (IMC), is severely limited by the high intrinsic noise of these memory technologies.\r\n        Simultaneously, conventional Von Neumann architectures exhibit data-dependent execution and power profiles, leaving embedded systems highly vulnerable to physical Side-Channel Attacks. \r\n        In this extended abstract, we propose a novel paradigm based on Hyperdimensional Computing for encoding and decoding RISC-V instructions. By mapping standard assembly instructions into a neural-inspired holographic representation and storing them in superposition, leveraging the capacity of high-dimensional spaces, the traditional decoding logic is replaced by a highly parallel Associative Memory. Our Design Space Exploration compares 1-bit Binary and 8-bit Integer representations, evaluating the trade-off between instruction capacity (chunk size) and dimensionality. Furthermore, we demonstrate the intrinsic fault tolerance and security-by-design of the architecture: a binary HDC system maintains 100% decoding accuracy even when subjected to a 5% physical memory corruption, while its constant-time execution and massive pseudo-random switching activity inherently mask side-channel leakages. This paradigm paves the way for ultra-robust, secure, and ECC-free RISC-V pipelines tailored for next-generation processing cores.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "KMDHNK", "name": "Marcello Barbirotta", "avatar": "https://cfp.riscv-europe.org/media/avatars/KMDHNK_Nv2E6Rx.webp", "biography": "", "public_name": "Marcello Barbirotta", "guid": "295c21cd-7f1d-521e-a943-3f569779fd82", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KMDHNK/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PTSN7C/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PTSN7C/", "attachments": []}, {"guid": "188ac4a8-0e19-56eb-a76d-381cd5554d1b", "code": "LNBB8V", "id": 184, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/LNBB8V/RISCV-Perf_framework_GG5xWPc__5HoxmsI.webp", "date": "2026-06-10T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-184-riscv-perf-a-performance-modeling-framework-for-risc-v-processors-integrated-with-spike", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LNBB8V/", "title": "RISCV-Perf: A Performance Modeling Framework  for RISC-V Processors Integrated with Spike", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Microarchitectural performance evaluation is an essential step in modern processor design and architecture exploration. However, developing a cycle-accurate simulator from scratch requires implementing both instruction semantics and detailed microarchitectural models, which significantly increases development complexity.\r\n\r\nThis work presents RISCV-Perf, a lightweight performance modeling framework designed to integrate with the Spike RISC-V functional simulator. The framework decouples functional execution from cycle-level timing simulation through a minimal instruction interface that captures key instruction attributes such as program counters, operand registers, and memory access information. By reusing the functional correctness provided by Spike, RISCV-Perf focuses solely on modeling microarchitectural timing behavior.\r\n\r\nRISCV-Perf adopts an execution-driven simulation approach, enabling cycle-level modeling of superscalar out-of-order processors without generating execution traces. The timing model represents major microarchitectural components including an instruction flow model, register renaming mechanism, memory operation pipelines, and cache hierarchy interactions. In addition, the framework is implemented using a modular policy-based design, allowing architectural components such as branch predictors and cache policies to be easily replaced or extended.\r\n\r\nExperimental evaluation using the MiBench benchmark suite on an RV64GC configuration demonstrates that RISCV-Perf can effectively generate performance insights such as CPI behavior and branch prediction miss rates across workloads. These results show that the framework provides a practical platform for workload characterization and microarchitectural policy exploration.", "description": "RISCV-Perf is a research framework designed to support microarchitectural performance exploration for RISC-V processors while maintaining tight integration with existing functional simulators. Unlike many trace-driven simulators that require generating and storing large instruction traces, RISCV-Perf follows an execution-driven approach by directly interfacing with the Spike functional simulator. This design avoids trace generation overhead and simplifies modeling of speculative execution behavior.\r\n\r\nThe framework introduces a lightweight instruction interface that extracts essential instruction information during execution and forwards it to the timing model through an instruction pool and instruction buffer. This mechanism decouples functional execution from timing simulation and enables superscalar modeling where multiple instructions can be processed per cycle.\r\n\r\nThe timing model approximates the structure of modern superscalar out-of-order processors, including register renaming, instruction scheduling, memory operation handling, and cache hierarchy interactions. The design follows a modular architecture that allows researchers to experiment with alternative microarchitectural policies, such as different branch predictors or cache replacement algorithms, without modifying the overall simulation framework.\r\n\r\nRISCV-Perf aims to provide a practical and extensible platform for early-stage architecture exploration, workload analysis, and microarchitectural policy evaluation for RISC-V systems.", "recording_license": "", "do_not_record": false, "persons": [{"code": "DKY9YN", "name": "Tsung-LI", "avatar": "https://cfp.riscv-europe.org/media/avatars/DKY9YN_fJy5p6r.webp", "biography": "Tsung-Li Chen is a master\u2019s student in the Department of Computer Science and Information Engineering at National Taiwan University of Science and Technology (NTUST). His research interests focus on computer architecture, microarchitectural performance modeling, and RISC-V processor design. His current work explores lightweight performance simulation frameworks for modern out-of-order processors by integrating timing models with functional simulators. Tsung-Li has been actively involved in RISC-V related research and previously presented work at the RISC-V Summit North America.", "public_name": "Tsung-LI", "guid": "6ab40cd7-82ee-53f8-b3cd-7e235eb8c668", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DKY9YN/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LNBB8V/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LNBB8V/", "attachments": []}, {"guid": "97ae0100-53f1-5d7f-9151-2ec35427b923", "code": "ALLVDR", "id": 160, "logo": null, "date": "2026-06-10T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-160-strive-vp-llvm-based-performance-simulator-for-risc-v-processors", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ALLVDR/", "title": "STRiVe-VP: LLVM-based performance simulator for RISC-V processors", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "In this paper we present STRiVe-VP, a hybrid RISC-V simulation framework that unifies functional and timing simulation by leveraging LLVM\u2019s compiler infrastructure. Built on RISC-V VP++, it translates executed instructions into LLVM MCInst and LLVM MCA Instruction objects, which are injected into an extended LLVM MCA pipeline. Custom hardware units (cache, prefetch buffer, branch predictor) are modeled, allowing the combination of static scheduling information with dynamic effects from control flow and memory behavior. This direct integration enables timing-aware decisions using live architectural state and provides unified functional and timing debugging. Validation against an FPGA prototype of an in-order, single-issue rv32emc_zfinx core shows that STRiVe-VP matches FPGA cycle counts exactly for several benchmarks and across multiple optimization levels, demonstrating cycle-accurate performance estimation and a solid basis for extending to more complex RISC-V microarchitectures.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "TRGRUX", "name": "Giorgio Marletta", "avatar": null, "biography": "", "public_name": "Giorgio Marletta", "guid": "c0945ad2-91c0-5112-a281-009c866d404f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TRGRUX/"}, {"code": "MBTKMS", "name": "Giovanni Di Guardo", "avatar": null, "biography": "", "public_name": "Giovanni Di Guardo", "guid": "8ce4e37f-678f-5e88-b4f2-6000d28b0c1c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MBTKMS/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ALLVDR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ALLVDR/", "attachments": []}, {"guid": "a382153f-d21c-5976-bf92-433f2d25e45c", "code": "RUUDYM", "id": 123, "logo": null, "date": "2026-06-10T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-123-transaction-level-analysis-and-optimization-of-decision-diagram-packages-on-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RUUDYM/", "title": "Transaction-Level Analysis and Optimization of Decision Diagram Packages on RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The complexity of modern electronic systems has increased significantly over the past decades due to continuous technological advances. To cope with this growing complexity, data structures, algorithms, and the underlying hardware platforms used in Electronic Design Automation (EDA) must be continuously improved. Decision Diagrams (DDs) constitute a fundamental graph-based structure for formal verification, enabling efficient representation and algorithmic manipulation of switching functions. Owing to their practical relevance, numerous optimizations have been incorporated into existing DD software packages. However, these optimizations are typically designed in an architecture-agnostic manner and do not explicitly exploit characteristics of a specific target platform. As a consequence, architecture-specific optimization opportunities may remain untapped. In this work, a transaction-level analysis of a representative DD package is conducted using a RISC-V-based trace analysis tool to investigate this potential. The study reveals recurring instruction sequences with strong potential for hardware-level aggregation, enabling more efficient hardware designs. Furthermore, the derived insights provide guidance for higher-level software optimizations.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "KJFQ3D", "name": "Rune Krauss", "avatar": null, "biography": "", "public_name": "Rune Krauss", "guid": "a0335d30-383c-59e7-850a-66345509b421", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KJFQ3D/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RUUDYM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RUUDYM/", "attachments": []}, {"guid": "b1961a8b-8d12-5b30-ad96-645e062e3950", "code": "N7AVZD", "id": 165, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/N7AVZD/session_image_oYR1wlK_6JBRryV.webp", "date": "2026-06-10T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-165-quick-qemu-internal-checkpointing-for-gem5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/N7AVZD/", "title": "QUICK: QEMU Internal Checkpointing for Gem5", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The gem5 simulator is a widely used tool for microarchitectural research, but often incurs prohibitive execution times. gem5 mitigates this cost through checkpoint-based resumption, yet existing checkpoint-generation mechanisms remain slow, non-portable, or both---significantly limiting iterative hardware-software exploration.\r\n\r\nWe introduce **QUICK** (**Q**EM**U** **I**nternal **C**hec**k**pointing for gem5), a framework that enables fast, automated, and deterministic generation of gem5-compatible checkpoints directly within QEMU.\r\nQUICK integrates full-system checkpointing into QEMU\u2019s TCG engine, capturing architectural, memory, and essential device state without external orchestration. QUICK substantially reduces checkpoint-generation overhead while preserving existing gem5 workflows, enabling scalable and systematic microarchitectural studies.\r\n\r\nInitial validation demonstrates correct cross-simulator state transfer and consistent workload resumption.", "description": "QUICK implements checkpoint generation directly inside the QEMU TCG execution engine. At fixed instruction intervals, QUICK automatically creates full-system checkpoints in a format compatible with gem5.\r\n\r\nThese checkpoints capture the complete CPU state\u2014including integer, floating-point, and vector registers, as well as miscellaneous registers such as the program counter\u2014along with the entire main memory. Additionally, QUICK records peripheral states such as timers and UARTs, preventing potential kernel-level hangs during restoration.\r\n\r\nThese checkpoints can later be restored in gem5 to enable detailed cycle-accurate performance evaluation. By combining QEMU\u2019s high-speed functional emulation with gem5\u2019s detailed microarchitectural modeling, QUICK leverages the strengths of both platforms.", "recording_license": "", "do_not_record": false, "persons": [{"code": "JVS889", "name": "Qi Shao", "avatar": "https://cfp.riscv-europe.org/media/avatars/JVS889_gKvCg73.webp", "biography": "I am a PhD student in Chamers University of Technology and currently in Barcelona Supercomputing Center. My research is about optimizating performance of memory system for CPU and GPU workloads. I am familiar with CPU/GPU archiecture and also gem5 and accel-sim simulators.", "public_name": "Qi Shao", "guid": "8171a56f-467e-56fc-86ec-def6d4a4a27c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JVS889/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/N7AVZD/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/N7AVZD/", "attachments": []}, {"guid": "5d4474fb-bf10-534a-ad5b-05fbe89bae8c", "code": "SCCL9S", "id": 306, "logo": null, "date": "2026-06-10T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-306-virtual-prototyping-of-pixel-detector-architecture-via-co-simulation-of-pixesl-and-gvsoc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SCCL9S/", "title": "Virtual Prototyping of Pixel Detector Architecture via Co-Simulation of PixESL and GVSoC", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "This work presents a co-simulation methodology for the evaluation of pixel detector architecture, combining two independently developed tools: PixESL, a virtual prototyping framework targeting the architectural exploration and performance assessment of pixel detector systems, and GVSoC, a full-platform simulator for RISC-V IoT SoCs.  \r\nIn parallel with PixESL's development, studies on integrating RISC-V-based SoCs with pixel detector readout circuitry were carried out using GVSoC. Rather than relying on fixed ASIC readout architectures, this approach introduces a programmable processing layer alongside the pixel readout, enabling software-level control over data handling.  \r\nIn the outlined co-simulation flow, PixESL generates data for a given readout architecture and set of stimuli, while GVSoC simulates the target application executing on the PULP RISC-V SoC platform. Additionally, in order to accurately capture the overhead of data movement within this chain, a virtual prototype of the DMA block responsible for transfers between pixel readout and SoC was developed. Together, these components provide a unified view of the full readout chain, from initial stimulus to processed data, opening possibilities for more informed hardware-software co-design in future detectors.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "ELQNGT", "name": "mobradovic00", "avatar": null, "biography": "Mihailo Obradovic is an electronics engineer at CERN. His current work focuses on co-simulation methodologies for hardware modelling, with a specific interest in evaluating RISC-V SoC integration into detector readout systems and investigating how open-standard processor architectures can satisfy the performance and reliability constraints typical of high-energy physics applications. Mihailo holds a Bachelor's degree in electronics engineering from the University of Belgrade.", "public_name": "mobradovic00", "guid": "10262821-89aa-54c8-a226-b51840b8826c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ELQNGT/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SCCL9S/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SCCL9S/", "attachments": []}, {"guid": "8455872d-087e-546a-966c-acc5bfa5728e", "code": "F7UKA3", "id": 291, "logo": null, "date": "2026-06-10T14:00:00+02:00", "start": "14:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-291-hardware-synthesized-monitor-actuator-design-patterns-a-proof-of-concept-application", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UKA3/", "title": "Hardware-Synthesized Monitor-Actuator Design Patterns: a Proof-of-Concept Application", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "As system complexity increases, so does the difficulty in demonstrating their overall correctness. The Monitor-Actuator design pattern is one the main approaches in the literature proposing ways to ensure that systems can work safely, even in the presence of undetected or unpatched system defects. This design pattern consists of coupling verification monitors to, at execution time, verify if a target system is executing as expected and intervene when needed. Therefore, maximizing the isolation between the target system and the monitoring unit becomes a fundamental factor to reduce mutual interference, both in functionality and in terms of computational overhead. This work presents a Monitor-Actuator proof of concept system developed for the PolarFire SoC Icicle Kit. The system consists of a target application executing on the PolarFire SoC\u2019s processing system and a dedicated runtime verification monitor IP executing on the programmable logic unit. We detail how the monitor IP is generated from a formal specification that is used to, first synthesize it's equivalent CPP code, and later serve as input to the process of high-level synthesis of hardware description language. The description of the development process and setup is designed to serve as a reference for future applications requiring low interference hardware synthesized runtime monitors capable of detecting user-specified property violations in a platform\u2019s hardcore and softcore RISC-V processors.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "AZDJF8", "name": "Giann Spilere Nandi", "avatar": "https://cfp.riscv-europe.org/media/avatars/AZDJF8_OOL6DvV.webp", "biography": "Driven by complex problem-solving, I am a researcher at VORTEX-CoLab specialising in the safety, cybersecurity, and formal verification of real-time embedded systems. My work focuses on bridging the gap between hardware and software to build dependable, high-performance architectures. With an academic and professional background spanning Brazil, the Netherlands, and Portugal, I have contributed to top-tier research in cyber-physical systems, with publications in premier venues like RTSS and DSN. Beyond research, I also have experience teaching undergraduate and master\u2019s level courses in Assembly, C, and NuSMV model checking. I am currently focusing on identifying industry-ready applications for applied research and cross-border collaboration.", "public_name": "Giann Spilere Nandi", "guid": "ba517ded-aed4-56a0-ad27-b6c765e652f6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AZDJF8/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UKA3/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UKA3/", "attachments": []}, {"guid": "39cbd49e-9c85-5ac0-b26a-af11dfad5cfb", "code": "F39Y3T", "id": 198, "logo": null, "date": "2026-06-10T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-198-emix-emulating-beyond-single-fpga-limits", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F39Y3T/", "title": "EMiX: Emulating Beyond Single-FPGA Limits", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale\r\nmulti-core systems increasingly exceed the hardware resource capacity of a single FPGA, limiting the feasibility of full-system emulation. To address this challenge, we introduce EMiX, a scalable multi-FPGA framework that enables distributed emulation of multi-core RISC-V architectures beyond single-FPGA resource limits. EMiX systematically partitions a monolithic multi-core design into multiple components and deploys them across multiple interconnected FPGAs, effectively exploiting inter-FPGA interconnects to balance scalability and performance without requiring fundamental RTL redesign. We prototype EMiX with a 64-core architecture across eight interconnected Alveo U55c FPGAs (scalable on core and FPGA counts), successfully demonstrating full-system execution including Linux boot. EMiX will be released as an open-source platform.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HAFK3H", "name": "Behzad Salami", "avatar": null, "biography": "", "public_name": "Behzad Salami", "guid": "ee06600b-db32-5436-b31c-c87010a131e3", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HAFK3H/"}, {"code": "XNB8ML", "name": "Alexander Kropotov", "avatar": null, "biography": null, "public_name": "Alexander Kropotov", "guid": "f9cf55b7-1206-5ac0-8238-6dbd9c0955ef", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/XNB8ML/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F39Y3T/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F39Y3T/", "attachments": []}, {"guid": "c6a1cdd5-f784-5da5-b88d-3ae17f2c31a9", "code": "BWUHVG", "id": 316, "logo": null, "date": "2026-06-10T14:20:00+02:00", "start": "14:20", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-316-unleashing-the-penguin-programmable-device-model-for-verifying-risc-v-iommu-using-linux", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BWUHVG/", "title": "Unleashing the Penguin: Programmable Device Model for verifying RISC-V IOMMU using Linux", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "RISC-V provides complex platform-level specifications, such as the RISC-V IOMMU, in addition to the core-level ISA to support a complete open computing platform. The RISC-V IOMMU delves into intricate hardware-software interactions, page table formats, command and fault queue handling, and multi-stage address translations that are as critical to system correctness but significantly harder to validate. \r\nAn essential part of verifying the IOMMU involves executing real-world scenarios as would be presented via Linux. However, setting up a full SoC-level environment to run Linux sequences is time-consuming and resource-intensive. As a result, critical IOMMU interactions are often validated too late or not at all.\r\n\r\nWe have developed a programmable device model that permits Linux testing of RISC-V IOMMU RTL without requiring PCIe or DMA-capable devices to be integrated into the design under test. \r\nThe device model has been pivotal in creating an emulation-friendly subsystem-level environment that integrates high-performance RISC-V cores (TT-Ascalon) with RISC-V IOMMU. \r\nThe subsystem runs Linux as the primary stimulus source, reusing the upstream kernel IOMMU driver to exercise the IOMMU implementation against the RISC-V specification with complex and realistic scenarios. \r\n\r\nWe will present the design and operation of this device model, the subsystem environment and related software, and shall share our findings, including how it enabled us to quickly uncover corner-case bugs in our IOMMU RTL and its software drivers, thereby complementing traditional IP-level validation approaches.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "NBNWDQ", "name": "Sai Rajat Goparaju", "avatar": "https://cfp.riscv-europe.org/media/avatars/NBNWDQ_aqwWgTd.webp", "biography": "Sai Rajat is an Engineer working on building high performance RISC-V CPU Cores and System IP at Tenstorrent. His work is deeply rooted in computer architecture, with a specific technical focus on IOMMU and cache coherency. He holds a degree in Electrical and Electronics Engineering from BITS Pilani. Driven by a belief in RISC-V ISA and a strong interest in advancing hardware systems, he joined Tenstorrent in 2024 after stints at Google Hardware and Samsung India.", "public_name": "Sai Rajat Goparaju", "guid": "cd6eb1d1-2566-5766-b26a-ca772fc6acb6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/NBNWDQ/"}, {"code": "PMSSPA", "name": "Nicholas Piggin", "avatar": null, "biography": "Tenstorrent systems software developer", "public_name": "Nicholas Piggin", "guid": "fbea2d7b-3e15-5d9a-b59b-000e597a4286", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/PMSSPA/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BWUHVG/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BWUHVG/", "attachments": []}, {"guid": "7fb68b5c-a9cb-536e-bbf6-2e2ee833fbb5", "code": "TTPKFR", "id": 337, "logo": null, "date": "2026-06-10T15:30:00+02:00", "start": "15:30", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-337-cycle-accurate-iopmp-reference-model-with-configurable-interfaces-integration-tests-and-a-cva6-soc-implementation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TTPKFR/", "title": "Cycle-Accurate IOPMP Reference Model with Configurable Interfaces, Integration Tests, and a CVA6 SoC Implementation", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "In RISC-V based systems, a key security mecha-\r\nnism is the Input-Output Physical Memory Protection (IOPMP)\r\nsubsystem, which enables controlled access to shared memory\r\nand peripherals by non-core initiators [1]. While the specification\r\ndefines functional behavior, the availability of a publicly available\r\ncycle-accurate reference model will encourage early SoC-level\r\nintegration.\r\nThis paper presents an open-source cycle-accurate IOPMP\r\nreference model consisting of a SystemVerilog wrapper integrated\r\nwith a C-based functional reference model. The SystemVer-\r\nilog wrapper models pipeline timing, transaction ordering, and\r\nstandard bus interfaces, while the C-based reference model\r\nprovides specification-compliant functional evaluation of address\r\nmatching, permission checking, and priority resolution. The\r\ncombined architecture enables both functional correctness and\r\ntiming-accurate system-level validation.\r\nThe model supports AMBA AXI4 for transaction enforcement\r\nand AMBA AHB3-Lite for configuration, to enables seamless re-\r\nplacement with actual RTL. A reusable suite of architectural-level\r\nbare-metal tests is provided, and the approach is demonstrated\r\nthrough integration in an open-source CVA6-based SoC [4].\r\nIndex Terms\u2014RISC-V, IOPMP, SoC Security, Reference\r\nModel, Cycle-Accurate Modeling", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "9E8KPQ", "name": "Gull Ahmed", "avatar": null, "biography": "", "public_name": "Gull Ahmed", "guid": "2d2e0876-c7e8-5616-b4ea-8c8bb4fd2698", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9E8KPQ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TTPKFR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TTPKFR/", "attachments": []}, {"guid": "75907672-2cc1-5a47-b1ad-e4c9172a2f1c", "code": "B8BJHQ", "id": 293, "logo": null, "date": "2026-06-10T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-293-gpu-accelerated-parallel-simulation-for-risc-v-multi-core-ip-verification", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B8BJHQ/", "title": "GPU-Accelerated Parallel Simulation for RISC-V Multi-Core IP Verification", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Functional verification of RISC-V multi-core IPs is bottleneck by the sequential nature of convectional CPU-based event driven simulation, where coverage closure timelines scale linearly with core count and configuration complexity. This paper presents a GPU- accelerated parallel simulation framework that offloads stimulus generation, constraint solving, and concurrent coverage computation to GPU hardware while retaining UVM testbench orchestration on the CPU host. The framework employs a heterogeneous partitioning tasks including constrained-random transaction generation, functional coverage bin evaluation, and reference model computation are parallelized across GPU threads using CUDA kernels. The control, DUT RTL simulation, and sequential verification logic, ensuring complete compatibility with existing verification flows. Evaluated on RISC-V IP configurations ranging from 2 to 32 cores with AXI4 interconnect and MESI coherency protocol, the framework achieves up to 22x simulation speedup, reduces coverage closure time from 44 hours to 14 hours, and reaches 99 percent functional coverage versus 93 percent for CPU-only baselines within the same wall clock budget. The GPU acceleration advantage scales near -linearly with core count, making it particularly valuable for emerging many core RISC-V designs targeting automotive and data-center applications. The approach requires no modification to existing RTL or UVM testbench architectures, integrating via a lightweight GPU dispatch layer that operates on standard simulation interfaces.", "description": "This work addresses the growing simulation bottleneck in RISC-V multi-core verification by leveraging GPU parallelism for stimulus generation and coverage computation. It is relevant to the RISC-V community because verification cost dominates development timelines, especially as core counts increase. The framework fosters ecosystem growth by enabling smaller verification teams to achieve coverage closure on complex multi-core designs using commodity GPU hardware rather than expensive emulation platforms. Target audience include verification engineers, IP designers, and EDA researchers working on RISC-V multi core SoCs.", "recording_license": "", "do_not_record": false, "persons": [{"code": "VRNMVG", "name": "Abinaya Senthil", "avatar": "https://cfp.riscv-europe.org/media/avatars/VRNMVG_dYg7ftG.webp", "biography": "Abinaya Senthil is a Design Verification  Engineer at NXP Semiconductors, Austin, Texas specializing in UVM-based IP verification, System Verilog, CDC verification, and memory injection methodologies for complex IP designs. She is a founder of SiliconDV , a technical education platform for semiconductor verification engineers. She is a member on the IEEE WIE MRP award review committee and has presented CSTIC 2026 ( IEEE Xplore indexed). Her research focus on AI-driven verification optimization and GPU accelerated simulation for RISC-V architectures.", "public_name": "Abinaya Senthil", "guid": "0892a77d-b72d-5998-8356-f974e58bf144", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VRNMVG/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B8BJHQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B8BJHQ/", "attachments": []}, {"guid": "367277f0-6745-52f9-b76a-4379323c5407", "code": "LSXU7K", "id": 356, "logo": null, "date": "2026-06-10T15:50:00+02:00", "start": "15:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-356-wolvrix-a-systemverilog-native-graph-infrastructure-for-rtl-research", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LSXU7K/", "title": "Wolvrix: A SystemVerilog-Native Graph Infrastructure for RTL Research", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "We present **Wolvrix**, an open-source infrastructure that ingests Verilog-2005/SystemVerilog into GRH (Graph RTL Hierarchy), an SSA-based graph intermediate representation, and supports composable transformation passes with Verilog re-emission. Wolvrix models complex SystemVerilog semantics, including multi-event registers, multi-port memories, blackboxes, cross-module references, and DPI-C calls, within a uniform graph structure amenable to analysis and transformation. We describe GRH and Wolvrix's architecture, and present roundtrip re-emission on XiangShan and XuanTie C910 plus RepCut partitioning on XiangShan.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CYA7AS", "name": "Haojin Tang", "avatar": null, "biography": "", "public_name": "Haojin Tang", "guid": "21b84c25-6cd6-5bbe-9ccc-46a239eedf51", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CYA7AS/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LSXU7K/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LSXU7K/", "attachments": [{"title": "Wolvrix: A SystemVerilog-Native Graph Infrastructure for RTL Research", "url": "/media/eu-summit-2026/submissions/LSXU7K/resources/Wolvrix_A_SystemVeri_RDKOosU.pdf", "type": "related"}]}, {"guid": "50af7ecd-ab1d-5bb4-a826-c230affdab2a", "code": "3AVQMT", "id": 169, "logo": null, "date": "2026-06-10T16:00:00+02:00", "start": "16:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-169-the-risc-v-test-platform-an-extension-of-the-omnipresent-risc-v-test-environments", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3AVQMT/", "title": "The RISC-V test platform; an extension of the omnipresent RISC-V test environments", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper presents the riscv-test-platform, an enhanced set of environments built upon the riscv-test-env, designed to facilitate the execution of tests and benchmarks on RISC-V architectures atop bare-metal environments. Their balance between code complexity and features make them a flexible platform to execute software in both simulated and FPGA environments, bridging the gap between the two platforms, with the advantages that each provide. The result is a set of four environments that mimic the functionalities of the original riscv-test-env, with the addition of some benchmarking features, which exercise more parts of RTL designs and help verification teams spot mismatches in the early stages of development.", "description": "This paper discusses riscv-test-platform, an extensible test environment collection designed to build versions of a single test routine in multiple target configurations. As mentioned in the abstract, the project is based on the riscv-test-env repository, and makes a case for extensible bare-metal environments that unify common differences in RISC-V designs. It also explores two cases in which it helped our verification team improve test coverage and bug reproducibility.", "recording_license": "", "do_not_record": false, "persons": [{"code": "UJZHEH", "name": "Eloi Merino", "avatar": null, "biography": "Computer Science and Engineering graduate and Master\u2019s student in HPC, both at Universitat Polit\u00e8cnica de Catalunya. Working as a Junior Research Engineer at the Barcelona Supercomputing Center, developing solutions to advance verification of RISC-V designs.", "public_name": "Eloi Merino", "guid": "eab4681d-64df-5c26-9d34-9e1575b7631d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UJZHEH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3AVQMT/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3AVQMT/", "attachments": []}, {"guid": "f01346ae-2e51-59ac-8a64-0a745f64050e", "code": "ZBRZ7X", "id": 135, "logo": null, "date": "2026-06-10T16:10:00+02:00", "start": "16:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-135-benchmarking-the-vortex-risc-v-gpu-for-sparse-workloads", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBRZ7X/", "title": "Benchmarking the Vortex RISC-V GPU for Sparse Workloads", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Many computational problems require the processing of large sparse matrices, where the vast majority of entries are zero. The irregular distribution of the non-zero elements in these matrices stresses the memory system resulting in performance being bottlenecked by the memory bandwidth. On parallel architectures, workload imbalances also limit performance. Graphics Processing Units (GPUs) runnning sparse matrix kernels using state-of-the-art Basic Linear Algebra Subsystem (BLAS) libraries are central in modern HPC systems. Although RISC-V application processors are gaining in performance, RISC-V based GPUs are in an early stage of development. We benchmark sparse kernels both on modern HPC-grade GPUs and on Vortex, a RISC-V GPU that is gaining adoption. We analyse their performance under memory-bound workloads and report the gaps in software and hardware required to enable efficient sparse BLAS processing on RISC-V GPUs.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3FDPPB", "name": "Jules Dubois", "avatar": null, "biography": "", "public_name": "Jules Dubois", "guid": "5f3d616a-8940-5a43-a090-acc7ffe327a5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3FDPPB/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBRZ7X/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBRZ7X/", "attachments": []}], "Poster Island C": [{"guid": "7b4af0fd-852f-5036-8d84-678be8aaccf5", "code": "GLCJSG", "id": 73, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/GLCJSG/Ascalon_Poster_final_Updated__78m7bWj.webp", "date": "2026-06-10T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-73-a-doom-demo-journey-tenstorrent-s-ascalon-cpu-on-synopsys-emulation-and-prototyping-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GLCJSG/", "title": "A Doom Demo Journey: Tenstorrent's Ascalon CPU on Synopsys emulation and prototyping systems", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "This paper tells the incremental journey of taking Tenstorrent\u2019s Ascalon RISC\u2011V CPU IP from RTL and emulation to a playable DOOM demo on a Synopsys\u2019s prototyping platform. Along the way we describe the problems we overcame, and how we optimized our flows and the design. We close with a set of lessons and recommendations for teams who want to use emulation and prototyping and realistic workloads like DOOM to de\u2011risk RISC\u2011V IP adoption and accelerate hardware/software co\u2011design.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "PYBQJR", "name": "Rae Parnmukh", "avatar": "https://cfp.riscv-europe.org/media/avatars/PYBQJR_0kQ80xs.webp", "biography": "Rae Parnmukh is Director of IP Product Operations at Tenstorrent, where she focuses on enabling high-performance compute through RISC-V and AI IP and close hardware\u2013software co-development.", "public_name": "Rae Parnmukh", "guid": "ee365d86-cedd-5df3-975b-bbed51e1cce0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/PYBQJR/"}, {"code": "9KLNMW", "name": "Dongjie Xie", "avatar": null, "biography": null, "public_name": "Dongjie Xie", "guid": "cafe532e-18b5-5c4f-9286-325e2d8b3191", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9KLNMW/"}, {"code": "CSBUAV", "name": "Brandon Zupan", "avatar": null, "biography": null, "public_name": "Brandon Zupan", "guid": "e47e9b5b-50f3-58b1-81e7-51075d84a9c4", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CSBUAV/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GLCJSG/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GLCJSG/", "attachments": [{"title": "Non-Blind Short technical report", "url": "/media/eu-summit-2026/submissions/GLCJSG/resources/CfP_Non-Blind-RISCV-_UFbE4TC.pdf", "type": "related"}]}, {"guid": "f12d6a8c-e1b5-5396-b2bf-9d9723f5e087", "code": "DHQPQB", "id": 330, "logo": null, "date": "2026-06-10T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-330-from-open-architecture-to-open-silicon-taping-out-core-et-many-core-risc-v-platform", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DHQPQB/", "title": "From Open Architecture to Open Silicon: Taping out CORE-ET Many-Core RISC-V Platform", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "We are going to talk about a fully open tapeout - from first schematics published for community review to sending the design to the Fab over the course of 6 months. Leveraging ET-platform and ecosystem around it, open source tools and now open CORE-ET silicon platform (part of OpenHW group), we present many-core RISC-V-based design with MRAM, creating a basis for the next generation open designs. \r\nThis talk presents an increasingly open development model, highlighting both the progress already made and the practical gaps that remain in today\u2019s silicon ecosystem.", "description": "The talk is going to cover the building blocks that made it possible, the tooling and processes that are used to support open development and testing, the software that is being brought from a larger ET-SOC-1 design to a smaller unit of compute. Rather than presenting a fully open flow as a solved problem, this talk offers a practical account of how far open silicon development can be pushed today, what still depends on closed tooling, and what this means for the next generation of open RISC-V designs.", "recording_license": "", "do_not_record": false, "persons": [{"code": "WHGEWC", "name": "Tanya Dadasheva", "avatar": null, "biography": "Tanya is a co-founder of Ainekko: a 100% open-source company on a mission to democratize inference and fine-tuning of all popular open-weight models with a hardware/software product. \r\nTanya also has started AIFoundry open source ecosystem of AI projects and engineers working on different building blocks of these stacks while maintaining the common goals and compatibility.\r\n\r\nBefore that Tanya has been involved in the tech world and open source in many different roles. She is an ex-VC @Almaz Capital with OSS and RISC-V portfolio, ex-OSS policy maker, working to integrate developing countries into the global scene while building local independent infrastructure, founder of project helping tech companies affected by the wars to leverage OSS for freedom of tech from politics.", "public_name": "Tanya Dadasheva", "guid": "64ab77eb-fc1d-5bb3-be7d-601fd164c6ed", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WHGEWC/"}, {"code": "3XBEGS", "name": "Roman Shaposhnik", "avatar": null, "biography": "Roman is a co-founder of Ainekko: a 100% open-source company on a mission to democratize how \u201cthe machine learning community collaborates on models, datasets, and applications\u201d and helping \u201cthe AI community building the future\u201d. He is a serial entrepreneur, technologist and a co-founder and former CTO of ZEDEDA Inc. who is also deeply involved in the world of Open Source as both VP of Legal Affairs at the ASF and a former VP of Technology at The LF.", "public_name": "Roman Shaposhnik", "guid": "69bb3308-ed6d-564c-8cc9-76325bab5526", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3XBEGS/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DHQPQB/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DHQPQB/", "attachments": []}, {"guid": "a4257861-6f93-572a-bf27-a5a12fa27de5", "code": "XXQJQF", "id": 47, "logo": null, "date": "2026-06-10T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-47-the-isolde-space-demonstrator-a-risc-v-ecosystem-for-low-power-on-board-inference", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XXQJQF/", "title": "The ISOLDE Space Demonstrator: a RISC-V Ecosystem for Low-Power On-board Inference", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Integrating AI-based capabilities into satellites improves spacecraft autonomy, but poses considerable obstacles in designing the hardware and software ecosystem. \r\nThe orbit-dependent generation of power with solar cells, the limited thermal dissipation and weight present significant challenges in designing a compute platform capable of edge inference, forcing the trade-off between high-performance for complex AI models and strict power/area budget. \r\nMoreover, AI models must share the same resources of traditional algorithm that are executed onboard concurrently with the inference, such as avionics, attitude orbit control, data handling and signal processing. \r\nHowever, benefits of onboard processing comprise secure and private computation, decreased data uplink/downlink demands, autonomous detection and resolution of anomalies, enabling autonomous spacecraft operation.\r\nTherefore, it is necessary to adapt a hardware-aware codesign approach in designing software components to implement energy-efficient and secure edge inference without decreasing the performance of traditional applications. \r\nThe ISOLDE space demonstrator comprises several RISC-V cores and accelerators, and its hardware architecture and software ecosystem are presented, with a particular focus on the interactions of several open-source and open-hardware IPs developed by various academic and industry European partners.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BW8LHD", "name": "Emanuele Valpreda", "avatar": null, "biography": "", "public_name": "Emanuele Valpreda", "guid": "797a52db-e918-5e43-acbd-3687dbcc1dae", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BW8LHD/"}, {"code": "TEH3RE", "name": "Davide Di Ienno", "avatar": null, "biography": null, "public_name": "Davide Di Ienno", "guid": "62e436bf-9ba4-52ad-83f5-ecdaa240a3dc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TEH3RE/"}, {"code": "DK9AZC", "name": "Mattia Paladino", "avatar": "https://cfp.riscv-europe.org/media/avatars/DK9AZC_cDkJOfS.webp", "biography": "Mattia Paladino is a Project Manager at E4 Computer Engineering. He is currently involved in several European projects within the HPC sector, focusing on areas such as co-design for optimizing ML applications, green computing, and RISC-V. He holds a master's degree in Nuclear and Subnuclear Physics from the University of Bologna.", "public_name": "Mattia Paladino", "guid": "cf56c56b-bfa6-54c5-a6f1-4d5b64336204", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DK9AZC/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XXQJQF/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XXQJQF/", "attachments": []}, {"guid": "18d45e56-0ed7-51a2-bdb4-ae2498d56bda", "code": "G7YQKR", "id": 248, "logo": null, "date": "2026-06-10T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-248-integration-challenges-in-risc-v-system-prototyping-the-riser-microserver-platform", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YQKR/", "title": "Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "This extended abstract reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V cloud server and accelerator prototypes capable of running fully-featured Linux-based software stacks. Building on processor IP from the EPI and EUPILOT projects, RISER targets Europe's open strategic autonomy in cloud infrastructure. We present the RISER Microserver Platform, an FPGA-assisted prototype that integrates the EPAC1.5 RISC-V vector-processor test-chip in a standalone computing node with its own boot firmware, NVMe storage, and 100 Gbps Ethernet connectivity, and discuss the integration challenges encountered during bring-up", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "VGSXRF", "name": "Manolis Marazakis", "avatar": "https://cfp.riscv-europe.org/media/avatars/VGSXRF_qsyedmE.webp", "biography": "Dr. Manolis Marazakis (Ph.D. in Computer Science, University of Crete, Greece - 2000) is a Principal Staff Research Scientist at the Institute of Computer science, FORTH. His research interests are in architectures and efficient systems software, mainly resource management and storage I/O middleware, for high-performance servers in data center environments. He has contributed to the design, implementation and performance analysis of several system prototypes for HPC, data analytics, multi-tenant workloads, and the convergence of HPC and Cloud infrastructures. He has been FORTH\u2019s technical lead for system software and performance evaluation for European digital sovereignty-focused research and innovation projects, for both HPC and Cloud infrastructure technologies. He is a Senior Member of ACM (since 2018) and IEEE (since 2021), and a Member of the USENIX Technical Society.", "public_name": "Manolis Marazakis", "guid": "12fd464b-ccbd-5533-a1a8-ffbda8581eda", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VGSXRF/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YQKR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YQKR/", "attachments": []}, {"guid": "11986ef7-1fe8-5836-aba5-f09a94ecb5cb", "code": "XSLFRB", "id": 310, "logo": null, "date": "2026-06-10T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-310-monte-cimone-v3-where-risc-v-stands-in-high-performance-computing", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XSLFRB/", "title": "Monte Cimone v3: Where RISC-V Stands in High-Performance Computing", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The Monte Cimone project provides a RISC-V testbed for High-Performacne Computing cluster. This paper presents Monte Cimone v3 (MCv3), the third iteration of the Monte Cimone RISC-V HPC cluster, integrating the SOPHGO Sophon SG2044 processor, an evolution of the SG2042 used in MCv2. We characterize MCv3 using HPL and STREAM benchmarks coupled with power measurements, and compare it against two reference platforms: the Intel Xeon Platinum 8480+ (Sapphire Rapids) and the NVIDIA Grace CPU Superchip. Our results show that the SG2044 more than doubles single-core performance and improves scalability compared to SG2042. MCv3 achieves an energy efficiency of 3.08GFLOPs/W which improves of 10x w.r.t. MCv1 and is in the range of x86-64 and Arm servers. On pure performance when normalized on the SIMD/Vector length MCv3 on its peak efficiency point (16 cores) achieves 46% performance of Intel Sapphire Rapids server and 91% performance of NVIDIA Grace CPU superchip.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HKYAWD", "name": "Emanuele Venieri", "avatar": null, "biography": "", "public_name": "Emanuele Venieri", "guid": "cd561a43-be92-50bf-a13c-f21b6ad66576", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HKYAWD/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XSLFRB/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XSLFRB/", "attachments": []}, {"guid": "2c25eef0-4729-5f16-9c7e-9d6da5d39357", "code": "VVJ8FY", "id": 113, "logo": null, "date": "2026-06-10T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-113-vitamin-v-results-and-lessons-learnt", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VVJ8FY/", "title": "Vitamin-V: Results and Lessons Learnt", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Vitamin\u2011V (2023\u20132025) is a Horizon Europe project building a production\u2011grade, open\u2011source RISC\u2011V ecosystem for cloud environments. It extends RISC-V ISA support in three execution platforms (QEMU, gem5, FPGA), enables virtualization and contributes to the development of full cloud\u2011native stacks\u2014OpenStack, Kubernetes, Kata Containers, RustVMM. The project also boosts commercial developments from Semidynamics, ZeroPoint, and Virtual Open Systems. This paper summarizes the technical outcomes and lessons learned.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "VGW7EE", "name": "Ramon Canal", "avatar": "https://cfp.riscv-europe.org/media/avatars/VGW7EE_bUVXnW8.webp", "biography": "Ramon Canal (PhD ,2004) is a Professor at the Universitat Polit\u00e8cnica de Catalunya (UPC), in Barcelona, Catalonia, EU. He worked at Sun Microsystems in 2000, and he was a Fulbright visiting scholar at Harvard University in 2006/2007 and a visiting professor at the University of Cyprus in 2019/2020. His research focuses on power and thermal aware architectures, as well as reliability and security. He has been programme committee member in several editions of HPCA, ISCA, MICRO, DATE, HiPC, IPDPS, ICCD, ICPADS, CF. He has been co-general chair of DFTS 2025, HPCA 2016 and IOLTS 2012. He has been track co-chair for DATE 2019 and 2020. He is currently an associate editor of the IEEE Transactions on Computers, ACM Transactions on Architecture and Code Optimization (TACO) and the Journal of Parallel and Distributed Computing (JPDC). He is a member of the IEEE.", "public_name": "Ramon Canal", "guid": "d61e288f-dbbc-5aae-9b9b-113cfc520f88", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/VGW7EE/"}], "links": [{"title": "Vitamin-V Github repository", "url": "https://github.com/vitamin-v-software", "type": "related"}, {"title": "Vitamin-V website", "url": "https://www.vitamin-v.eu", "type": "related"}], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VVJ8FY/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VVJ8FY/", "attachments": []}, {"guid": "6320127f-59a4-511f-b446-1223a3eacc8d", "code": "3XNCRH", "id": 364, "logo": null, "date": "2026-06-10T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-364-conflict-to-compliance-risc-v-extension-migration-across-spec-hw-and-sw", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3XNCRH/", "title": "Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified Database (UDB) as the source of truth for extension definition and a Large Language Model (LLM) connected through Model Context Protocol (MCP) tools to accelerate migration into compliant custom opcode space. In Phase 1, the agent inspects instruction encodings, identifies conflicts against ratified and reserved space, and proposes remappings for human approval. In Phase 2, it generates hardware and software artifacts from the approved mapping and validates them through automated build-and-test loops. To evaluate the flow, we are open-sourcing two packed-SIMD extensions and the supporting hardware and software, including a full-system simulator, GNU assembler support, Zephyr runtime support and even the RTL design for the more than 140 migrated instructions. The result is a working open-source end-to-end stack, from decoder to application code, demonstrating AI assistance as a practical aid for ISA architects and as an automation layer for the associated hardware and software engineering.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "JNNEDZ", "name": "Afonso Oliveira", "avatar": null, "biography": "", "public_name": "Afonso Oliveira", "guid": "08d99180-28e8-5b97-9bca-8a341efe4059", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JNNEDZ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3XNCRH/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3XNCRH/", "attachments": []}, {"guid": "7c7a645f-20ee-5037-a54c-b39a34243cac", "code": "SED3UJ", "id": 145, "logo": null, "date": "2026-06-10T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-145-risc-v-silicon-at-scale-in-academia-designing-big-open-source-chips-on-pulp-platform", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SED3UJ/", "title": "RISC-V Silicon at Scale in Academia: Designing \u201cBig\u201d Open-Source Chips on PULP Platform", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The PULP Platform team at ETH Z\u00fcrich and the University of Bologna has delivered several \u201cbig\u201d chips based on RISC-V cores that exceed the complexity of chips traditionally designed in academic/research settings. These designs are made possible through open-source principles that allow greater collaboration and innovation in critical parts of the design. RISC-V has been instrumental in the development of these designs, allowing the team to develop a sandbox of building blocks for creating designs that exceed one billion transistors.", "description": "This extended abstract presents large-scale RISC-V silicon developed in academia using the PULP Platform at ETH Z\u00fcrich and the University of Bologna. Over a decade, the platform has produced more than 70 ASICs, including several \u201cbig\u201d chips exceeding one billion transistors across 22\u20137 nm technologies. We discuss four key enablers: open-source design reuse, forming capable design teams, access to funding and advanced technologies/IP, and assembly and packaging for prototype quantities, enabling complex academic silicon tapeouts.", "recording_license": "", "do_not_record": false, "persons": [{"code": "7ZEJZN", "name": "Yichao Zhang", "avatar": "https://cfp.riscv-europe.org/media/avatars/7ZEJZN_gNK8X95.webp", "biography": "Yichao Zhang received his M.Sc. degree from Nanyang Technological University, Singapore, in 2017. He served as a Physical Design Engineer at MediaTek and as the Lead Application Engineer at Cadence Design Systems in Singapore until 2021.\r\nIn 2021, he joined the Integrated Systems Laboratory at ETH Zurich to pursue a Ph.D. under the supervision of Prof. Dr. Luca Benini. As a developer of the Parallel Ultra-Low Power (PULP) platform, his research focuses on physically feasible, ultra-large-scale many-core shared-memory architectures with both scalar and vector processing, leveraging scalable, high-bandwidth, low-latency Network-on-Chip. On the application side, he focuses on software-defined B5G/6G Open Radio Access Networks for programmable baseband Physical Uplink Shared Channel processing.", "public_name": "Yichao Zhang", "guid": "a7484d63-c1c6-5135-b72a-4101062d973c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7ZEJZN/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SED3UJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SED3UJ/", "attachments": []}, {"guid": "b5666658-f5ee-5373-bf6a-19c281064b36", "code": "PRU8TZ", "id": 225, "logo": null, "date": "2026-06-10T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-225-piconut-risc-v-one-educational-platform-for-hardware-and-software-development", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PRU8TZ/", "title": "PicoNut/RISC-V: One Educational Platform for Hardware and Software Development", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Most existing educational tools for RISC-V focus on either hardware or software development, rarely both. PicoNut is an open, synthesizable RISC-V processor and system platform designed for academic education and rapid prototyping. By using SystemC-RTL as the main hardware modeling language, modules can be arbitrarily replaced by C/C++ software implementations. This allows to build full RTL as well as software based simulators for highly efficient and cycle-accurate simulations of complete systems. Even emulations of external hardware are possible, for example, by implementing screen hardware with a Qt-based GUI. To any system simulator, GDB can be attached for software debugging.\r\n\r\nTo demonstrate the platforms capabilities, students implemented a retro game console featuring custom peripherals and several ports of classic games. Through hands-on engagement with real hardware and software challenges, PicoNut empowers students to develop a comprehensive understanding of digital design, computer architecture, hardware-software codesign, and embedded systems development.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "MDUKU3", "name": "Johannes Hofmann", "avatar": null, "biography": "Johannes Hofmann is a graduate student pursuing a Master of Science (MSc) in Applied Research in Engineering Sciences at the Technical University of Applied Sciences Augsburg. His research interests include embedded systems and debugging methodologies, RISC-V hardware development, and embedded AI.", "public_name": "Johannes Hofmann", "guid": "5fbdad65-9653-546b-9538-c5558bbd2be4", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MDUKU3/"}, {"code": "WLABY3", "name": "Gundolf Kiefer", "avatar": null, "biography": "", "public_name": "Gundolf Kiefer", "guid": "658a99c8-0ed4-5c45-955f-19178be02349", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WLABY3/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PRU8TZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PRU8TZ/", "attachments": []}, {"guid": "dc2a6171-c612-5493-907b-f05cba5bbab2", "code": "G8FEKT", "id": 175, "logo": null, "date": "2026-06-10T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-175-flying-v-a-radiation-hardened-l1-data-cache-for-risc-v-aerospace-processors", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G8FEKT/", "title": "Flying V: A Radiation-Hardened L1 Data Cache for RISC-V Aerospace Processors", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Radiation-induced bit-flips in on-chip memories threaten the reliability of processor-based systems, particularly in aerospace applications. This work introduces ECC-based hardening for the HPDcache, an open-source L1 data cache compatible with RISC-V cores (e.g., CVA6). The design enables Single Error Correction and Double Error Detection (SECDED), thereby protecting SRAMs from transient faults. A scrubber further mitigates multi-bit errors by periodically refreshing cachelines. Implementation of an 8 KiB cache configuration in 45 nm technology shows a 2.1% core area overhead and an 8% clock frequency reduction. This is a first step towards a fully open-source RISC-V core with both safety features and a high-performance memory subsystem to address the increasing computing demand in aerospace applications.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "UZ7BT9", "name": "C\u00e9sar Fuguet", "avatar": "https://cfp.riscv-europe.org/media/avatars/UZ7BT9_OlxGhqE.webp", "biography": "He is a researcher at Inria in the TIMA laboratory of the University Grenoble Alpes since November 2024, after spending 9 years at CEA. He\u2019s got his computer sciences and electronics PhD from Universit\u00e9 Paris 6 in 2015. He works on multi-core heterogeneous architectures, cache hierarchy and cache coherence.", "public_name": "C\u00e9sar Fuguet", "guid": "b9656eaa-1f41-53b6-83bc-f68ea9a8eecb", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UZ7BT9/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G8FEKT/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G8FEKT/", "attachments": []}, {"guid": "06c339b0-0b49-5ca7-9bbb-e2fba1696c3b", "code": "TYLEYW", "id": 38, "logo": null, "date": "2026-06-10T14:20:00+02:00", "start": "14:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-38-fault-tolerant-open-source-cva6-core-for-automotive-aeronautics-and-space", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TYLEYW/", "title": "Fault-Tolerant Open-Source CVA6 Core for Automotive, Aeronautics and Space", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper presents a radiation-hardened, open-source RISC-V CVA6 core designed for space, aeronautics, and automotive applications, where Single Event Upsets (SEUs) threaten reliability or safety. The design integrates error detection and recovery in L1 caches and Dual-Core Lockstep (DCLS) with temporal diversity. For non-critical workloads, the system supports Asymmetric Multiprocessing (AMP), enabling independent core operation. Tested with Linux and Zephyr, this work is inspired by RISC-V International\u2019s Functional Safety white paper and advances open-source, fault-tolerant computing for critical systems. It is being integrated in a new 18 nm SoC for AI.", "description": "Co-authors:\r\nThales / cortAIx Labs, Palaiseau, France: J\u00e9r\u00f4me Qu\u00e9vremont, Daniel Gracia P\u00e9rez, Abdou Lahat Ndiaye, Julien Mallet\r\nSTMicroelectronics, Agrate Brianza, Italy: Paolo Zambotti, Francesco Diodati, Stefano Bosisio", "recording_license": "", "do_not_record": false, "persons": [{"code": "KPLURG", "name": "J\u00e9r\u00f4me Qu\u00e9vremont", "avatar": "https://cfp.riscv-europe.org/media/avatars/KPLURG_r7tw1qP.webp", "biography": "J\u00e9r\u00f4me Qu\u00e9vremont graduated in telecommunications and electronics in 1995 (T\u00e9l\u00e9com Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology cortAIx Labs as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security.", "public_name": "J\u00e9r\u00f4me Qu\u00e9vremont", "guid": "979f0318-1d60-5904-b2dd-9e5d334061e8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KPLURG/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TYLEYW/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TYLEYW/", "attachments": [{"title": "Final extended abstract", "url": "/media/eu-summit-2026/submissions/TYLEYW/resources/RVSummitEU26-CVA6-sa_hbZ2TFe.pdf", "type": "related"}, {"title": "Poster", "url": "/media/eu-summit-2026/submissions/TYLEYW/resources/Poster_CVA6-Safe_v1__cNtCyUf.pdf", "type": "related"}]}, {"guid": "723a863a-6169-5e0c-a377-1829637229ed", "code": "RCLLZH", "id": 348, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/RCLLZH/CORDIC_mpFYA7t_Qmdq3zO_PXIqcg_P4y5UrW.webp", "date": "2026-06-10T15:30:00+02:00", "start": "15:30", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-348-toxos-a-risc-v-coprocessor-for-non-linear-function-acceleration", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RCLLZH/", "title": "TOXOS: A RISC-V Coprocessor for Non Linear Function Acceleration", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The growing demand for near-sensor processing exposes a gap: nonlinear activation functions still fall back on the host CPU, incurring energy and latency penalties. We present TOXOS, a RISC-V CORDIC coprocessor tightly integrated into X-HEEP via the Core-V eXtension Interface, achieving up to 27\u00d7 speedup over a hardware FPU (CVFPU) with minimal area overhead.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HXRE8T", "name": "Luigi Giuffrida", "avatar": null, "biography": "", "public_name": "Luigi Giuffrida", "guid": "e3bb8f25-534f-5aa4-9e6d-5fa4a76481c9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HXRE8T/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RCLLZH/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RCLLZH/", "attachments": []}, {"guid": "4b96376d-53fd-5812-8675-411c412ea808", "code": "HMZYAS", "id": 282, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/HMZYAS/vishwa_H20e7dR_xAorqsn_mxJnic_OBMFAuS.webp", "date": "2026-06-10T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-282-vishwa-a-scalable-risc-v-based-gpgpu", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HMZYAS/", "title": "Vishwa: A Scalable RISC-V Based GPGPU", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The growing demand for artificial intelligence, scientific computing, and large-scale data analytics has significantly increased the need for massively parallel computing architectures. Modern GPUs provide high computational throughput by executing thousands of concurrent threads, but most existing GPU architectures remain proprietary, limiting open architectural innovation and research. This paper presents Vishwa, a scalable RISC-V based General Purpose GPU (GPGPU) architecture designed to enable open and extensible parallel computing platforms. The architecture adopts a hierarchical compute model composed of Vishwa Compute Clusters (VCLs) containing multiple Vishwa Compute Cores (VCCs) that execute threads using a Single Instruction Multiple Thread (SIMT) execution model. Each compute core integrates specialised Vishwa Matrix Cores (VMCs) designed to accelerate matrix-intensive operations commonly used in machine learning workloads. Work distribution across the architecture is managed by a global Vishwa Work Distributor (VWD) that schedules workloads across available compute clusters. The architecture is supported by a complete software ecosystem through the CHAKRA compiler stack, which integrates with LLVM to provide kernel compilation and runtime execution support. The compute core architecture has been implemented and validated on an FPGA platform, demonstrating functional correctness of the execution pipeline and SIMT execution model.", "description": "The Vishwa architecture follows a hierarchical GPU design composed of a host interface, a global Vishwa Work Distributor (VWD), multiple Vishwa Compute Clusters (VCLs), and a hierarchical memory subsystem connected to high-bandwidth memory. Kernels launched by the host processor are distributed across compute clusters through the VWD, which dynamically assigns workloads to available clusters to maximise parallel utilisation. Each Vishwa Compute Cluster integrates multiple Vishwa Compute Cores (VCCs) along with shared resources such as register files, shared memory, scheduling hardware, and instruction and data caches. This organisation enables the architecture to support a large number of concurrent threads while effectively hiding memory latency through hardware multithreading.\r\n\r\nThe architecture consists of multiple Vishwa Compute Clusters interconnected through a shared cache hierarchy and supported by High Bandwidth Memory (HBM) to provide high-throughput data access. Each VCL integrates four Vishwa Compute Cores, forming a scalable compute unit capable of parallel execution. Every VCC can execute 32 threads in parallel, enabling fine-grained data parallelism across workloads. In addition, each VCC supports up to 16 pipelined thread groups, allowing overlapping execution and improving utilisation of the compute pipeline.", "recording_license": "", "do_not_record": false, "persons": [{"code": "UUME9J", "name": "PRANOSE J EDAVOOR", "avatar": null, "biography": "", "public_name": "PRANOSE J EDAVOOR", "guid": "227f9418-57df-5186-8a60-c880cbf5b781", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UUME9J/"}, {"code": "AMGGLL", "name": "Prachi Pandey", "avatar": "https://cfp.riscv-europe.org/media/avatars/AMGGLL_4hHMX1G.webp", "biography": "Ms. Prachi Pandey is a Senior Compiler Engineer at C-DAC, where she works on MLIR/LLVM-based compiler development for indigenous processors, GPUs, and AI accelerators. She has nearly two decades of experience in HPC, parallel programming, compilers, and runtime systems. Her research interests include compiler optimization techniques, automatic parallelizing compilers, performance portability for heterogeneous architectures, and parallelization strategies for HPC and AI workloads.", "public_name": "Prachi Pandey", "guid": "784470bb-6909-5518-8d6e-2183cb128a6d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AMGGLL/"}, {"code": "PMXKMP", "name": "Vivian", "avatar": null, "biography": "Scientist at Centre for Development of Advanced Computing (C-DAC), Bangalore, India", "public_name": "Vivian", "guid": "658cd7fa-ab41-57cc-8d28-8257ac882ee6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/PMXKMP/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HMZYAS/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HMZYAS/", "attachments": []}, {"guid": "6e15b964-6c8d-53f7-9180-4709482c7411", "code": "RRK9ZJ", "id": 294, "logo": null, "date": "2026-06-10T15:50:00+02:00", "start": "15:50", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-294-cincoranch-a-heterogeneous-multi-microarchitecture-risc-v-test-chip-silicon-bring-up", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RRK9ZJ/", "title": "Cincoranch: A Heterogeneous Multi-Microarchitecture RISC-V Test Chip \u2013 Silicon Bring-Up", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The Cincoranch Test Chip 1 (TC1), manufactured in Intel3 technology, integrates three RISC-V processors\r\nwith a Vector Processing Unit (VPU) accelerator and an HPC-oriented cache hierarchy. This work presents the\r\nelectrical characterization of the silicon, the power-on bring-up procedure, and basic functionality verification\r\nof the TC1 chips. Initial measurements focused on power consumption and temperature of each core under idle\r\nconditions, providing insight into the chip\u2019s behavior and readiness for further workload testing.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "KMKCFH", "name": "Hugo Safadi", "avatar": "https://cfp.riscv-europe.org/media/avatars/KMKCFH_6e5KQfy.webp", "biography": "", "public_name": "Hugo Safadi", "guid": "55f3a8e4-f7ec-5ed3-9aef-08f955993cdd", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KMKCFH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RRK9ZJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RRK9ZJ/", "attachments": []}, {"guid": "a26bbb96-505f-5472-9661-422948c46670", "code": "DSMVHN", "id": 335, "logo": null, "date": "2026-06-10T16:00:00+02:00", "start": "16:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-335-cva6-rt-an-open-source-time-predictable-rv64-processor-for-mixed-criticality-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DSMVHN/", "title": "CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implements the rv64gch ISA and features advanced support for real-time execution, including TLB partitioning and locking for predictable address translation, a dynamically reconfigurable scratchpad mode in the L1 caches for deterministic memory access, and low-latency interrupt handling via an enhanced interrupt controller combined with hardware-assisted context stacking. With real-time features enabled, CVA6-RT achieves an interrupt latency of 12 cycles, comparable to that of simpler Arm Cortex-M microcontrollers, and 10x lower than the baseline CVA6 core.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BUQTFJ", "name": "Enrico Zelioli", "avatar": null, "biography": "", "public_name": "Enrico Zelioli", "guid": "aa6588df-1546-5abe-91d5-aafdab115877", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BUQTFJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DSMVHN/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/DSMVHN/", "attachments": []}, {"guid": "12d119fc-a7e2-58e1-9393-67cac6692ddf", "code": "WDXS8R", "id": 353, "logo": null, "date": "2026-06-10T16:10:00+02:00", "start": "16:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-353-toward-an-open-source-platform-for-multi-lead-embedded-ecg-processing-on-risc-v-processors", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WDXS8R/", "title": "Toward an open-source platform for multi-lead Embedded ECG Processing on RISC-V processors", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Interest in edge inference for biomedical applications has boomed in recent years, given its benefits in terms of data privacy, low latency, and reduced cloud costs. We present Embedded ECG Processing on RISC-V(EEP-V), an end-to-end platform for multi-lead embedded ECG processing on RISC-V processors. EEP-V combines a custom multi-lead acquisition board, real-time digital signal conditioning, and on-device neural network inference in a fully local processing pipeline without cloud offloading. The platform is designed as an open-source hardware/software stack to support reproducible research on embedded cardiac monitoring. Our implementation targets a heterogeneous RISC-V architecture based on GAP9 and supports concurrent processing of up to 12 ECG leads. We validate the complete acquisition-to-inference pipeline using a medical-grade patient simulator and a reference multi-class arrhythmia classification model from PhysioNet/CinC Challenge 2021. On the deployed system, inference completes in 150 ms using 488 kB of L2 memory and consumes less than 5.47 mJ per classification, while the full pipeline consumes about 7 mJ per inference cycle. These results show the feasibility of an end-to-end multi-lead ECG processing platform on RISC-V and provide an open foundation for future embedded cardiac-monitoring research.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "SCLP78", "name": "Da Rocha Carvalho Bruno", "avatar": null, "biography": "Embedded systems engineer specializing in embedded AI deployment and optimization. My work focuses on adapting machine learning models to resource-constrained hardware and improving performance through efficient compilation and system-level optimization", "public_name": "Da Rocha Carvalho Bruno", "guid": "052c5d30-092f-53a1-921e-69679de21353", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SCLP78/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WDXS8R/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WDXS8R/", "attachments": []}], "Poster Island D": [{"guid": "f54f1d45-6692-5500-8d5d-de2cc11507d3", "code": "SFGFJE", "id": 154, "logo": null, "date": "2026-06-10T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-154-who-checks-the-checker-end-to-end-architectural-seu-tolerance-for-risc-v-microcontroller-protection", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SFGFJE/", "title": "Who Checks the Checker? End-to-End Architectural SEU Tolerance for RISC-V Microcontroller Protection", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "RISC-V-based microcontroller units (MCUs) are increasingly adopted in radiation-heavy environments such as space, where single-event upsets (SEUs) can cause bit-flips in sequential and combinational logic. RISC-V-based designs are ideally suited for these domains, as open architectures allow for fault-tolerance modifications, enhancing readiness for architectures and systems-on-chip (SoCs). While component-level architectural protection methods, such as error correction codes (ECC) and triple modular redundancy (TMR), can individually harden each component, they leave critical gaps: the voters, encoders, and decoders that implement these protections themselves remain unprotected and become single points of failure.\r\nWe propose an overlapping protection approach that addresses this fundamental \u201cwho checks the checker?\u201d problem. By extending each protection domain to encompass the checking logic of adjacent domains, we achieve end-to-end fault tolerance across an entire RISC-V MCU without requiring radiation-hardened standard cells. We build on croc, an open-source, extensible RISC-V MCU platform based on the CVE2 core, incrementally applying ECC-protected SRAM, triple-core lockstep cores, a reliable OBI interconnect, and TMR peripherals.\r\nFault injection campaigns in both RTL and synthesized netlist show that the fully protected RISC-V MCU achieves over 99.9% fault coverage at 2.71\u00d7 area overhead, 22% less than fine-grained triplication. Critically, without overlapping protection, 16.33% of faults in voter signals cause failures; with overlapping, this drops to 0.26%. All designs are implemented using the fully open-source IHP 130nm technology, Yosys, and OpenROAD.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "LF9LT9", "name": "Michael Rogenmoser", "avatar": null, "biography": "Michael Rogenmoser received his BSc and MSc degrees from ETH Zurich in 2020 and 2021, respectively. In 2021, he joined the Integrated Systems Laboratory of ETH Zurich as a PhD candidate under the supervision of Prof. Dr. Luca Benini. His research interests include fault-tolerant architectures for space, multicore processors, and reliability in systems-on-chip (SoCs).", "public_name": "Michael Rogenmoser", "guid": "b7ee535a-44af-5e40-a88a-2f6d6623c107", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/LF9LT9/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SFGFJE/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SFGFJE/", "attachments": []}, {"guid": "ac3adf9e-fd98-5f83-9ffd-886948e7e9a4", "code": "EZCAXM", "id": 308, "logo": null, "date": "2026-06-10T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-308-a-lightweight-multi-context-architecture-for-mixed-criticality-systems-on-risc-v-processors", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EZCAXM/", "title": "A Lightweight Multi-Context Architecture for Mixed-Criticality Systems on RISC-V Processors", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Mixed-criticality systems incorporating software components with different criticality levels demand strong isolation mechanisms to guarantee dependability. High-end and mid-end architectures accomplish this through rigorous temporal and spatial partitioning, backed by multiple privilege levels and memory management units. Nevertheless, low-end processors, constrained to two privilege levels, encounter difficulties in realizing effective temporal and spatial partitioning without undermining system composability. This paper presents a novel multi-context framework for low-end RISC-V processors, exploiting a lightweight hardware extension and enabling efficient temporal and spatial partitioning. The proposed approach not only guarantees robust isolation and system composability but also offers flexibility to trade off hardware and software overhead, pushing forward the state of the art in dependability for resource-constrained embedded systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EW9KEB", "name": "Giacomo Valente", "avatar": "https://cfp.riscv-europe.org/media/avatars/EW9KEB_Qln3ZYm.webp", "biography": "Giacomo Valente received the M.S. degree in Electronic Engineering in 2014 and the Ph.D. degree in Information and Communication Technology in 2018 from the University of L'Aquila.\r\nHis primary research activities are in electronic design automation, reconfigurable computer architectures, and real-time systems.\r\nSince 2022, he has been an Assistant Professor in Computer Architecture at the Department of Information Engineering, Computer Science, and Mathematics of the University of L\u2019Aquila.\r\nHe is the author or co-author of more than 40 research articles in peer-reviewed journals and international conference proceedings. He has been also a reviewer and member of several TPCs related to his research topics", "public_name": "Giacomo Valente", "guid": "8e028f98-dbca-59f1-87e8-a4c421aa32f1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EW9KEB/"}, {"code": "JPHDWC", "name": "Leonardo Fazzini", "avatar": null, "biography": null, "public_name": "Leonardo Fazzini", "guid": "0abc3e3c-5018-5551-9cac-65063658e549", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JPHDWC/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EZCAXM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EZCAXM/", "attachments": []}, {"guid": "dafa2092-eab4-5c31-99fe-369a68cb27a5", "code": "YXSRKX", "id": 137, "logo": null, "date": "2026-06-10T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-137-cva6-optimization", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YXSRKX/", "title": "CVA6 Optimization", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "CVA6 is an open-source RISC-V core with highly configurable parameters for tailoring the core to various\r\napplications. An optimization-oriented analysis of the current implementation showed that the scoreboard (SB) and controller are the biggest combinational modules involved in the critical path. The SB is in charge of many crucial functions, including issuing, forwarding, writeback, and committing, while the controller manages all the stages of the core. This work presents two optimization proposals:  re-order buffer (ROB) and Issue logic separation from the Scoreboard and registering Controller output. Preliminary results show promising outcomes in implementing the core, relaxing the timing, which in turn enables operating at a higher frequency. With this optimization, we get to improve the maximum frequency of operation by 14% for the existing FPGA configuration from OpenHW for Xilinx FPGA.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "AXH7HH", "name": "Udaya Subedi", "avatar": null, "biography": "A working student at PlanV, currently pursuing a Master's in Embedded Computing Systems at RPTUKaiserslautern, Germany.", "public_name": "Udaya Subedi", "guid": "3c262010-f114-569a-88a3-0e9aa09311bd", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AXH7HH/"}, {"code": "HSBXVW", "name": "Angela Gonzalez", "avatar": null, "biography": null, "public_name": "Angela Gonzalez", "guid": "543a6a93-45a4-578f-bd1a-690e4323db67", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HSBXVW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YXSRKX/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YXSRKX/", "attachments": [{"title": "Poster", "url": "/media/eu-summit-2026/submissions/YXSRKX/resources/CVA6_Optimization_Po_N8KsC5y.pdf", "type": "related"}, {"title": "Abstract Paper Final", "url": "/media/eu-summit-2026/submissions/YXSRKX/resources/CVA6_Optimization_l48V6rJ.pdf", "type": "related"}]}, {"guid": "bb18974c-a268-569f-bb47-613fa724f19e", "code": "3TQ3K9", "id": 260, "logo": null, "date": "2026-06-10T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-260-maximizing-performance-at-low-area-cost-in-risc-v-processors-leveraging-fine-grained-multithreading", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3TQ3K9/", "title": "Maximizing Performance at Low Area Cost in RISC-V Processors Leveraging Fine-Grained Multithreading", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Embedded applications increasingly rely on highly efficient, low-area RISC-V processors. However, short 3-stage pipelines often suffer from data and control hazards that degrade performance by introducing frequent stalls. This paper presents the implementation of Fine-Grained Multithreading (FGMT) on [OMITTED FOR BLIND REVIEW], an industrial 32-bit RISC-V core supporting the RV32ECM instruction set. By interleaving two hardware threads, the design effectively hides pipeline stalls and simplifies branch target calculation without requiring complex branch prediction. To further mitigate structural hazards and the underutilization caused by inactive thread contexts in fixed round-robin scheduling, we introduce a novel \"Thread Forwarding\" (TF) technique which enables a form of TLP (Thread-Level Parallelism). Implemented in 40nm (C40) technology with a target frequency of 300MHz, the standard FGMT achieves a 14\\% IPC improvement over the baseline at the cost of a 9\\% area overhead within an MCU SoC featuring 16 KBytes of instruction and data memory. The TF architecture achieves a Pareto optimal configuration, further boosting IPC to 0.958 (+18.8\\% over baseline) while maintaining the same area footprint as the standard FGMT implementation.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "KHK9V3", "name": "Arbi", "avatar": null, "biography": "", "public_name": "Arbi", "guid": "49fe08d7-6bba-5f4d-a280-b27540009dd2", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KHK9V3/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3TQ3K9/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3TQ3K9/", "attachments": []}, {"guid": "32cb690e-9b40-59da-9303-e6bc2f8229d9", "code": "8MCLHT", "id": 143, "logo": null, "date": "2026-06-10T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-143-runtime-reconfiguration-of-decoders-in-minimal-area-risc-v-cores", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8MCLHT/", "title": "Runtime Reconfiguration of Decoders in Minimal-area RISC-V Cores", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Processor implementations designed to occupy minimal areas, such as SERV or FazyRV, are becoming increasingly popular. Some of these designs focus on flexibility and configurability while maintaining their compact design. However, due to their minimal area, implementations often involve compromises in specific components to achieve this level of efficiency. The FazyRV decoder, e.g., is highly optimized for area and therefore omits certain checks for illegal instructions. \r\nTo address these drawbacks, we propose a concept that uses partial runtime reconfiguration to dynamically replace the decoder's logic with a more robust variant to enable stricter instruction checking. These modifications introduce an area overhead of up to 39% more flip-flops than the original implementation. Dynamic partial reconfiguration can be triggered during runtime via a memory-mapped register, enabling the processor to continue normal operation seamlessly.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "L9JTZN", "name": "Tobias Scheipel", "avatar": "https://cfp.riscv-europe.org/media/avatars/L9JTZN_hhdzUyW.webp", "biography": "I'm an Assistant Professor of Reconfigurable Computer Architectures in the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology and a RISC-V Advocate. I completed my PhD under Prof. Marcel Baunach, earning the Doctor of Engineering Sciences (Dr. techn.) degree sub auspiciis Praesidentis. My research focuses on sustainable, flexible, and runtime-reconfigurable microcontroller architectures for embedded systems \u2013 especially FPGA-based RISC-V \u2013 at the hardware-software interface, including processor logic and embedded operating systems. I teach CPU architecture and implementation, embedded programming, and scientific writing. I have authored peer-reviewed publications in international journals and conference proceedings and am active in several RISC-V SIGs, Euromicro, the ACM, and the German Informatics Society (GI).", "public_name": "Tobias Scheipel", "guid": "b327ab33-41db-5eb5-a7c8-6ca9e3f05846", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/L9JTZN/"}, {"code": "7YGDYF", "name": "Lukas Glantschnig", "avatar": null, "biography": null, "public_name": "Lukas Glantschnig", "guid": "3118becc-b765-50e4-aecf-ad04e09eb133", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7YGDYF/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8MCLHT/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8MCLHT/", "attachments": [{"title": "Final Paper", "url": "/media/eu-summit-2026/submissions/8MCLHT/resources/Runtime_Reconfigurat_ZJGsEwg.pdf", "type": "related"}]}, {"guid": "0d4f7eba-3446-5780-a2ff-ae460b8fbef2", "code": "7AQXJK", "id": 257, "logo": null, "date": "2026-06-10T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-257-generator-driven-functional-safety-for-risc-v-socs-with-formal-assurance", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7AQXJK/", "title": "Generator-Driven Functional Safety for RISC-V SoCs with Formal Assurance", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Functional safety (FuSa) in modern SoC designs demands rigorous fault detection mechanisms alongside standardized error reporting. We present a fully automated, generator-driven design flow that automatically applies dual modular redundancy (DMR) through a pass implemented in CIRCT, an MLIR-based hardware compiler framework, without requiring manual RTL modification. To validate the correctness of the generated design, we apply formal verification, providing strong assurance that the DMR composition itself introduces no spurious faults. In addition, we address the system-level integration of the generated fault detection signals by routing them to a safety controller that adheres to the \"RISC-V RERI Architecture Specification\" for error reporting across the SoC, capturing each error's severity, nature, and location. We validate our generation flow through fault injection, demonstrating reliable fault detection across arbitrary hardware modules and correct propagation, recording, and reporting of detected errors in the safety controller. Combined, our contributions form an automated path from module-level fault hardening to system-level error observability, advancing the practical adoption of FuSa practices in generator-based RISC-V SoCs.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EKLD3S", "name": "Frederik Haxel", "avatar": null, "biography": "Frederik Haxel is a researcher at the FZI Research Center for Information Technology. His research interests include developing tools and methods to accelerate the design of safe and efficient RISC-V systems.", "public_name": "Frederik Haxel", "guid": "447ec056-177e-56fc-bb5c-d7d9527902d1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EKLD3S/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7AQXJK/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7AQXJK/", "attachments": []}, {"guid": "be41be51-60dd-5f19-8f1d-9d6cf64bcac8", "code": "LNTKNT", "id": 89, "logo": null, "date": "2026-06-10T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-89-heterogeneous-interrupts-for-ultra-low-latency-embedded-risc-v-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LNTKNT/", "title": "Heterogeneous Interrupts for Ultra-Low Latency Embedded RISC-V Systems", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Reactive real-time systems rely on preemption and, by extension, context switching (CS) to schedule critical tasks. Short, frequent interrupt routines may use a disproportinally large ammount of time and energy for CS rather than core application functionality. Replicated register files (RRFs) are an established solution for fast CS, but area-intensive and poorly scalable. This abstract presents the heterogeneous interrupt architecture, a solution for targeted use of RRFs that maintains area-efficiency, and the parallel context stack (PCS), a novel RRF microarchitecture. The proposed concepts are evaluated with implementations in TSMC 22-nm and a periodic task case study. The implementation in a RISC-V microcontroller system demonstrates a 1.2% area overhead with no timing detriment for the PCS, while the case study demonstrates a reduction in clock cycles and retired instructions of up to 26% and 21%, respectively.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "WTD9YU", "name": "Antti Nurmi", "avatar": null, "biography": "Antti Nurmi received the B.Sc. degree in electronics and the M.Sc. degree in embedded systems from Tampere University, Tampere, Finland, in 2019 and 2022, respectively, where he is currently working toward the Ph.D. degree in computer engineering at the SoC Hub Research Centre. His research interests include predictable computer architecture, embedded real-time systems, RISC-V, and SoC design.", "public_name": "Antti Nurmi", "guid": "7e1df896-385c-59f5-8ab3-4ffdbccbd8e0", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WTD9YU/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LNTKNT/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LNTKNT/", "attachments": [{"title": "Camera-ready manuscript", "url": "/media/eu-summit-2026/submissions/LNTKNT/resources/HETI_RVS_CR_CMP_wYj58iC.pdf", "type": "related"}, {"title": "Poster", "url": "/media/eu-summit-2026/submissions/LNTKNT/resources/heti_poster_comp_EZI8TIi.pdf", "type": "related"}]}, {"guid": "6ff0eb60-f459-521a-b67e-4e871ca812b8", "code": "FMQNTD", "id": 233, "logo": null, "date": "2026-06-10T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-233-advanced-interrupt-latency-optimization-approaches-in-risc-v-interrupt-architectures", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FMQNTD/", "title": "Advanced Interrupt Latency Optimization Approaches in RISC\u2011V Interrupt Architectures", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Modern interrupt controllers combine hardware and software mechanisms to reduce interrupt latency, optimizing either worst-case latency, average-case latency, or both. The paper provides analysis of interrupt-latency optimization techniques and their trade-offs in the context of RISC\u2011V interrupt architectures. It draws on an end-to-end workflow that began with functional modeling and continued through simulation, OS porting, and RTL implementation. This provides practical insight into how these techniques behave both in isolation and in real-world systems. The paper shows that each technique admits multiple realizations, which redistribute cost across latency metrics, software and hardware implementation complexity, memory footprint, and other factors, and that the techniques are interdependent, so the benefits of enabling them are not directly additive.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EH9ZHR", "name": "Evgenii Paltsev", "avatar": null, "biography": "", "public_name": "Evgenii Paltsev", "guid": "ec2a61a0-4931-5613-ad8c-62b5038714ac", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EH9ZHR/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FMQNTD/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FMQNTD/", "attachments": []}, {"guid": "36782212-68f4-5660-82e7-1a3c0f29ecda", "code": "LQRAW3", "id": 95, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/LQRAW3/SMSIC_6Vw5PyY_rfG3Gqg.webp", "date": "2026-06-10T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-95-smsic-software-interrupt-msi-controller-for-riscv-aia-in-large-scale-noc-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LQRAW3/", "title": "SMSIC: Software-Interrupt MSI Controller for RISCV AIA in Large-Scale NoC Systems", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Advanced Interrupt Architecture (AIA) Incoming MSI Controller (IMSIC) is a message-signaled interrupt (MSI) solution designed for the RISC-V External interrupt. However, due to the lack of native support for Software-Interrupt, IPI was forced to mix with IMSIC interrupts. In large systems, inter-processor interrupts (IPIs) occur very frequently and in large numbers, far exceeding the number of device interrupts. To alleviate IPI pressure on the Network-on-Chip (NoC), an interrupt-forwarding router is typically designed. However, the requirement for 2048 interrupt sources in the AIA IMSIC consumes a significant amount of SRAM in the BITMAP design, increasing chip area and cost. To improve IPI doorbell efficiency, hardware logic for merge-and-absorption based on BITMAP also needs to be designed per-hart at the transmitter, but AIA IMSIC's large interrupt sources design makes this design expensive. Furthermore, IMSIC's IPI allows any MSI-capable device to forge an IPI by sending a specific interrupt number, causing unnecessary disruption. To bridge this gap, propose a Software MSI Controller (SMSIC) for AIA, an optional RISC-V hardware component tightly coupled to each hart. The idea of architecturally separating IPIs from external interrupts not only reduces the cost of improving IPI performance in large systems but also aligns with the original intent of the Software Interrupt design in the RISC-V Privileged Specification.", "description": "In a RISC-V system, Message Signaled Interrupt (MSI) is directed not just to a specific hart but to different domains within that hart, such as the machine or supervisor level, or the VM domain. So, SMSIC contains a separate interrupt file for each privilege level. The MSI write to the interrupt file would raise a software interrupt of that privilege level. When a hart also implements the H extension, its SMSIC has additional interrupt files for virtual harts, called guest interrupt files, which are similar to AIA IMSIC. The number of guest interrupt files an SMSIC has is determined by GEILEN, the number of supported guest external interrupts, as defined by the H extension, which is the same as AIA IMSIC. SMSIC reuses CSR_HGEIP to notify the hypervisor of the virtual machine, rather than introducing a new CSR, as in AIA IMSIC.", "recording_license": "", "do_not_record": false, "persons": [{"code": "ZAFG7Q", "name": "GUO Ren", "avatar": "https://cfp.riscv-europe.org/media/avatars/ZAFG7Q_5gT9cTS.webp", "biography": "A Linux kernel developer focuses on the CPU subsystem, including virtualization, IOMMU, PCIe, Heterogeneous Programming, and RV64ILP32.\r\n\r\nStaff Engineer, Alibaba Damo Academy", "public_name": "GUO Ren", "guid": "ce2c5ad7-9b7b-54a2-b1ca-d3dd06df2b40", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZAFG7Q/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LQRAW3/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LQRAW3/", "attachments": []}, {"guid": "7058f30f-8508-5fc5-9bd3-69a578fd3159", "code": "VXCZWW", "id": 211, "logo": null, "date": "2026-06-10T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-211-the-next-generation-risc-v-socs-for-space-communications", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VXCZWW/", "title": "The Next Generation RISC-V SoCs for Space Communications", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Non-Terrestrial Networks (NTN) require software-defined payloads to stretch the lifetime of space-components, while meeting strict real-time and power constraints. We evaluate the end-to-end 5G NTN up&downlink on a single rv64gc core. Measurements show that 273\u00d7 speedup is needed to run the uplink in 1ms transmission time interval (TTI). We argue that programmable decoupled vector datapaths, implementing the RISC-V \"V\" extension are the key to bridge performance gaps, while preserving long term flexibility for space-grade systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "D8AY99", "name": "Marco Bertuletti", "avatar": "https://cfp.riscv-europe.org/media/avatars/D8AY99_YMY4Xdf.webp", "biography": "Marco Bertuletti received the B.Sc. and M.Sc. degree in Electrical Engineering in Politecnico di Milano, Milano, Italy. He is currently pursuing his Ph.D. at ETH, Zurich, Switzerland, in the Integrated Systems Laboratory (IIS). His main interests are in the design of multi and many-core clusters of RISC-V processors for next-generation telecommunications.", "public_name": "Marco Bertuletti", "guid": "4032a92c-2967-5395-967f-d3589a159da8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/D8AY99/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VXCZWW/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VXCZWW/", "attachments": []}, {"guid": "7dce44b0-74b1-56e0-8dd0-e1dc725dd2c9", "code": "NWCNCN", "id": 155, "logo": null, "date": "2026-06-10T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-155-alpes-advanced-low-power-edge-skeleton", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NWCNCN/", "title": "ALPES: Advanced Low-Power Edge Skeleton", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The emergence of the open-source RISC-V Instruction Set Architecture has significantly democratized CPU and SoC design across a wide range of applications. By enabling companies to implement and customize their own processor architectures, rather than relying on proprietary solutions from a few vendors, RISC-V allows architectures to be tailored to specific application requirements. However, CPU and SoC development remains complex and demands substantial design and verification expertise. To address this challenge, several academic and industrial reference platforms have been introduced to accelerate RISC-V\u2013based SoC development. This abstract presents ALPES, a versatile SoC platform built around cores from the OpenHW Foundation. ALPES includes an application-class chipset based on the CVA6 processor, as well as multiple secondary chipsets built around the CV32E40P core, targeting safe and secure real-time use cases. ALPES provides a robust, pre-verified foundation for ASIC projects, supporting several research projects focused on the RISC-V ecosystem.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "TUKUZV", "name": "Emanuele Valea", "avatar": null, "biography": "", "public_name": "Emanuele Valea", "guid": "45210441-fc95-5da8-aab7-b5f818a8d404", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/TUKUZV/"}, {"code": "ZXXRKG", "name": "JEREMIE PESCATORE", "avatar": null, "biography": "", "public_name": "JEREMIE PESCATORE", "guid": "0fb8c9cc-eb22-52db-a9c3-73e7fe732732", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZXXRKG/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NWCNCN/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NWCNCN/", "attachments": []}, {"guid": "6e4c174f-7c1b-537a-b215-27d1970a95c2", "code": "HKZX8R", "id": 371, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/HKZX8R/xrce_stack_thesis-cropped_ihZMgxQ.svg", "date": "2026-06-10T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-371-towards-open-user-space-power-management-communication-interfaces", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HKZX8R/", "title": "Towards Open User-Space Power-Management Communication Interfaces", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Modern processors delegate power and thermal management to dedicated Power Control Systems (PCS), communicating through kernel-mediated interfaces such as SCMI or the emerging RPMI. \r\nPrior work has shown that end-to-end control quality is dominated by the power-management policy rather than by interface latency, leaving room to choose communication paradigms based on flexibility rather than raw latency. \r\nWe integrate Micro XRCE-DDS on ControlPULP, a RISC-V\u2013based PCS, connecting it to a user-space Agent on an ARM host via a custom shared-memory transport. \r\nThis design removes protocol logic from kernel drivers and naturally supports multi-controller coordination through a shared middleware layer. Experiments on a ZCU102 FPGA at 20 MHz show 490 \u03bcs of active processing per publication, 0.8 MB/s throughput, and a memory footprint under 11.2 KB for 32 topics. The resulting latency is comparable to SCMI [1] while enabling a more flexible communication model.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "LKCSJJ", "name": "Antonio del Vecchio", "avatar": null, "biography": "", "public_name": "Antonio del Vecchio", "guid": "1c8d2f9a-3516-576d-b8d8-258c2938aeb8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/LKCSJJ/"}, {"code": "HKYAWD", "name": "Emanuele Venieri", "avatar": null, "biography": "", "public_name": "Emanuele Venieri", "guid": "cd561a43-be92-50bf-a13c-f21b6ad66576", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HKYAWD/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HKZX8R/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HKZX8R/", "attachments": []}, {"guid": "882c7444-01d5-5296-a894-626ea0bbf041", "code": "ZFMXUE", "id": 287, "logo": null, "date": "2026-06-10T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-287-1w-envelope-area-energy-trade-offs-of-scalable-risc-v-systolic-arrays-in-sky130", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZFMXUE/", "title": "1W Envelope: Area-Energy Trade-offs of Scalable RISC-V Systolic Arrays in Sky130", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Deploying high-performance AI inference on autonomous drones requires a precise balance between computational throughput and a strict 1W power envelope. This paper presents a vertical design space exploration (DSE) of the RISC-V Gemmini accelerator, scaling from 8x8 to 32x32 mesh configurations in the SkyWater 130nm process. Through an end-to-end evaluation using a YOLOv4-tiny model on the VisDrone dataset, we demonstrate a 74.75% reduction in model memory footprint via INT8 quantization and a speedup of up to 2352x compared to a RISC-V CPU baseline. Our results indicate that while the 32x32 mesh excels in peak throughput, the 16x16 mesh represents the optimal \u201csweet spot\u201d for 1W-limited drone chiplets, combining high performance with manageable leakage and area.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "XDVSLL", "name": "Daniel Kl\u00fcnder", "avatar": "https://cfp.riscv-europe.org/media/avatars/XDVSLL_64Xvdiw.webp", "biography": "", "public_name": "Daniel Kl\u00fcnder", "guid": "80c79142-63b0-58a8-b003-d8986f2de6ce", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/XDVSLL/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZFMXUE/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZFMXUE/", "attachments": []}, {"guid": "448248a6-f39c-51a5-ae78-3f9619aaa1b3", "code": "PYSBZM", "id": 203, "logo": null, "date": "2026-06-10T14:20:00+02:00", "start": "14:20", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-203-low-power-floating-point-unit-for-risc-v-processors-using-fphub-format", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PYSBZM/", "title": "Low-power Floating Point Unit for RISC-V Processors using FPHUB format", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "In this paper, we present the results of the XXXXXXXX project, in which a fully open-source, parametrizable low-power floating-point unit (FPU) under HUB format has been designed and validated. This unit, implemented in SystemVerilog, supports addition, subtraction, multiplication, division, square root, and Fused Multiply-Add (FMA) operations under HUB format. This FPU has been exhaustively tested through simulation and FPGA implementations. Moreover, it has been integrated with some RISC-V cores and validated using several test benches. The development is complemented by a compiler environment that enables native FPHUB arithmetic for C and C++ programs. The proposed unit achieves a roughly 60\\% reduction in area and power consumption compared with a classic IEEE FPU implementation.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "S3CLBQ", "name": "Javier Hormigo", "avatar": null, "biography": "", "public_name": "Javier Hormigo", "guid": "b1d6b59c-e79f-5e42-9e7a-4a406e55f2b5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/S3CLBQ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PYSBZM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PYSBZM/", "attachments": []}, {"guid": "c993f9e1-6e3f-5f72-9f34-6facc5b38990", "code": "UCSJXG", "id": 28, "logo": null, "date": "2026-06-10T15:30:00+02:00", "start": "15:30", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-28-bringing-cloud-connected-automotive-workloads-to-risc-v-a-cva6-based-fpga-case-study", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UCSJXG/", "title": "Bringing Cloud-Connected Automotive Workloads to RISC-V: A CVA6-Based FPGA Case Study", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "An end-to-end case study evaluating cloud-connected workloads on CVA6 platforms is presented.\r\nSystem behaviour under increasing telemetry loads is analysed using CAN trace replay.\r\nThe results provide empirical insights into the suitability of open RISC-V platforms for industrial deployment and highlight further optimisation.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "JLYSHY", "name": "Tianhai Liu", "avatar": "https://cfp.riscv-europe.org/media/avatars/JLYSHY_TjJKEUT.webp", "biography": "Dr. Tianhai Liu is a postdoctoral researcher at KIT and a project lead at aicas GmbH. His work focuses on formal methods, consistency analysis, and verification for cyber-physical systems, with applications in automotive software, IoT architectures, and FPGA-cloud integration.", "public_name": "Tianhai Liu", "guid": "b0ece579-d153-5eb1-bec8-886ab04b3d92", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JLYSHY/"}, {"code": "8Z8ZUM", "name": "Holger Blasum", "avatar": null, "biography": "Holger Blasum is research engineer at SYSGO GmbH, with interests in architecture, design, implementation and verification (including formal methods) of safe and secure systems.", "public_name": "Holger Blasum", "guid": "f21a08c0-9821-51cf-9812-64f7f305a982", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/8Z8ZUM/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UCSJXG/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UCSJXG/", "attachments": []}, {"guid": "f5351021-db89-54e4-9bf2-86822e72ca85", "code": "UZ9UMQ", "id": 29, "logo": null, "date": "2026-06-10T15:40:00+02:00", "start": "15:40", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-29-risc-v-vs-arm-in-an-embedded-real-time-system", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UZ9UMQ/", "title": "RISC-V vs. ARM in an Embedded Real-Time System", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The Raspberry Pi Pico2 is an ideal platform to showcase the state of RISC-V capabilities in the realm of embedded real-time systems. When switching from the ARM Cortex-M33 to the RISC-V Hazard3 CPU cores everything else stays the same: memory subsystem, clock tree, peripherals. This allows for an apples-to-apples comparison of the relative strengths and weaknesses of the two CPU implementations by compiling the same C code for both architectures. We present a detailed comparison of relative performance and assembly code differences as well as insight on how much effort using RISC-V instead of ARM on the RP2350 MCU powering the Pico2 really adds.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "RBGF8D", "name": "Christian Wenzel-Benner", "avatar": null, "biography": "Christian Wenzel-Benner completed a dual engineering degree at the former DaimlerChrysler AG / University of Cooperative Education in Stuttgart. After several years of ECU development at Bosch, he took on tasks as project manager and later as a specialist for embedded systems & security at ITK Engineering.\r\nDuring this time, he earned a Master of Science at Brunel University West London and led an embedded systems benchmarking team for the international NIST SHA-3 standardization competition. \r\nSince the end of 2015, he has been responsible for customer-specific solutions and training at GLIWA and works as a part time university lecturer.", "public_name": "Christian Wenzel-Benner", "guid": "fe41b189-90fb-5beb-badb-9ca58dfb68eb", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/RBGF8D/"}, {"code": "NQ8GH8", "name": "Germano Brunacci", "avatar": null, "biography": "Germano Brunacci earned his degree in Electronic Engineering from the University of Ferrara, Italy, in 2000. He began his career as a firmware developer, contributing to projects across the automotive, medical, and telecommunications sectors from 2000 to 2010.\r\n \r\nIn 2010 he joined FIAMM, and later MIDAC, where he served as Firmware Lead Engineer, focusing on Battery Management Systems (BMS) for advanced battery technologies. From 2018 to 2023, he was BMS Component Responsible for 800 V Battery Electric Vehicles (BEVs) at MASERATI, playing a key role in high-voltage system development.\r\n \r\nSince 2023, Germano has been part of GLIWA, where he is involved in development of customer specific solutions, as well as training and coaching activities in the field of real-time embedded systems.", "public_name": "Germano Brunacci", "guid": "b85910de-eb90-5485-817d-5ece9d7146b2", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/NQ8GH8/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UZ9UMQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UZ9UMQ/", "attachments": []}, {"guid": "fa45e41f-b731-51c7-a7c0-c13566d87777", "code": "MKEL9U", "id": 170, "logo": null, "date": "2026-06-10T15:50:00+02:00", "start": "15:50", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-170-risc-v-address-encoded-byte-order-extension", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MKEL9U/", "title": "RISC-V Address-Encoded Byte Order Extension", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "In certain scenarios computer systems have to deal with both little-endian and big-endian data regardless their native endianness. A RISC-V extension that makes it possible to remove the overhead introduced when dealing with foreign-endian data is proposed. It can be implemented with little engineering effort and negligible impact on performance and hardware resources. Preliminary results show that the extension can remove a 62% or 37% of foreign-endian data processing overhead when compared to software solutions using the base Instruction Set Architecture (ISA) or the currently available bit manipulation extensions respectively. This performance boost can benefit both new and legacy software once compiler and library support is put in place.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "8P8EUD", "name": "David Guerrero Martos", "avatar": null, "biography": "", "public_name": "David Guerrero Martos", "guid": "f12e963b-a8fc-51f2-8cbd-2fb5744b7de3", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/8P8EUD/"}, {"code": "RVHPQX", "name": "Jorge", "avatar": null, "biography": null, "public_name": "Jorge", "guid": "f7bf65ef-498f-5fab-b313-f9cdd79daa7d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/RVHPQX/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MKEL9U/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MKEL9U/", "attachments": [{"title": "Poster", "url": "/media/eu-summit-2026/submissions/MKEL9U/resources/2026-RISCV_Summit_po_wGxbVyu.pdf", "type": "related"}]}], "Devzone": [{"guid": "52fc6c10-e064-5d66-9799-5ce37cb744e8", "code": "QEAHWX", "id": 64, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/QEAHWX/demo_overview_Q9cJS8W_ebufI3b_vwxAPZe.webp", "date": "2026-06-10T10:30:00+02:00", "start": "10:30", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-64-on-device-context-informed-incremental-learning-for-myoelectric-control-on-risc-v-based-wearable-platform", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QEAHWX/", "title": "On-Device Context-Informed Incremental Learning for Myoelectric Control on RISC-V-based Wearable Platform", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "This live demonstration showcases our custom surface electromyography (sEMG) armband, enabling 16-channel monopolar acquisition. It features the RISC-V-based GAPWatch platform, which integrates two ADS1298 ADCs, an ESP32 radio module, GAP9 (a programmable multi-core RISC-V processor), and an STM32U5 microcontroller acting as a system gateway.\r\nThe armband is used to control a cursor in a 2D reach-and-hold task through EMG gestures. The system runs a context-informed incremental learning pipeline directly on GAP9. EMG signals are acquired, filtered, and fed to a tiny CNN, which predicts one of four gestures mapped to cursor directions (e.g., index finger contraction for LEFT, middle finger contraction for UP, etc.). Predictions are transmitted via BLE to a computer running the GUI with the task. The GUI updates the cursor position and derives a pseudolabel from the task context. If the predicted movement brings the cursor closer to the target, the pseudolabel acts as a reward signal; otherwise, it provides corrective feedback. This pseudolabel is returned to the device, where the CNN is updated via stochastic gradient descent (SGD). A replay mechanism is also implemented to stabilize training. EMG processing, inference, and SGD are all executed on GAP9.\r\nDuring the demo, a participant will perform the task starting from an untrained model. As the task progresses, attendees can observe real-time on-device adaptation. The demonstration highlights how parallel RISC-V processing enables fully embedded, adaptive HMIs without reliance on the cloud or external PCs for recalibration.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "GFJBAR", "name": "Mattia Orlandi", "avatar": "https://cfp.riscv-europe.org/media/avatars/GFJBAR_NsgetsI.webp", "biography": "Mattia Orlandi received his M.Sc. degree in Artificial Intelligence from the University of Bologna, Italy, in 2022. He is currently pursuing his Ph.D. in Data Science and Computation under the supervision of Prof. S. Benatti at the Energy-Efficient Embedded Systems Laboratory (EEES Lab), DEI Department, University of Bologna. His research activities involve bio-signal processing with machine learning on low-power computing platforms. He is investigating how to develop advanced human-machine interfaces based on EMG.", "public_name": "Mattia Orlandi", "guid": "ffbb6dd5-af60-5ad1-bfc4-784ffe224496", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GFJBAR/"}, {"code": "CUDA7T", "name": "Margherita Rossi", "avatar": null, "biography": "", "public_name": "Margherita Rossi", "guid": "dc298493-0c2b-5bd4-a413-6857f222dcd5", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CUDA7T/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QEAHWX/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QEAHWX/", "attachments": []}, {"guid": "218e25cf-2cad-5169-82f7-e4c24074bbb5", "code": "GQUDKS", "id": 100, "logo": null, "date": "2026-06-10T13:00:00+02:00", "start": "13:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-100-running-ilp32-on-rva-22-23-s64-ai-glasses-product-demo", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GQUDKS/", "title": "Running ILP32 on RVA(22/23)S64: AI Glasses Product Demo", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "Historically, many architectures have attempted to run ILP32 software on 64-bit ISAs, such as x86-X32, mips-N32, and arm64-ILP32. However, only arm64ilp32 achieved commercial success on Apple Watch OS in a closed-source manner.\r\n\r\nToday, we present the commercial deployment of RV64-ILP32 based on Allwinner v861 AI Glasses chips (Dual-Core RISC-V XuanTie C907) [1]. This demo showcases AI Glasses running the ILP32 Linux kernel on RVA22S64. Compared to traditional RV32, performance improves significantly: iperf throughput reaches 1.5\u00d7, and lmbench shows 1.1\u20131.2\u00d7 gains across most tests. Furthermore, another demo runs LP64 applications on an RV64-ILP32 Linux kernel within a 2GB address space for the first time, highlighting this ABI's compatibility, flexibility, and potential. This demo achievement marks a milestone in bringing 64-bit RISC-V architectural benefits to resource-constrained embedded AI devices while maintaining ILP32 memory efficiency based on an open-source software stack.\r\n\r\n[1]: https://www.cnx-software.com/2026/01/04/allwinner-v861-dual-core-64-bit-risc-v-ai-camera-sip-features-128mb-ddr3l-4k-h-265-h-264-video-encoder/\r\n\r\nThis demo illustrates ILP32 on RVA (22/23) S64.\r\nNext, call for sponsors for ILP32 on RVA (22/23) U64!", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "ZAFG7Q", "name": "GUO Ren", "avatar": "https://cfp.riscv-europe.org/media/avatars/ZAFG7Q_5gT9cTS.webp", "biography": "A Linux kernel developer focuses on the CPU subsystem, including virtualization, IOMMU, PCIe, Heterogeneous Programming, and RV64ILP32.\r\n\r\nStaff Engineer, Alibaba Damo Academy", "public_name": "GUO Ren", "guid": "ce2c5ad7-9b7b-54a2-b1ca-d3dd06df2b40", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZAFG7Q/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GQUDKS/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/GQUDKS/", "attachments": []}, {"guid": "456d13b9-cd1d-5900-aee3-facb0bfe22b1", "code": "LMUL9F", "id": 60, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/LMUL9F/overview_new_Uyo80Mm_SPDYAGZ.webp", "date": "2026-06-10T13:30:00+02:00", "start": "13:30", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-60-risc-v-edge-inference-for-real-time-eye-movement-control-on-gapses-smart-glasses", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LMUL9F/", "title": "RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "This live demonstration showcases GAPses, an ultra-low-power smart-glasses platform based on an ultra-low power RISC-V multicore processor (GAP9), enabling always-on, real-time, energy-efficient edge processing of electrooculography (EOG) and electroencephalography. GAPses performs on-device signal processing and machine-learning inference, converting raw biosignals into events without cloud compute or continuous high-bandwidth streaming, enabling energy-scalable and privacy-preserving operation. In the demo, dry electrodes integrated into the glasses frame capture horizontal/vertical EOG, and an on-device lightweight CNN running on GAP9 classifies saccadic eye movements from these EOG signals in real time. The resulting eye-movement events are transmitted via BLE to a laptop running a visualization application, which displays the CNN outputs alongside filtered EOG traces. The classification stream drives multiple interactive scenarios, including grid control, a Tetris game, and live class-probability visualization. During the demo session, we will run the complete pipeline live: a team member will wear the glasses and perform a sequence of saccades to trigger on-device CNN inference. The GUI updates in real time with predicted classes and EOG traces, allowing attendees to observe latency, robustness, and privacy benefits of RISC-V-based embedded biosignal inference in a practical wearable form factor. Overall, the demo highlights GAPses as an open, fully wearable research platform and illustrates how parallel RISC-V compute enables always-on neural interfaces by executing sensing, inference, and event-level decisions locally without cloud dependence or continuous high-bandwidth streaming.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HTMTSK", "name": "Sebastian Frey", "avatar": "https://cfp.riscv-europe.org/media/avatars/HTMTSK_BnJWb39.webp", "biography": "Sebastian Frey received his M.Sc. degree in Electrical Engineering and Information Technology from\r\nETH Z\u00fcrich, Switzerland, in 2022. He is currently working toward his Ph.D. in Information Technology and Electrical Engineering under the supervision of Prof. L. Benini at the Integrated Systems Laboratory, D-ITET, ETH Zurich, Switzerland. His research interests focus on the design of intelligent, head-centric wearables and on applying machine learning for biosignal processing on low-power devices, aiming to advance smart wearable technologies for real-time health monitoring and human-computer interaction.", "public_name": "Sebastian Frey", "guid": "80a05b5f-fd90-51b3-8115-eb808aca5ca6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HTMTSK/"}, {"code": "UZZQXC", "name": "Andrea Helga Bernardi", "avatar": "https://cfp.riscv-europe.org/media/avatars/UZZQXC_anPTgen.webp", "biography": "", "public_name": "Andrea Helga Bernardi", "guid": "f0bbcc50-eb61-5829-836c-d51d7c56fdf9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UZZQXC/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LMUL9F/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LMUL9F/", "attachments": []}, {"guid": "18512a2a-3aad-571f-8ac3-e3082642f600", "code": "QBPTRZ", "id": 76, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/QBPTRZ/5c5520ca-1_UcQ5uCz_WvPjpty_D5_jwu0KKp.webp", "date": "2026-06-10T14:00:00+02:00", "start": "14:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-76-risc-v-edge-processing-for-real-time-unobtrusive-driver-state-monitoring-on-the-automotive-soc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QBPTRZ/", "title": "RISC-V Edge Processing for Real-Time Unobtrusive Driver State Monitoring on the Automotive SoC", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "This live demonstration showcases the integration of Carfield, a heterogeneous automotive RISC-V SoC for mixed-criticality edge  intelligence applications, with SHIELD, a non-intrusive, multimodal smart steering wheel. SHIELD enables robust, redundant acquisition of physiological signals to monitor the driver\u2019s state continuously. During the demo, dry electrodes embedded within the steering wheel synchronously measure electrocardiography (ECG), electrodermal activity (EDA), photoplethysmography (PPG), and body temperature from both hands. Raw signals are transmitted via the automotive CAN-FD protocol directly to the Carfield SoC, while simultaneously streaming to a PC GUI via Bluetooth Low Energy (BLE) or WiFi. The RISC-V core processes the incoming CAN-FD data stream in real time. It performs digital signal filtering and employs golden-standard algorithms, including the Pan-Tompkins algorithm for ECG and PPG peak detection, to analyze heart rate (HR) and heart rate variability (HRV) in both the time and frequency domains. In the live session,(see Figure 1), a team member will use the smart steering wheel during a dynamic driving simulation using BeamNG.tech. Attendees will observe the GUI updating in real time, displaying the physiological waveforms alongside the HR and HRV metrics computed by Carfield.\r\nOverall, this demo illustrates how heterogeneous, open-source RISC-V architectures can efficiently handle vital sensor data acquisition and complex biosignal processing at the edge in a real-time automotive contest, paving the road for non-intrusive, real-time driver monitoring systems in next-generation vehicles.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HAA3MC", "name": "Massimo", "avatar": "https://cfp.riscv-europe.org/media/avatars/HAA3MC_sVF1njg.webp", "biography": "", "public_name": "Massimo", "guid": "360aad67-7213-56f1-bbf0-a5e36d5847cf", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HAA3MC/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QBPTRZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QBPTRZ/", "attachments": []}, {"guid": "e5836bf9-0432-5528-ad17-164ed7bbc02c", "code": "SRK9TJ", "id": 174, "logo": null, "date": "2026-06-10T15:30:00+02:00", "start": "15:30", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-174-end-to-end-on-device-transformer-training-on-ultra-low-power-risc-v-mcu", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SRK9TJ/", "title": "End-to-End On-Device Transformer Training on Ultra-Low Power RISC-V MCU", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "This demo showcases complete end-to-end Transformer training locally on the GAP9 RISC-V MCU. On-device training is crucial for applications that operate in dynamically changing environments. One example is biosignal DNNs in wearable devices, where cross-subject transfer and long-term temporal drift degrade performance. RISC-V MCUs are already widely used for edge DNN deployment. However, most existing work focuses either on inference only, or on fine-tuning a small portion of the network.\r\n\r\nWe extended the Deeploy compiler to generate training code. Deeploy generates bare-metal C code from an ONNX graph and is tailored for efficient inference. To support training, we added critical kernels such as optimizers and in-place gradient accumulators. We also extended the ONNX runtime training API to generate graphs optimized for edge deployment. This extension is released at https://github.com/pulp-platform/ONNX4Deeploy. To reduce the memory footprint of batching required for stable training, we implement gradient accumulation. The demo video showcases the full workflow, from training graph optimization to code generation and on-board execution. The video is available at https://drive.google.com/file/d/16BMiHn0jyMvScFJD7AGTwHpA4Rc0aMnC/view?usp=drive_link and will be uploaded to the Pulp Platform YouTube channel.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "D3YWSP", "name": "Victor Jung", "avatar": "https://cfp.riscv-europe.org/media/avatars/D3YWSP_YeHEI01.webp", "biography": "Victor Jean-Baptiste Jung received his Bachelor\u2019s Degree in Computer Science and Engineering Physics from Juniata College, and his Master\u2019s Degree in Computer Science from the Institut Sup\u00e9rieur de l\u2019Electronique et du Num\u00e9rique of Lille (ISEN Lille) in 2022. After 3 months as a research intern with KU Leuven\u2019s MICAS Research group, supervised by Prof. Marian Verhelst, he's currently pursuing his Ph.D. at the Integrated Systems Laboratory with Prof. Dr. Luca Benini. His current research interests include Efficient deployment of ML models on Microcontrollers, Tiny Transformers, Scheduling, and Quantization.", "public_name": "Victor Jung", "guid": "9d3da4dc-aee1-5ce3-8654-c9c9dd0d11a1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/D3YWSP/"}, {"code": "9ZE98D", "name": "RunW", "avatar": "https://cfp.riscv-europe.org/media/avatars/9ZE98D_PJ0Am0r.webp", "biography": "", "public_name": "RunW", "guid": "d7bb355d-91c0-5058-a2c0-768b3d2c53d2", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9ZE98D/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SRK9TJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/SRK9TJ/", "attachments": [{"title": "Abstract Pdf", "url": "/media/eu-summit-2026/submissions/SRK9TJ/resources/_RISC_V_Summit_2026__ZmRbwHN.pdf", "type": "related"}]}]}}, {"index": 4, "date": "2026-06-11", "day_start": "2026-06-11T04:00:00+02:00", "day_end": "2026-06-12T03:59:00+02:00", "rooms": {"Plenary": [{"guid": "38a8cf12-c5e6-5b91-b55a-0a60298b2fb3", "code": "MCBEUE", "id": 232, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/MCBEUE/lev_EnYwpTD_mnONbmA_6mvnL6H_P_ULkuEdi.webp", "date": "2026-06-11T10:00:00+02:00", "start": "10:00", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-232-world-s-first-lunar-exploration-rover-using-fpga-based-risc-v-processor", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MCBEUE/", "title": "World's first lunar exploration rover using FPGA-based RISC-V processor", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "A small lunar rover named \"LEV-1\" made surface mobility exploration on the Moon in January 2024. This was the first lunar exploration robot in our country. LEV-1 was installed in the lunar lander \"SLIM\" and was deployed onto the Moon surface just before landing.\r\n\r\nLEV-1 explored over the landing area fully autonomously after the deployment. The obained data inclusing images were directly transmitted to the Ground with no relay by the lander.\r\n\r\nThe onboard computer of the rover used a RISC-V soft-core CPU implemented within the FPGA. The system is one of the world's first onboard computers using a RISC-V processor being operated on the Moon.\r\n\r\nThis paper describes the configuration of the RISC-V controller installed on LEV-1 rover as well as the technical background for using RISC-V in space applications.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "ZLVBEP", "name": "Tetsuo YOSHIMITSU", "avatar": null, "biography": "He is a professor at the Institute of Space and Astronautical Science (ISAS) of the Japan Aerospace Exploration Agency (JAXA). He is engaged in solar system exploration, particularly research on planetary exploration rovers for celestial surfaces. As principal investigator, he developed the MINERVA and MINERVA-II rovers for the asteroid sample return missions of the Hayabusa and Hayabusa2 spacecraft. He has also been involved in multiple lunar exploration missions, including the OMOTENASHI CubeSat and the SLIM landing mission. He served as principal investigator for the LEV-1 rover for the SLIM mission.", "public_name": "Tetsuo YOSHIMITSU", "guid": "db57674f-bd51-5662-a120-f5014549b7ad", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/ZLVBEP/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MCBEUE/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MCBEUE/", "attachments": []}, {"guid": "e06da5ce-6f80-58a1-9e27-eb3fe19756cc", "code": "WHFNV3", "id": 190, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/WHFNV3/bianbu-lxqt_wRZ2uML_wGYW5R3_F_qafo11A.webp", "date": "2026-06-11T10:15:00+02:00", "start": "10:15", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-190-a-user-friendly-and-ai-ready-desktop-for-risc-v-bianbu-lxqt", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WHFNV3/", "title": "A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "We present Bianbu LXQt, a user-oriented desktop environment for RISC-V platforms built on a deeply adapted LXQt software stack, optimized for real hardware such as SpacemiT\u2019s K1 and K3 SoCs. Unlike straightforward ports that assume x86-like hardware standardization, this work addresses common RISC-V Linux challenges, including fragmented peripheral support and the absence of a unified hardware abstraction layer. SpacemiT's CPUs integrate AI-oriented instruction extensions such as IME, enabling CPU-based inference without discrete GPUs or NPUs, requiring coordinated adaptation across the OS and AI frameworks.\r\nPreserving LXQt\u2019s lightweight design, we redesigned the UI and interaction logic to improve responsiveness and visual consistency on resource-constrained RISC-V systems. Development was accelerated using AI-assisted tooling, while continuous feedback from educators and early adopters guided iterative fixes for lag, crashes, and complex configuration\u2014letting users focus on creation, learning, and development rather than system tuning.\r\nThe full software stack is open source with reproducible builds and modular components. We proved educational AI examples covering image recognition, speech processing, video analysis, and large language model inference,  all with intuitive GUIs. Frameworks including ONNX Runtime, llama.cpp, and Ollama run reliably, demonstrating the feasibility of RISC-V systems for AI deployment and local AI development.\r\nThrough practical system integration, community-driven iteration, and accessible AI tooling, this work shows RISC-V can deliver a polished, daily-driver desktop environment\u2014moving beyond a demo into a trusted open platform for developers, educators, and innovators.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3VQGA9", "name": "Xiaogang Fan", "avatar": null, "biography": "", "public_name": "Xiaogang Fan", "guid": "0f7b9a57-96e6-5e87-8b32-f9513cd84d20", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3VQGA9/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WHFNV3/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WHFNV3/", "attachments": []}, {"guid": "5c5025e4-1a0a-58e2-a27c-0a90b12636c1", "code": "ETWPMQ", "id": 201, "logo": null, "date": "2026-06-11T12:00:00+02:00", "start": "12:00", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-201-all-the-scaling-no-new-state-one-matrix-isa-with-microarchitectural-freedom", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ETWPMQ/", "title": "All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "RISC-V's Zvvm matrix extension stores all tile state in the standard V register file and derives tile geometry algebraically from VLEN, SEW, and a new aspect-ratio field \u03bb. This yields arithmetic intensity that scales with VLEN: a binary compiled at VLEN=256 delivers higher throughput at VLEN=65536 with no recompilation. The same partial-VL mechanism that enables one-column-at-a-time embedded streaming also drives full HPC bulk tiling, while microscaling is integrated via vm-bit opcode aliasing with no new architectural state.\r\n\r\nTile dimensions are not programmer-specified constants \u2014 they are consequences of existing parameters. The tile is always square: M = N = VLEN/(SEW\u00d7\u03bb), with inner dimension K\\_eff = \u03bb\u00d7W\u00d7LMUL. Arithmetic intensity (M/2) grows proportionally with VLEN, and the ratio of intensity to cache-to-VRF bandwidth remains constant \u2014 a provable algebraic identity with no equivalent in Arm SME or Intel AMX.\r\n\r\nZvvm's geometry knobs form an intent vocabulary expressed from both sides: software selects LMUL and VL to control K\\_eff depth and streaming granularity; hardware determines \u03bb and VLEN to shape the tile for its datapath. Setting VL = K\\_eff with LMUL = 1 gives portable streaming; increasing LMUL or computing multiple C panels trades register pressure for compute intensity \u2014 all via the same opcode.\r\n\r\nMicroscaling (MX) support is integrated by aliasing the vm bit in FP multiply-accumulate opcodes, introducing no new encoding space, registers, or modes.", "description": "This extended abstract presents Zvvm, a RISC-V matrix ISA extension that takes a fundamentally different approach from Arm SME and Intel AMX. Where SME requires a dedicated ZA register file and streaming mode, and AMX uses fixed 16\u00d716 tiles that cannot exploit wider datapaths without ISA revision, Zvvm stores all matrix state in the standard V register file, derives tile geometry algebraically from existing CSR fields, and introduces no new architectural state or modes.\r\n\r\nThis presentation offers a rare window into the architects' design rationale behind a matrix ISA approach that has no counterpart in the industry. Rather than presenting a finished specification, we expose the algebraic foundations, the interplay of five independent geometry knobs (VLEN, \u03bb, LMUL, VL, W), and the deliberate trade-offs that allow one ISA \u2014 and one binary \u2014 to span from a VLEN=128 microcontroller streaming one column at a time to a VLEN=65536 supercomputer computing full tiles.\r\n\r\nWe show how partial-VL streaming and full bulk tiling are two ends of the same VL continuum, how the bidirectional intent vocabulary lets software and hardware independently express their capabilities through the same opcode, and how microscaling (MXFP8, MXFP4, MXINT8) is integrated via vm-bit opcode aliasing with zero overhead. The design is validated by a public QEMU implementation, BLAS kernels, and a parameterized test suite covering all (SEW, \u03bb, LMUL) combinations \u2014 enabling concurrent hardware and software development against a stable, machine-testable specification.", "recording_license": "", "do_not_record": false, "persons": [{"code": "XNGHCM", "name": "Dr. Philipp Tomsich", "avatar": "https://cfp.riscv-europe.org/media/avatars/XNGHCM_eI9EGVb.webp", "biography": "Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL GmbH, providing strategic R&D for semiconductor companies. He chairs the RISC-V Applications & Tools Committee, serves on the RISC-V Board of Directors, and is Vice-Chair of the Technical Steering Committee, where he champions software ecosystem growth and standards alignment, including efforts to publish RISC-V under ISO.\r\n\r\nHe instigated the standards-development matrix operations and AI/ML, serving as principal editor of the Integrated Matrix Extension and as the Vice-chair of the Attached Matrix TG.", "public_name": "Dr. Philipp Tomsich", "guid": "6f41581c-6add-516d-b1be-1bb922640c67", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/XNGHCM/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ETWPMQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ETWPMQ/", "attachments": []}, {"guid": "1fd456fc-5257-5d7e-bbb0-e19ac155e082", "code": "G7Y79Q", "id": 285, "logo": null, "date": "2026-06-11T12:15:00+02:00", "start": "12:15", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-285-arcane-enabling-high-performance-in-cache-tensor-extensions-in-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7Y79Q/", "title": "ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "Modern data-centric workloads increasingly expose the limitations of traditional von Neumann architectures, where excessive data movement limits throughput and energy efficiency.\r\n        While hardware accelerators improve performance, they often lack flexibility and still require costly memory transfers.\r\n        Existing compute in- and near-memory solutions reduce the memory bottleneck but introduce usability challenges related to constraints on data placement.\r\n        ARCANE is a cache architecture that doubles as a tightly-coupled near-memory coprocessor.\r\n        The embedded RISC-V cache controller executes custom instructions offloaded by the host CPU relying on near-memory vector processing units within the cache memory subsystem. This architecture hides memory synchronization and data mapping from application software, while offering software-based Instruction Set Architecture extensibility.\r\n        Evaluations demonstrate up to an 84x speedup on 8-bit convolution layers over a traditional system-on-chip, incurring only a 41.3\\% area overhead.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EAKGEL", "name": "Flavia Guella", "avatar": "https://cfp.riscv-europe.org/media/avatars/EAKGEL_Wwp5tss.webp", "biography": "Flavia Guella received the B.S. and M.S. (both with summa cum laude) in Electronics Engineering from Universit\u00e0 degli Studi di Palermo in 2020, and Politecnico di Torino in 2023, respectively. She is currently pursuing the Ph.D. program in Electronics and Communications Engineering at Politecnico di Torino, under the supervision of Prof. Maurizio Martina and Prof. Guido Masera. Her research interests include RISC-V based in-cache computing, and co-design methodologies for the efficient deployment of neural networks on low-power systems.", "public_name": "Flavia Guella", "guid": "22fe7d6c-76d3-557b-b5e7-3a1dc3c88dc7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EAKGEL/"}, {"code": "A87H8N", "name": "Vincenzo Petrolo", "avatar": null, "biography": "", "public_name": "Vincenzo Petrolo", "guid": "4af34515-e5b6-505b-8bf0-315bbc2dc6c8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/A87H8N/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7Y79Q/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G7Y79Q/", "attachments": []}, {"guid": "cbaa9206-7928-5ae1-8800-3ab44c104485", "code": "HNQPKX", "id": 370, "logo": null, "date": "2026-06-11T12:30:00+02:00", "start": "12:30", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-370-evaluating-tenstorrent-risc-v-accelerators-for-high-performance-scientific-computing", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HNQPKX/", "title": "Evaluating Tenstorrent RISC-V Accelerators for High Performance Scientific Computing", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "We implemented an N-body astrophysical simulation code and offloaded its most computationally intensive kernel to Tenstorrent RISC-V\u2013based accelerators using the TT-Metalium programming interface. Performance was assessed on the Wormhole n300 card in terms of execution time and energy consumption, and compared with both an optimized CPU implementation and a CUDA version. The TT-Metalium implementation achieves a speedup of 2\u00d7 over the CPU baseline, although its performance still slightly lags behind the CUDA implementation. Finally, we investigated strategies for scaling the application across multiple Tenstorrent accelerators, evaluating configurations with up to four devices.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "M3YPYK", "name": "Elisabetta Boella", "avatar": "https://cfp.riscv-europe.org/media/avatars/M3YPYK_hTOYKU0.webp", "biography": "Elisabetta Boella received her M.Sc. degree in Energy and Nuclear Engineering in 2009 from Politecnico di Torino (Turin, Italy) and her Ph.D. in Computational Plasma Physics in 2014 from the same institution. She currently works as HPC product specialist at E4 Computer Engineering (Scandiano, Italy), where she leads the company effort in several European projects, including MaX, SPACE and EoCoE. Her research interests include numerical modelling, parallel programming, and co-design practices. She has a long-time experience in the development and optimisation of parallel codes using the Message Passing Interface protocol. She is one of the main developers of the massively parallel plasma code ECsim. She also has extensive experience in Graphical Processing Unit (GPU) programming and off-loading of legacy codes to GPU.", "public_name": "Elisabetta Boella", "guid": "e72b9abf-8288-50d8-9d82-ae965e9815bc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/M3YPYK/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HNQPKX/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HNQPKX/", "attachments": []}, {"guid": "b69b38ce-541c-5c67-a88f-688c134d2ddd", "code": "FRDLL7", "id": 290, "logo": "https://cfp.riscv-europe.org/media/eu-summit-2026/submissions/FRDLL7/chakra_flow_MMZJQtC_xnihweE.webp", "date": "2026-06-11T12:45:00+02:00", "start": "12:45", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-290-chakra-gp-a-retargetable-compiler-framework-for-risc-v-gpgpu-architectures", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FRDLL7/", "title": "CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "The emergence of RISC-V as an open and extensible instruction set architecture has enabled the development of domain-specific accelerators and General-Purpose Graphics Processing Units (GPGPUs). While the RISC-V ISA provides support for scalar instructions and the RISC-V Vector Extension (RVV) enables data-parallel vector execution, these models do not directly support the Single-Instruction Multiple-Thread (SIMT) execution paradigm required by modern GPU architectures. Consequently, efficient software enablement for RISC-V\u2013based GPUs requires compiler support capable of generating SIMT-oriented instruction sequences and managing massively parallel execution. This proposal talks about CHAKRA-GP, a hardware-optimized compiler framework for RISC-V\u2013based GPGPU architectures. Built upon LLVM and MLIR infrastructures, CHAKRA-GP provides a scalable compilation pipeline enabling efficient kernel generation, memory optimization, and parallel execution mapping for massively parallel workloads. The compiler targets custom RISC-V GPGPU platforms and enables efficient execution of HPC, scientific computing, and AI workloads. The work demonstrates how an extensible compiler infrastructure can bridge the gap between the RISC-V ISA and SIMT-based GPU execution models, enabling efficient compilation for customizable RISC-V GPGPU architectures.", "description": "This work presents CHAKRA-GP, a compiler framework targeting RISC-V\u2013based GPGPUs that combines domain-specific optimization pipelines with unified LLVM-based code generation. HPC workloads are compiled through a direct LLVM [5] optimization flow that generates SIMT [6][7] execution and custom memory instructions optimized for throughput-oriented computation. AI workloads are processed using an MLIR-based [8] pipeline that preserves tensor semantics and performs structured transformations before lowering to LLVM IR for final instruction generation targeting tensor and matrix compute cores.\r\nBy integrating MLIR-driven high-level optimization with LLVM\u2019s mature backend infrastructure, CHAKRA-GP enables efficient mapping of heterogeneous workloads onto customizable RISC-V GPU architectures while maintaining retargetability across evolving designs. The proposed approach demonstrates how compiler architecture can support co-design of open GPU hardware and software ecosystems for next-generation HPC and AI platforms.", "recording_license": "", "do_not_record": false, "persons": [{"code": "AMGGLL", "name": "Prachi Pandey", "avatar": "https://cfp.riscv-europe.org/media/avatars/AMGGLL_4hHMX1G.webp", "biography": "Ms. Prachi Pandey is a Senior Compiler Engineer at C-DAC, where she works on MLIR/LLVM-based compiler development for indigenous processors, GPUs, and AI accelerators. She has nearly two decades of experience in HPC, parallel programming, compilers, and runtime systems. Her research interests include compiler optimization techniques, automatic parallelizing compilers, performance portability for heterogeneous architectures, and parallelization strategies for HPC and AI workloads.", "public_name": "Prachi Pandey", "guid": "784470bb-6909-5518-8d6e-2183cb128a6d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AMGGLL/"}, {"code": "UUME9J", "name": "PRANOSE J EDAVOOR", "avatar": null, "biography": "", "public_name": "PRANOSE J EDAVOOR", "guid": "227f9418-57df-5186-8a60-c880cbf5b781", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/UUME9J/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FRDLL7/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FRDLL7/", "attachments": []}, {"guid": "1613c26a-ba72-5586-8a3a-424c93312ba2", "code": "RRD8XA", "id": 273, "logo": null, "date": "2026-06-11T16:30:00+02:00", "start": "16:30", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-273-enabling-high-performance-storage-for-risc-v-porting-the-lustre-parallel-file-system", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RRD8XA/", "title": "Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "Lustre powers approximately 70% of TOP500 supercomputers and is essential infrastructure for high-performance computing (HPC). Our work enables RISC-V systems to access Lustre storage clusters, addressing a critical gap in the RISC-V HPC ecosystem. The port required only 8 minimal patches (19 lines changed across 9 files) to Lustre 2.17.0, demonstrating the maturity of both the RISC-V Linux ecosystem and Lustre\u2019s portable codebase. We validated functionality through QEMU-based testing with multi-client mount operations, FIO, and IOR benchmarks. The patches are being submitted upstream to the Lustre project for inclusion in future releases.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "8XT8LA", "name": "Dave Cremins", "avatar": "https://cfp.riscv-europe.org/media/avatars/8XT8LA_LMG1OPX.webp", "biography": "Dave Cremins is a Principal Cloud Software Engineer at OPENCHIP, where he specializes in designing and building advanced cloud\u2011native systems at scale. With deep expertise in distributed architectures, automation, and infrastructure engineering, Dave plays a key role in shaping technical strategy and delivering high\u2011impact engineering solutions across the organization.", "public_name": "Dave Cremins", "guid": "f8bf418b-33b1-5741-8e6d-f6f65e43e3dc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/8XT8LA/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RRD8XA/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RRD8XA/", "attachments": [{"title": "Presentation for talk", "url": "/media/eu-summit-2026/submissions/RRD8XA/resources/RISCV-EU-Summit-202_En1kscN.pptx", "type": "related"}]}, {"guid": "12f30cba-b843-5c10-8de5-adbc51aa5f7d", "code": "D3TVFS", "id": 197, "logo": null, "date": "2026-06-11T16:45:00+02:00", "start": "16:45", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-197-accelerating-sparse-linear-solvers-in-openfoam-using-risc-v-vector-extensions", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/D3TVFS/", "title": "Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions", "subtitle": "", "track": "Blind Submission (Default)", "type": "Talk", "language": "en", "abstract": "Computational Fluid Dynamics (CFD) relies heavily on the efficiency of linear solvers based on sparse linear algebra kernels. Widely used frameworks like OpenFOAM exploit parallelism primarily at the domain decomposi-tion level via MPI. Support for vector/SIMD architectures is limited to compiler auto-vectorization. Furthermore, support for such architectures is limited by OpenFOAM\u2019s internal matrix data format, which is intrinsically ill-suited for the contiguous memory accesses required for efficient execution on vector processors. In this work, we focused on two very different RISC-V architectures: the prototype long-vector EPAC accelerator and the commercial short-vector CPU Sophon SG2044. On these platforms, we optimized the Sparse Matrix-Vector multiplication (SpMV) using RISC-V vector intrinsics and integrated it into a custom smoother, performing a runtime conversion of internal data into a vector-friendly format. Experimental results on the EPAC test chip show a 6\u00d7 speedup for the smoother; benchmarks on Monte Cimone (MCv2) cluster with the Sophon SG2044 processor achieve a 1.5\u00d7 smoother speedup, proving that legacy CFD codes can be effectively accelerated on both research and commercial emerging hardware.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "LMYZ9M", "name": "Gabriele Ceccolini", "avatar": "https://cfp.riscv-europe.org/media/avatars/LMYZ9M_I9sBrO8.webp", "biography": "Gabriele Ceccolini received his Master's degree in Computer Engineering from the University of Bologna in March 2026. He previously obtained his Bachelor's degree from the same institution in 2023. Since May 2025, Gabriele has been collaborating with CINECA, focusing on the optimization of CFD algorithms on RISC-V platforms.", "public_name": "Gabriele Ceccolini", "guid": "090e4202-ec21-54d2-b867-8a2b956288f1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/LMYZ9M/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/D3TVFS/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/D3TVFS/", "attachments": []}, {"guid": "d39fec92-ce7f-5a81-b5a6-5cbf0603152d", "code": "TX9SGW", "id": 202, "logo": null, "date": "2026-06-11T17:00:00+02:00", "start": "17:00", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-202-optimizing-llama-cpp-and-ggml-for-risc-v-vector-rvv", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TX9SGW/", "title": "Optimizing Llama.cpp and GGML for RISC-V Vector (RVV)", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "Llama.cpp is a widely used open-source platform for running Large Language Models (LLMs) on CPUs, but its support for RISC-V remains limited compared to x86 and ARM. Many floating-point and quantized kernels lack RISC-V Vector (RVV) implementations, restricting the performance of existing hardware. This work improves the upstream RISC-V performance by vectorizing core floating-point kernels and extending support across multiple quantization types, enabling first-class support for RVV in Llama.cpp. VLEN-aware data repacking is introduced to accelerate GEMM and GEMV kernels for both floating point and quantization types. The optimized kernels are validated across VLENs up to 1024-bit, with benchmarking on Banana Pi BPI-F3 (256-bit VLEN) demonstrating considerable performance gains over upstream Llama.cpp. This work is supported by the RISC-V Software Ecosystem (RISE), with the vectorized kernels being upstreamed to Llama.cpp along with the test infrastructure.", "description": "This work is performed under RISE RP-014 - Optimizing Llama.cpp and GGML for RVV. All artifacts are open source and either upstreamed to Llama.cpp or in the process of being upstreamed. This contribution not only improves baseline RISC-V vector hardware performance for AI workloads, enabling adoption among AI developers, but also provides first-class software infrastructure support for RISC-V hardware makers to test, benchmark, and optimize standardized hardware solutions for AI workloads.", "recording_license": "", "do_not_record": false, "persons": [{"code": "DV3CZU", "name": "Taimur Ahmad", "avatar": "https://cfp.riscv-europe.org/media/avatars/DV3CZU_afOdHtF.webp", "biography": "", "public_name": "Taimur Ahmad", "guid": "2d1ba8c1-bde5-59e8-8155-79a80adcca13", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DV3CZU/"}, {"code": "GWHRLJ", "name": "Adeel Ahmad", "avatar": "https://cfp.riscv-europe.org/media/avatars/GWHRLJ_DikZTSu.webp", "biography": "I am a compiler engineer at 10xEngineers, working on enabling the compilation of LLMs and vision models for custom hardware/accelerators using IREE, an MLIR-based AI compiler. I have experience in writing optimized kernels for RISC-V Vector (RVV) and custom hardware, LLVM middle-end and backend development.", "public_name": "Adeel Ahmad", "guid": "202a90e8-44be-532e-828d-5399fcd45bd7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GWHRLJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TX9SGW/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/TX9SGW/", "attachments": []}, {"guid": "75c9439a-d424-51a5-a0ef-cc5d1a5629be", "code": "NHUVSR", "id": 342, "logo": null, "date": "2026-06-11T17:15:00+02:00", "start": "17:15", "duration": "00:15", "room": "Plenary", "slug": "eu-summit-2026-342-wuehans-a-full-stack-open-source-risc-v-gaming-console-and-soc-architecture", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NHUVSR/", "title": "wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture", "subtitle": "", "track": "Non-Blind submission", "type": "Talk", "language": "en", "abstract": "To address the lack of hardware sovereignty in proprietary console ecosystems, this paper presents a fully open-source RISC-V gaming platform utilizing a VexRiscv core and Lattice ECP5 FPGA. We implemented a custom SoC featuring dedicated 2D GPU and APU accelerators, supported by a complete LLVM-based toolchain and a high-level Game Development Framework API. Validation through a 48-hour game jam demonstrated the platform\u2019s utility, achieving a stable 640 \u00d7 480 at 60 FPS output and high power efficiency for independent development.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "EYMWSH", "name": "Jonathan Hager", "avatar": "https://cfp.riscv-europe.org/media/avatars/EYMWSH_z6mOXWZ.webp", "biography": "", "public_name": "Jonathan Hager", "guid": "6dc28d50-4553-5d9a-9c4f-cd2c510af428", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/EYMWSH/"}, {"code": "BKNYLP", "name": "Yannik Stamm", "avatar": null, "biography": "", "public_name": "Yannik Stamm", "guid": "87d4fa5e-029a-5500-9525-01aeeb001830", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BKNYLP/"}, {"code": "AAV8QY", "name": "Matthias Jung", "avatar": "https://cfp.riscv-europe.org/media/avatars/AAV8QY_vDHNrsT.webp", "biography": "He received the Diploma and PhD degree in electrical engineering from the Technische Universit\u00e4t Kaiserslautern, Germany, in 2011 and 2017, respectively. From 2011 to 2017 he was a researcher at the Microelectronic Systems Design Research Group of RPTU Kaiserslautern. Since 2017 he is with the Fraunhofer Institute for Experimental Software Engineering in Kaiserslautern as Expert Engineer for virtual hardware engineering. In 2018, he received the EDAA Outstanding Dissertation Award for this work. At Fraunhofer IESE in Kaiserslautern, he has been leading many research and industrial projects in the area of embedded systems since 2017 and has published more than 100 papers in relevant journals and conference proceedings. Since 2023, he is professor at the University of W\u00fcrzburg. Matthias Jung's scientific focus is on embedded and autonomous systems, especially with a focus on memory architectures, functional safety, and virtual product development of embedded systems through virtual platforms and simulations.", "public_name": "Matthias Jung", "guid": "55ca3b8a-4681-561f-88ed-a49a66a56925", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AAV8QY/"}, {"code": "DVKJ79", "name": "Timo Grundheber", "avatar": "https://cfp.riscv-europe.org/media/avatars/DVKJ79_yAqngfW.webp", "biography": "", "public_name": "Timo Grundheber", "guid": "b6097c0e-46eb-5a37-a720-e178431d29ee", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DVKJ79/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NHUVSR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/NHUVSR/", "attachments": []}], "Poster Island A": [{"guid": "958a4731-30ef-59b5-8c39-ecd05dcccb6b", "code": "G93SVJ", "id": 245, "logo": null, "date": "2026-06-11T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-245-accelerating-the-poseidon2-s-box-in-a-risc-v-soc-with-a-4-4-cgra", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G93SVJ/", "title": "Accelerating the Poseidon2 S-box in a RISC-V SoC with a 4\u00d74 CGRA", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Cryptographic hash algorithms for zero-knowledge proof systems often rely on prime-field S-box kernels such as x\u2077 mod p over 31-bit fields. We accelerate this class of S-box primitives on a 4\u00d74 coarse-grained reconfigurable array (CGRA) integrated within a RISC-V SoC. As a case study, we use the BabyBear instantiation adopted by the state-of-the-art Poseidon2 hash function, employing Barrett reduction to avoid software division on the host core. Our mapping decomposes operands into 8-bit limbs across CGRA processing elements and exploits the toroidal mesh for carry propagation in 4 hops. Compared to a hand-optimized baseline, we achieve 1.26\u00d7 speedup and 25.7% energy reduction; versus an automatic compiler, we improve by 6.6\u00d7 speedup and save 82% energy. Cycle-accurate RTL simulation of a full Poseidon2 integration shows ~3.3\u00d7 fewer cycles than the RISC-V host for the full 141-invocation workload at 100 MHz (even a ~1.3\u00d7 reduction at 250 MHz).", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HSGWBH", "name": "Cristian Campos", "avatar": null, "biography": "", "public_name": "Cristian Campos", "guid": "e8f326fe-8001-5882-b945-37f91e27a106", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HSGWBH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G93SVJ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/G93SVJ/", "attachments": []}, {"guid": "379f0ace-e68c-5b52-89b6-21aeedfdce95", "code": "LP7WTL", "id": 357, "logo": null, "date": "2026-06-11T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-357-energy-efficiency-optimization-of-a-risc-v-floating-point-unit-for-hpc-oriented-architectures", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LP7WTL/", "title": "Energy-Efficiency Optimization of a RISC-V Floating-Point Unit for HPC-Oriented Architectures", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "As High-Performance Computing (HPC) advances towards the Exascale era, energy efficiency has become the primary design constraint. In HPC systems, the Floating-Point Unit (FPU) is instantiated in massive numbers to support parallel workloads, that require huge number of floating point computations. Consequently, the FPU becomes a dominant consumer of dynamic power within the chip. This work presents an energy-optimized FPU for RISC-V Vector Processing Units. To address the inefficiencies of standard unified FMA datapath, we propose a Split-Path FMA micro- architecture tailored for the RISC-V Vector specification. Our design integrates the physical separation of the arithmetic pipelines with vector-aware clock gating and operand isolation. Evaluated in a commercial 4nm technology at 2 GHz, the optimized design demonstrates up to a 29% increase in energy efficiency for mixed-arithmetic workloads and a 7.8% performance speedup in vector reduction-heavy kernels.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CYFWYH", "name": "Marco Crisologo", "avatar": null, "biography": "", "public_name": "Marco Crisologo", "guid": "614609b4-06af-59bc-82f3-c11555e34f3e", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CYFWYH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LP7WTL/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LP7WTL/", "attachments": []}, {"guid": "b28849e8-6f0a-5f05-b26f-30bde01c6465", "code": "KGMSLQ", "id": 263, "logo": null, "date": "2026-06-11T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-263-lessons-learned-from-designing-decoupled-access-hardware-accelerators-in-a-risc-v-framework", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KGMSLQ/", "title": "Lessons Learned from Designing Decoupled-Access Hardware Accelerators in a RISC-V Framework", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Sparse tensor operations are critical for scientific computing but their irregular memory access patterns challenge traditional architectures. While domain-specific architectures offer efficiency, integration into mature SoCs often requires ISA modifications or complex driver development. This work addresses these challenges via a decoupled SpMV access unit integrated through Cohort, a coherent shared-memory queue interface communicating with a CVA6 RISC-V core. To mitigate the inter-tile communication overhead, we introduce a hybrid tiling approach that co-locates the access unit and the core in the same tile, enabling direct data delivery into the private cache. This hybrid architecture achieves significant performance gains, yielding geometric mean speedups of 1.33\u00d7 and 1.50\u00d7 for COO and CSR formats, respectively, over traditional multi-tile configurations. These results demonstrate that offloading memory traversal to a programmable data-flow engine, combined with optimized placement in the memory hierarchy, efficiently accelerates irregular workloads with minimal intrusion.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "YLYDCG", "name": "Xicu Mar\u00ed", "avatar": null, "biography": "", "public_name": "Xicu Mar\u00ed", "guid": "4ea34d8d-9207-5bfe-856e-eda4cbad015e", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YLYDCG/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KGMSLQ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/KGMSLQ/", "attachments": []}, {"guid": "92c166ca-74a5-5fb7-83c0-918b755d02e0", "code": "FWGCHN", "id": 372, "logo": null, "date": "2026-06-11T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-372-apex-accelerating-fft-on-cva6-with-a-tightly-coupled-cv-x-if-co-processor", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FWGCHN/", "title": "APEX: Accelerating FFT on CVA6 with a Tightly Coupled CV-X-IF Co-processor", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The Fast Fourier Transform (FFT) is a fundamental algorithm in embedded and edge signal processing applications, including audio and speech processing, radar systems, and biomedical sensing, where real-time performance must be achieved under strict area and power constraints. Conventional approaches typically rely on dedicated standalone accelerators, but these often impose significant area and power overheads that are impractical for resource-constrained embedded and edge platforms. To address this, tightly-coupled acceleration within the CPU pipeline offers a more efficient alternative by delivering substantial performance gains without requiring an independent hardware block. This paper presents APEX, a tightly-coupled coprocessor integrated with the CV32A6 32-bit RISC-V processor, designed to provide high-performance FFT acceleration for embedded RISC-V systems. For a fixed-point FFT of size N=512, APEX achieves an 83.5% reduction in execution cycles and an 87.9% reduction in instruction count compared to the software FFT implementation on the baseline CV32A6, while preserving the baseline operating frequency and full RV32IM_Zicsr software compatibility with only minimal area overhead. These results demonstrate that APEX is an efficient and practical solution for accelerating FFT-intensive workloads in embedded and edge deployments built on open RISC-V architectures.", "description": "APEX is a hardware/software co-design project targeting FFT acceleration on the CVA6 RISC-V application-class processor. On the hardware side, APEX is a tightly coupled co-processor connected to CVA6 via an enhanced CV-X-IF interface, implementing pipelined radix-2 and radix-4 butterfly units with a dedicated APEX Register File (APR) for wide operand handling in Q1.15 fixed-point arithmetic. On the software side, the KissFFT library serves as the application program, modified to exploit the APEX hardware through custom RISC-V instructions encoded in the reserved custom opcode space. These instructions \u2014 covering butterfly computation (`bfly2`, `bfly4`) and APR load/store configuration (`APEX_CFG`, `APEX_RESTORE`) \u2014 are integrated into the **LLVM compiler toolchain**, enabling the generation of APEX-aware machine code directly from a high-level C FFT application. The full stack spans RTL design of the co-processor, CV-X-IF integration with CVA6, ISA extension and instruction encoding, LLVM backend modifications for custom instruction emission, and application-level profiling on FPGA.", "recording_license": "", "do_not_record": false, "persons": [{"code": "GCUNUF", "name": "Abdul Wadood", "avatar": "https://cfp.riscv-europe.org/media/avatars/GCUNUF_r7uUztI.webp", "biography": "Digital Design Engineer with 3+ years of industry experience in RTL design and verification, specialising in RISC-V CPU architecture, ISA extensions, and hardware accelerators for FPGA and ASIC targets. Passionate about open-source CPU design, computer architecture, and hardware/software co-design. Active contributor to the RISC-V ecosystem, including CVA6, SERV, and RISC-V Architecture Compatibility Test Suites (ACTs).", "public_name": "Abdul Wadood", "guid": "231c915c-362d-5d99-b58d-16e2c92d1d54", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GCUNUF/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FWGCHN/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FWGCHN/", "attachments": []}, {"guid": "db2dd75e-c6bf-5a71-96fc-1bdc24305d89", "code": "H8SWVM", "id": 226, "logo": null, "date": "2026-06-11T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-226-integration-of-cva6-in-esp-for-isa-extensions-and-coherent-multicore-with-fft-butterfly-instruction", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/H8SWVM/", "title": "Integration of CVA6 in ESP for ISA extensions and coherent multicore: with FFT-butterfly instruction", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The RISC-V ecosystem is moving toward increasingly heterogeneous SoCs that combine multicore processors, hardware accelerators, and software programmability. In this work, we integrate the application-class CORE-V CVA6 processor into the open-source ESP framework, enabling ISA extensions within a coherent multicore platform. \r\nThe integration preserves cache coherence, SMP correctness, and Linux-class software support, while providing a practical path to deploying custom instructions in ESP-based systems. To demonstrate the benefits of heterogeneity at the core level, we implement an FFT butterfly extension using a CV-X-IF-based flow with three custom instructions. Across FFT sizes from 16 to 1024 points, the proposed design achieves speedups of 1.37\u00d7 to 1.45\u00d7.\r\nThese improvements are obtained with low hardware overhead, namely +0.23% at the platform level and +5% at the core level. Results show that ISA-level extensions can complement multi-accelerator architectures by providing efficient fine-grained acceleration for recurring DSP kernels.", "description": "Integration of the CVA6 application-class RISC-V core into the ESP heterogeneous SoC framework, enabling coherent multicore execution and CV-X-IF-based ISA extensions. A custom FFT butterfly instruction is used as case study, showing low overhead and consistent speedup across FFT sizes.", "recording_license": "", "do_not_record": false, "persons": [{"code": "7M7Q9G", "name": "rodrigo olmos", "avatar": null, "biography": "Rodrigo Olmos is a researcher in heterogeneous RISC-V SoC design and hardware acceleration at Universidad Polit\u00e9cnica de Madrid (UPM). His work focuses on hardware/software co-design, multicore integration, custom ISA extensions, and FPGA-based prototyping for embedded and high-performance systems.", "public_name": "rodrigo olmos", "guid": "1e51d4cc-5971-5249-8cd9-0a1021134a6d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/7M7Q9G/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/H8SWVM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/H8SWVM/", "attachments": []}, {"guid": "7205313a-f701-53ed-af2c-2e6fa2d56b60", "code": "7TD7TB", "id": 350, "logo": null, "date": "2026-06-11T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-350-an-embedded-risc-v-vector-extension-for-edge-oriented-acceleration", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7TD7TB/", "title": "An Embedded RISC-V Vector Extension for Edge-Oriented Acceleration", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This work details a high-performance Vector Processing Unit (VPU) architecture designed to exploit data-Level Parallelism (DLP) within the strict power and area constraints of embedded environments. Addressing the parallelization needs of data-intensive tasks, the proposed modular architecture implements a subset of the RISC-V Vector (RVV) Zve32x sub-extension, focusing on essential 32-bit integer operations. The VPU is integrated as a co-processor to a CV32E20 core within the eXtendable Heterogeneous Energy-efficient Platform (X-HEEP) ecosystem. It leverages the Core-V eXtension Interface (CV-X-IF) 1.0 for low-latency instruction offloading and the Open Bus Interface (OBI) v1.0 protocol to ensure high-throughput data memory access during load/store operations. The implementation, featuring a Vector Register Length (VLEN) of 128 bits, was validated through Register Transfer Level (RTL) simulation and in hardware using a Xilinx Pynq-Z2 FPGA. Performance was evaluated using standard data-parallel kernels including SAXPY, Indexed Arithmetic, and Matrix Multiplication (Matmul). Additionally, this research investigates the RISC-V GNU Compiler Toolchain, comparing standard C auto-vectorization against manual vectorization using RISC-V Vector C Intrinsics.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "J9GEWF", "name": "I\u00f1igo Diez de Ulzurrun", "avatar": null, "biography": "", "public_name": "I\u00f1igo Diez de Ulzurrun", "guid": "a46bcaad-f53a-5868-8ff5-5e92bd9b8089", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/J9GEWF/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7TD7TB/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/7TD7TB/", "attachments": []}, {"guid": "da399a63-1764-5d3c-8ab0-aa93128410ac", "code": "88TJXG", "id": 132, "logo": null, "date": "2026-06-11T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-132-high-performance-crc-ec-acceleration-for-risc-v-server-storage-via-novel-isa-extensions", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/88TJXG/", "title": "High-Performance CRC/EC Acceleration for RISC-V Server Storage via Novel ISA Extensions", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Data integrity and fault tolerance are prerequisites for RISC-V adoption in enterprise server environments, relying heavily on Cyclic Redundancy Check (CRC) and Erasure Coding (EC) for storage reliability and network transmission. Currently, the RISC-V ISA lacks the dedicated hardware acceleration found in mature architectures such as x86, leading to significant overhead in implementations. We propose novel ISA extensions to bridge this gap: a fused carry-less multiply-add instruction for CRC folding achieving up to 4x speedup, and a specialized GF(2^8) multiply-accumulate instruction for EC delivering 4x throughput gains over vectorized baselines. Evaluation confirms that these extensions significantly enhance data path efficiency, positioning RISC-V as a competitive architecture for reliable, high-performance storage and networking systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "RDKE3Y", "name": "Zhanheng Yang", "avatar": "https://cfp.riscv-europe.org/media/avatars/RDKE3Y_FVE05vS.webp", "biography": "", "public_name": "Zhanheng Yang", "guid": "f65398b1-0aff-5081-8a69-899dea01ac0a", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/RDKE3Y/"}, {"code": "QP89SV", "name": "Fengrui Sun", "avatar": null, "biography": "", "public_name": "Fengrui Sun", "guid": "c337d54e-b151-5ff6-ab42-041a22132cfb", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QP89SV/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/88TJXG/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/88TJXG/", "attachments": []}, {"guid": "d62e1ffc-94ef-5d42-b081-399e8a515c95", "code": "VRKMGE", "id": 327, "logo": null, "date": "2026-06-11T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-327-risc-v-hardware-accelerator-for-2-d-discrete-cosine-transform", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VRKMGE/", "title": "RISC-V Hardware Accelerator for 2-D Discrete Cosine Transform", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The Discrete Cosine Transform (DCT) is a key component in image and video compression systems due to its high energy compaction and efficient implementation. This paper presents a hardware accelerator for the 2-D DCT integrated into RISC-V\u2013based FPGA systems. The design relies on an optimized 8-point 1-D DCT algorithm requiring only 11 multiplications and 29 additions, extended to 2-D using row\u2013column decomposition. The accelerator employs a three-stage pipeline performing row-wise transform, column-wise transform, and quantization. It was integrated with both MicroBlaze V and CVA6 RISC-V cores and implemented on AMD VCU128 and KCU116 FPGA development boards. Experimental results for multiple image resolutions show significant performance improvements compared with the software implementation, achieving speedups of up to 44.56\u00d7 and a throughput of 2 Mpixel/s at 100 MHz. The accelerator uses modest FPGA resources, enabling multiple instances and demonstrating its suitability for accelerating image and video compression pipelines in RISC-V\u2013based systems.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "A3AXVK", "name": "Andrei Stan", "avatar": null, "biography": "", "public_name": "Andrei Stan", "guid": "65e02e2c-735c-5cba-9668-8f9cca093912", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/A3AXVK/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VRKMGE/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/VRKMGE/", "attachments": []}, {"guid": "047f7416-d219-5d9f-899e-f5a0511a1229", "code": "3HRCLU", "id": 48, "logo": null, "date": "2026-06-11T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-48-a-risc-v-accelerator-for-convex-optimisation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3HRCLU/", "title": "A RISC-V Accelerator for Convex Optimisation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "We show how a processor with native extended floating point precision could be incorporated in algebraic subroutines in convex optimisation, namely in indirect matrix inversion methods like Conjugate Gradient, which are used in Interior Point Methods in the case of very large problem sizes. Also, an estimate is provided of the expected acceleration of the time to solution for a hardware running natively on extended precision. Specifically, when using indirect matrix inversion methods like Conjugate Gradient, which have lower complexity than direct methods and are therefore used in very large problems, we see that increasing the internal working precision reduces the time to solution by a factor that increases with the system size.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "FHET9Y", "name": "David Herrera Marti", "avatar": null, "biography": "", "public_name": "David Herrera Marti", "guid": "bdbcf8c0-e1d0-5254-a638-7f1a938fcf33", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FHET9Y/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3HRCLU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3HRCLU/", "attachments": []}, {"guid": "6bcbb678-7dcb-5e95-8edb-4133ecff9c7f", "code": "ZTDS9J", "id": 125, "logo": null, "date": "2026-06-11T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-125-a-fully-integrated-fpga-based-reconfigurable-intelligent-surface-controller-using-an-embedded-risc-v-core", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZTDS9J/", "title": "A Fully Integrated FPGA-Based Reconfigurable Intelligent Surface Controller using an Embedded RISC-V Core", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper presents a compact FPGA-based controller for Reconfigurable Intelligent Surfaces (RIS) that integrates an embedded RISC-V processor and dedicated hardware control within a single device. The proposed architecture targets a 15\u00d715 mechanical RIS prototype driven by stepper motor actuators. The embedded RISC-V processor accesses the RIS controller through a lightweight memory-mapped interface, enabling software-programmable RIS reconfiguration while fully abstracting low-level actuation details. By integrating processing and control within the same FPGA, the proposed platform eliminates the need for external computing units and reduces communication latency.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HFXED8", "name": "Rub\u00e9n Padial-Allu\u00e9", "avatar": null, "biography": "", "public_name": "Rub\u00e9n Padial-Allu\u00e9", "guid": "e62b1b06-fbc5-51cd-905e-74c1bbc05d4d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HFXED8/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZTDS9J/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ZTDS9J/", "attachments": []}, {"guid": "3f39742d-5243-5a1f-8687-b0f7725597e5", "code": "3MEHL7", "id": 116, "logo": null, "date": "2026-06-11T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-116-improving-dsp-performance-in-processors-by-repurposing-existing-multiplier-architectures", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3MEHL7/", "title": "Improving DSP Performance in Processors by Repurposing Existing Multiplier Architectures", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Hearing loss is among the most prevalent sensory impairments worldwide. Hearing aids that incorporate adaptable, personalized signal processing have the potential to improve communication outcomes and social participation for affected individuals. The development and rigorous evaluation of novel hearing-aid algorithms requires high-level programmable, low-power, and portable behind-the-ear (BTE) research platforms that enable studies in real-world environments. The RISC-V open source instruction set architecture (ISA) presents a flexible and configurable baseline for the development of signal processing architectures.\r\nThis paper presents a lightweight single instruction multiple data (SIMD) architecture featuring a complex number extension targeted at embedded applications with a specific focus on the energy efficiency by reusing existing multiplier hardware. Performance data is gathered from a reference Fast Fourier Transform (FFT) implementation, with FFT sizes taken from the field of typical hearing aid applications. Power values are obtained by synthesizing the baseline processor and the extension in a 22 nm FD-SOI technology, followed by a gate-level simulation to obtain accurate switching activity values. The implemented extension achieves a speedup of up to 26 %. A comparison of the energy values through gate-level simulation reveals that the energy consumption of the modified design decreases by 27 % on average.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "9G93MH", "name": "Sven Sch\u00f6newald", "avatar": null, "biography": "Sven Sch\u00f6newald received his B.Sc and M.Sc\r\nin 2017 and 2020, respectively, from the Leib-\r\nniz University of Hannover. He is currently a\r\nresearch associate and Ph.D. candidate at the\r\nInstitute of Microelectronics Systems (IMS) from\r\nthe Leibniz University of Hannover. His research\r\nfocuses on exploring new and efficient archi-\r\ntectures for digital signal-processing tasks. His\r\nmain research interest is in the field of RISC-V\r\nbased processors.", "public_name": "Sven Sch\u00f6newald", "guid": "6c354e0c-4d8b-59de-b27d-9fe9771ea72f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9G93MH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3MEHL7/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/3MEHL7/", "attachments": []}, {"guid": "8585b017-63ff-5348-8648-d789a6d2e009", "code": "MARKW9", "id": 31, "logo": null, "date": "2026-06-11T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-31-fpga-lifecycle-management-for-risc-v-systems", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MARKW9/", "title": "FPGA Lifecycle Management for RISC-V Systems", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "FPGA lifecycle management remains tied to proprietary toolchains and host architectures, leaving RISC-V without a vendor-neutral model for scalable bitstream deployment.\r\nA host-agnostic control-plane architecture is presented that shifts lifecycle management to the operating-system layer by leveraging standard Linux capabilities, thereby decoupling deployment from specific ISAs and vendor stacks. This enables Linux-capable RISC-V processors to serve as control hosts in heterogeneous FPGA systems.\r\nPrototyped on a Zynq-7000 SoC and generalizable to RISC-V platforms, the architecture provides a portable foundation for fleet-scale FPGA management.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "JLYSHY", "name": "Tianhai Liu", "avatar": "https://cfp.riscv-europe.org/media/avatars/JLYSHY_TjJKEUT.webp", "biography": "Dr. Tianhai Liu is a postdoctoral researcher at KIT and a project lead at aicas GmbH. His work focuses on formal methods, consistency analysis, and verification for cyber-physical systems, with applications in automotive software, IoT architectures, and FPGA-cloud integration.", "public_name": "Tianhai Liu", "guid": "b0ece579-d153-5eb1-bec8-886ab04b3d92", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JLYSHY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MARKW9/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MARKW9/", "attachments": []}, {"guid": "3c9bc077-6a7f-59b2-aaa2-a51d777c3b86", "code": "EHJ3MR", "id": 180, "logo": null, "date": "2026-06-11T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island A", "slug": "eu-summit-2026-180-magia-v-a-heterogeneous-zve32d-gemm-tile-for-emerging-mesh-of-tiles-accelerators", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EHJ3MR/", "title": "MAGIA-V: A Heterogeneous Zve32d+GEMM Tile for Emerging Mesh-of-Tiles Accelerators", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "AI and HPC workloads demand scalable, efficient accelerator architectures. We present **MAGIA-V**, an open mesh-of-tiles accelerator template integrating a **RISC-V Zve32d Spatz vector processor** with a **RedMulE tensor engine**, enabling concurrent vector and matrix operations.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CTJKAY", "name": "Luca Balboni", "avatar": "https://cfp.riscv-europe.org/media/avatars/CTJKAY_7OwGuif.webp", "biography": "", "public_name": "Luca Balboni", "guid": "3892e4e7-9b58-5272-9a59-8672e8ff1417", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CTJKAY/"}, {"code": "LMJ9BU", "name": "Alessandro Nadalini", "avatar": null, "biography": null, "public_name": "Alessandro Nadalini", "guid": "a116180b-106e-5be5-ba69-a9b2b25988e7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/LMJ9BU/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EHJ3MR/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EHJ3MR/", "attachments": [{"title": "Extended abstract NON-Blinded", "url": "/media/eu-summit-2026/submissions/EHJ3MR/resources/_RISC_V_Summit_2026__WLizAtS.pdf", "type": "related"}]}], "Poster Island B": [{"guid": "0e1b85e0-ef56-5057-b99f-f8e127514f99", "code": "BSGU8Y", "id": 281, "logo": null, "date": "2026-06-11T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-281-tightly-coupled-near-memory-matrix-unit-for-risc-v-embedded-computing", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BSGU8Y/", "title": "Tightly Coupled Near-Memory Matrix Unit for RISC-V Embedded Computing", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This work presents the design of a tightly coupled near-memory computing unit compatible with a preliminary RISC-V Attached Matrix Extension. The proposed unit is designed to be integrated with a processor core through the Core-V eXtension Interface (CV-X-IF), enabling matrix operations to be decoded and executed directly in a processing unit attached to a system's main memory. Instead of moving data into registers prior to computation, load instructions specify operand locations in main memory. Memory access and near-memory computation are deferred until the execution unit requires the operands. To evaluate the feasibility of the proposed architecture, a model of the unit is designed, implemented, and validated in the gem5 architectural simulator. This model serves as a first step to prove the concept and enables design-space exploration of the architecture. As a preliminary evaluation, a quantized convolutional neural network workload is executed on the simulator to assess the potential performance benefits of the approach, achieving a 47x speed-up with respect to a simulated processor baseline.", "description": "See Abstract.", "recording_license": "", "do_not_record": false, "persons": [{"code": "WLW7EY", "name": "Juan Granja", "avatar": null, "biography": "", "public_name": "Juan Granja", "guid": "80a3e307-f323-58dd-bfff-d002ca452246", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WLW7EY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BSGU8Y/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BSGU8Y/", "attachments": []}, {"guid": "aa0cdd7f-a7a8-5330-a1f1-e2bd76e29120", "code": "WVYG7T", "id": 297, "logo": null, "date": "2026-06-11T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-297-evaluating-the-impact-of-vector-co-processors-on-memory-hierarchies-through-hybrid-simulation", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WVYG7T/", "title": "Evaluating the Impact of Vector Co-Processors on Memory Hierarchies through Hybrid Simulation", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "With the proliferation of data-hungry accelerators and co-processors in embedded system design, co-design of processors and memory systems is becoming more important.  Current simulation techniques for processors rely on oversimplified and inflexible memory models, while techniques for memory system simulation tend to only utilize simple processor models.  In this work, we integrate a cycle-accurate Verilator processor and vector co-processor model with the Gem5 memory simulator in order to evaluate the full impact of a data-hungry co-processor on the memory system and main core performance, and to provide a framework for future co-design of both processor and memory systems.", "description": "This extended abstract introduces a method for Verilator and Gem5 hybrid simulation in order to explore the impact of a integrated co-processor on the memory hierarchy and vice-versa.  The hybrid simulation framework is evaluated through the testing of a simple system with a single level cache hierarchy, main core, and vector co-processor, and compared to the standard evaluation of both the core and co-processor and memory hierarchy separately.", "recording_license": "", "do_not_record": false, "persons": [{"code": "AZZNBC", "name": "J Parker Jones", "avatar": null, "biography": "I am a current PhD student at TUWien.  Interested in embedded system design and vector processing.", "public_name": "J Parker Jones", "guid": "88f35f6a-5dfb-51bd-a2f4-2ee564581f60", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/AZZNBC/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WVYG7T/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WVYG7T/", "attachments": []}, {"guid": "6670bf67-8bc9-5042-87b3-0ac967f003a5", "code": "XYRVET", "id": 139, "logo": null, "date": "2026-06-11T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-139-bicameral-re-assessing-split-vector-and-scalar-cache-designs-for-increased-efficiency", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XYRVET/", "title": "Bicameral+: re-assessing split vector and scalar cache designs for increased efficiency", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper introduces the Bicameral+, an enhanced version of the Bicameral Cache; a vector-aware memory hierarchy that separates vector and scalar accesses into two cache partitions tailored to the needs of each kind of access, improving spatial locality for vectors and eliminating scalar interference. The new design aims to reduce implementation complexity and improve energy efficiency, while retaining the performance improvements of the original proposal, by introducing a set associative design and an alternative opportunistic dirty block management scheme. Experimental results on thirteen benchmarks across various configurations show a 7x area reduction and 18x energy savings, while retaining an average 1.59x speedup w.r.t a conventional cache.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "GKMLCM", "name": "Borja Perez", "avatar": null, "biography": "", "public_name": "Borja Perez", "guid": "8e25c1e7-f0a2-5ab5-8a1e-93143f4d983c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GKMLCM/"}, {"code": "E8FNRH", "name": "Aitor Echevarr\u00eda", "avatar": null, "biography": "", "public_name": "Aitor Echevarr\u00eda", "guid": "dd7eea91-b857-5d8b-b7c6-5486977ec161", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/E8FNRH/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XYRVET/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XYRVET/", "attachments": []}, {"guid": "5d428fa5-950d-5613-9a74-a5dbb25579dd", "code": "FP7AUZ", "id": 366, "logo": null, "date": "2026-06-11T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-366-ame-pim-breaking-the-memory-wall-with-risc-v-matrix-extensions-and-hbm-pim", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FP7AUZ/", "title": "AME-PIM: Breaking the Memory Wall with RISC-V Matrix Extensions and HBM-PIM", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Matrix workloads, essential in generative AI, increasingly rely on ISA-level (i.e. AMX, SME). The attached matrix extension (AME) is one of the three (IME, AME, VME) ISA extensions  under standardization in RISC-V. In common, all these matrix-ISA assumes extensions of the processor datapath with dedicated matrix acceleration hardware. However, executing matrix kernels requires moving large tiles between memory and processor registers, making performance limited by memory bandwidth.\r\nWe investigate whether High Bandwidth Memory with Processing-in-Memory (HBM--PIM) can serve as alternative implementation of AME instructions. We propose a PIM Execution Primitive (PEP) computational model mapping AME ISA onto Samsung Aquabolt-XL HBM-PIM microkernels, using an outer-product dataflow to enable in-memory accumulation, as well as remapping AME tile registers into memory regions\u2014making possible to chain AME instructions without leaving the memory.\r\nOur experiments show AME tile multiplication reaching 14.9 GFLOP/s (59.4 FLOP/cycle) on a HBM--PIM pseudo-channel, demonstrating that HBM--PIM can serve as an implementation of RISC-V matrix extensions.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "HKYAWD", "name": "Emanuele Venieri", "avatar": null, "biography": "", "public_name": "Emanuele Venieri", "guid": "cd561a43-be92-50bf-a13c-f21b6ad66576", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/HKYAWD/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FP7AUZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/FP7AUZ/", "attachments": []}, {"guid": "e3d520a8-b4e3-53bc-b7b0-8b53f49e74bd", "code": "ADHZLM", "id": 347, "logo": null, "date": "2026-06-11T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-347-revisiting-transputers-with-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ADHZLM/", "title": "Revisiting Transputers with RISC-V", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The transputer is a famous High Performance Computing (HPC) architecture from the late 1980s/early 1990s, with Inmos being arguably the most famous example. Embodying a communication-centric, distributed-memory MIMD architecture designed explicitly for scalable parallel process networks, there are numerous potential efficiency advantages to this approach. In a world where scientific programmers are ever demanding more performance, but having to balance this with energy efficiency, this approach is worth another look. The Esperanto ET-SoC-1 was a 1,088-core RISC-V manycore accelerator organised around a mesh network-on-chip (NoC) with hierarchical cache and scratchpad memory structures. Purchased and released by the AI foundry who are focussed on open source, they are emphasising the transputer credentials of the architecture. In this abstract and associated poster we provide and independent exploration around how parallel code written for a T800 transputer array may be systematically mirrored onto the ET-SoC-1 compute fabric. We identify architectural similarities and highlight key divergences.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "39EF9C", "name": "Rich Neale", "avatar": null, "biography": "", "public_name": "Rich Neale", "guid": "f75c63cb-288d-5064-b17f-44394ea9b227", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/39EF9C/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ADHZLM/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ADHZLM/", "attachments": []}, {"guid": "57e5d921-34bc-5c0d-8750-3a89b6776d70", "code": "W3ANF8", "id": 340, "logo": null, "date": "2026-06-11T13:00:00+02:00", "start": "13:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-340-profiling-and-optimizing-ame-for-matrix-multiplication", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/W3ANF8/", "title": "Profiling and Optimizing AME for Matrix Multiplication", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The RISC-V ecosystem is evolving toward AI-oriented computing, with matrix-oriented proposal directions such as AME, VME, and IME attracting increasing attention. In LLM inference, matrix multiplication constitutes one of the dominant computation patterns, and quantized matrix multiplication is widely adopted by many accelerators to improve efficiency. In this setting, the practical value of matrix-oriented proposals depends not only on the instruction capabilities they provide, but also on how effectively representative operators can be mapped onto realistic execution flows. This work presents an operator-level profiling study of a currently discussed AME proposal for RISC-V AI. We first design representative matrix operators for quantized LLM-style workloads, then develop a gem5-based platform with support for the AME proposal, and profile matrix multiplication on this platform. Based on these observations, we further analyze scaled matrix multiplication as an extended operator flow and discuss a possible scaled matrix multiplication instruction strategy as a future optimization direction.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "DCQFDS", "name": "Xinlei Zhao", "avatar": "https://cfp.riscv-europe.org/media/avatars/DCQFDS_aCPxbig.webp", "biography": "", "public_name": "Xinlei Zhao", "guid": "ac472fee-685e-5b02-8c8f-ecfabced8895", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DCQFDS/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/W3ANF8/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/W3ANF8/", "attachments": []}, {"guid": "07ecd4e3-0cce-5c99-be05-3d3d25dd891f", "code": "U38PRX", "id": 71, "logo": null, "date": "2026-06-11T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-71-a-holistic-approach-to-attached-matrix-extension-on-risc-v-from-isa-to-software-stack", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/U38PRX/", "title": "A Holistic Approach to Attached Matrix Extension on RISC-V From ISA to Software Stack", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The increasing computational demands of modern AI workloads necessitate a holistic architectural approach to AI acceleration on RISC-V processors. This talk presents the XuanTie Tensor Processing Engine (TPE), a RISC-V-based Attached Matrix Extension (AME) engine designed to address AI acceleration across three dimensions: ISA, microarchitecture, and software ecosystem.\r\nAt the ISA level, the TPE adopts the in-progress RISC-V AME specification, featuring dedicated tensor registers and a comprehensive instruction set encompassing matrix multiply-accumulate, element-wise, special function, reduction, and load/store operations with broad data type support including INT4, FP8, FP16, and micro-scaling formats. \r\nAt the microarchitecture level, the design incorporates a matrix engine achieving 2 TOPS/GHz at INT8/FP8, a concurrent vector engine with hardware-accelerated non-linear functions, and a layered memory subsystem featuring a coherent tensor cache and data prefetch engine. \r\nA full-stack software ecosystem spanning LLVM toolchain to graph execution runtime completes the solution.\r\nExperimental results on the XuanTie C930 cluster demonstrate 99% FP16 GEMM utilization. We discuss key design trade-offs and implications for the evolving RISC-V AME standard.", "description": "The XuanTie TPE demonstrates a production-grade, RISC-V-native Attached Matrix Extension approach to AI acceleration that is both performant and practical. Through this work, we aim to contribute to the RISC-V community in several important ways:\r\n\u2022\tDriving Community-Driven Standardization of AME: Our implementation is closely aligned with the RISC-V AME TG's ongoing AME specification efforts. By sharing our design choices, the trade-offs we encountered, and the real-world workload requirements that shaped our ISA decisions, we hope to provide valuable feedback to the standardization process. We believe that practical, silicon-validated implementations are essential for grounding specification discussions in engineering reality.\r\n\u2022\tHighlighting the Unique Advantages of RISC-V for AI Extension: The openness and modularity of RISC-V make it uniquely suited for domain-specific acceleration. Unlike proprietary ISAs where AI extensions must fit within rigid architectural constraints, RISC-V allows the community to co-evolve the ISA, microarchitecture, and software stack together. The TPE is a concrete example of this co-design philosophy \u2014 the AME ISA, the hardware engines, and the software ecosystem were developed in concert, each informing and refining the others.", "recording_license": "", "do_not_record": false, "persons": [{"code": "DSVPCE", "name": "Qiu Jing", "avatar": "https://cfp.riscv-europe.org/media/avatars/DSVPCE_VJpaZzQ.webp", "biography": "Qiu Jing is a CPU design engineer at Alibaba DAMO Academy, where he has been involved in the design of multiple XuanTie RISC-V processors. He served as the Acting Chair during the inception phase of the RISC-V AME (Attached Matrix Extension) Task Group, and has been actively contributing to the TG's discussions since its establishment. His work focuses on bridging the gap between AI workload requirements and RISC-V ISA design, with particular emphasis on vector/matrix extension architecture and its hardware implementation.", "public_name": "Qiu Jing", "guid": "969dabdc-fe49-5a45-bbbf-27899aca6e7a", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/DSVPCE/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/U38PRX/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/U38PRX/", "attachments": []}, {"guid": "0c316574-0c78-5320-b10c-3ac6a9f157d8", "code": "A8BV3C", "id": 93, "logo": null, "date": "2026-06-11T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-93-architectural-scalability-trade-offs-in-an-risc-v-vector-processor-for-communication-kernels", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A8BV3C/", "title": "Architectural Scalability Trade-Offs in an RISC-V Vector Processor for Communication Kernels", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Communication baseband workloads such as covariance estimation, synchronization and reduction operations exhibit substantial data-level parallelism. The RISC-V Vector Extension (RVV) introduces vector-length agnostic (VLA) execution, enabling scalable vector implementations independent of a fixed hardware width. In this work, we explore architectural scalability trade-offs of a configurable RVV-based vector processor across VLEN, lane count, and lane width. Using representative communication kernels and synthesis with the predictive ASAP7 PDK, we analyze architectural scaling behavior and the interaction between cycle reduction and frequency degradation. While increasing VLEN reduces cycle counts, critical-path growth and bandwidth imbalance introduce a parallelism\u2013frequency trade-off that yields kernel-dependent optimal configurations. We further demonstrate how a lightweight custom vector complex multiplication instruction improves efficiency for covariance-based workloads. The results highlight the importance of balanced compute\u2013memory design for practical and physically realizable RVV implementations.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "GYH89J", "name": "Keivan Fayyazifard", "avatar": null, "biography": "", "public_name": "Keivan Fayyazifard", "guid": "7773ee72-3eab-5a07-9a09-33e3c0d466b6", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GYH89J/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A8BV3C/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/A8BV3C/", "attachments": []}, {"guid": "51b8715a-0622-50b3-99d7-50ac0c3cee77", "code": "RTYDA8", "id": 264, "logo": null, "date": "2026-06-11T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-264-risc-v-instruction-subset-processors-for-extreme-edge-machine-learning", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RTYDA8/", "title": "RISC-V Instruction-Subset Processors for Extreme Edge Machine Learning.", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "We present an end-to-end framework for the automatic generation of custom RISC-V instruction-subset processors (RISSPs) tailored to machine learning (ML) inference. Building on the RISSP methodology, our fully automated flow accepts model hyperparameters and a target dataset, performs offline training, and generates the complete inference implementation together with all deployment artifacts for the target device. The resulting inference code then drives the RISSP generation, synthesising a custom processor that implements only the RISC-V instructions used by the application. By co-optimizing software and hardware within a tightly integrated co-design toolchain, the combined flow reduces ISA footprint and design complexity, enabling smaller and more energy-efficient processors for ML workloads at the edge.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "S9PYXN", "name": "Konstantinos Iordanou", "avatar": null, "biography": "", "public_name": "Konstantinos Iordanou", "guid": "235e399a-e6dd-5300-ae72-c56ea113a058", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/S9PYXN/"}, {"code": "FPM9DD", "name": "Shengyu Duan", "avatar": null, "biography": null, "public_name": "Shengyu Duan", "guid": "05f62a69-9c54-5d01-a693-d0951a911bac", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FPM9DD/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RTYDA8/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/RTYDA8/", "attachments": []}, {"guid": "29c9099a-537c-5e97-8f1a-e1421843b8c5", "code": "9PWJCZ", "id": 276, "logo": null, "date": "2026-06-11T13:40:00+02:00", "start": "13:40", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-276-energy-efficient-risc-v-based-neuromorphic-soc-for-edge-ai-applications", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9PWJCZ/", "title": "Energy-Efficient RISC-V based neuromorphic SoC for Edge AI Applications", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Spiking Neural Networks (SNNs) offer significant energy efficiency for Edge AI, yet their event-driven nature leads to unpredictable, variable-length output data. In traditional heterogeneous SoCs, this unpredictability causes high CPU overhead and bus inefficiency. This paper presents a specialized Event-Adaptive DMA (EA-DMA) integrated into a RISC-V based SoC. Unlike standard DMAs, the proposed engine performs buffer-triggered, variable-length transfers with maximum-size clamping and hardware backpressure for irregular SNN spike traffic. This work provides a scalable solution for integrating neuromorphic accelerators into the RISC-V ecosystem.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "3SZGEW", "name": "wenfei", "avatar": "https://cfp.riscv-europe.org/media/avatars/3SZGEW_2JrR69j.webp", "biography": "PhD student at the LEAT laboratory (Laboratoire d'\u00c9lectronique, Antennes et T\u00e9l\u00e9communications), Universit\u00e9 C\u00f4te d'Azur, France. Research focuses on neuromorphic computing, specifically the design and optimization of energy-efficient hardware accelerators for Spiking Neural Networks (SNNs).", "public_name": "wenfei", "guid": "733487ab-e223-54eb-b1e7-8c30206cef74", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3SZGEW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9PWJCZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9PWJCZ/", "attachments": []}, {"guid": "3fda0a49-790c-59c0-a335-54d80283242d", "code": "EZY7K8", "id": 162, "logo": null, "date": "2026-06-11T13:50:00+02:00", "start": "13:50", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-162-co-optimizing-custom-instructions-risc-v-and-llm-specialized-accelerator-for-attention-based-edge-ai", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EZY7K8/", "title": "Co-optimizing Custom Instructions RISC-V and LLM Specialized Accelerator for Attention-Based Edge AI", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This work presents a co-optimized architecture for edge-based Transformers, focusing on a specialized RISC-V CPU designed to manage a parallel AI co-processor. While the BumBleBee (BBB) unit handles core Flash Attention Method (FAM) computations, the system relies on an adaptable RISC-V core for critical data orchestration and pre-processing. To overcome the bottlenecks of a memory-bound system, the CPU's ISA is enhanced with custom fused instructions\u2014convcat, lwincr, and swincr\u2014which consolidate complex macro-operations into single-cycle actions. Notably, the convcat instruction reduces 13 F-extension instructions to one, cutting latency by over 50%. Furthermore, the CPU incorporates M and F extensions with data-gating in the ALU to minimize power consumption during scaling and normalization tasks. By prioritizing CPU-level adaptability and instruction fusion, the architecture significantly reduces the energy bill and latency required for high-performance LLM inference in power-constrained environments.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "JQQEX3", "name": "Joaquin Cornejo", "avatar": "https://cfp.riscv-europe.org/media/avatars/JQQEX3_T6b4jcn.webp", "biography": "Currently pursuing a PhD in Microelectronics with a focus on digital circuits for edge AI. I work on digital hardware for edge implementations of Transformer models (aka LLMs), with a particular emphasis on attention mechanisms\u2014especially dot-product attention\u2014and on the design of ASICs that implement this computation with optimized power and performance.  A goal-oriented and curious engineer, committed to continuous learning and collaboration.", "public_name": "Joaquin Cornejo", "guid": "0a6f8131-8486-533f-8498-d446a505d06f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JQQEX3/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EZY7K8/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EZY7K8/", "attachments": []}, {"guid": "19d856de-cb73-5bde-beb9-b493c012e240", "code": "PSCKCE", "id": 188, "logo": null, "date": "2026-06-11T14:00:00+02:00", "start": "14:00", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-188-an-open-heterogeneous-risc-v-ai-acceleration-architecture-for-next-generation-space-computers", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PSCKCE/", "title": "An Open Heterogeneous RISC-V AI Acceleration Architecture for Next-Generation Space Computers", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Integrating AI onboard satellites to reduce dependence on ground stations and facilitate quick orbital maneuvers demands a new class of onboard computers with enhanced processing power, real-time control capabilities, and robustness against the harsh space environment.\r\nAstral is a fully open-source, highly parametric platform for RISC-V-based heterogeneous SoCs targeting reliable  onboard control and AI acceleration for next-generation space computers.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "XSZWUJ", "name": "Yvan Tortorella", "avatar": "https://cfp.riscv-europe.org/media/avatars/XSZWUJ_YpfOgjN.webp", "biography": "Yvan Tortorella received the Ph.D. degree from the University of Bologna, Italy, in 2025, with a dissertation on RISC-V-based heterogeneous computing platforms for reliable space computing. He is currently with Fondazione Chips-IT, where he is a postdoctoral researcher and digital IC designer working on mixed-criticality space processors and AI accelerators.", "public_name": "Yvan Tortorella", "guid": "cd20b4e4-5127-58ea-bb80-720e5769fa15", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/XSZWUJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PSCKCE/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/PSCKCE/", "attachments": []}, {"guid": "7b1e5b23-dc3a-5d91-a0b3-95c256575274", "code": "V33F9K", "id": 120, "logo": null, "date": "2026-06-11T14:10:00+02:00", "start": "14:10", "duration": "00:10", "room": "Poster Island B", "slug": "eu-summit-2026-120-exploring-ai-acceleration-paradigms-for-automotive-risc-v-platforms", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/V33F9K/", "title": "Exploring AI Acceleration Paradigms for Automotive RISC-V Platforms", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The transition toward centralized automotive computing platforms demands scalable, high-performance, and energy-efficient AI acceleration tightly integrated with open instruction set architectures. Within the European Chips Joint Undertaking framework, the [PROJECT NAME] project develops a next-generation automotive hardware platform based on RISC-V technology.\r\nThis paper explores three hardware acceleration paradigms applicable to RISC-V-based automotive systems: (i) memory-mapped monolithic accelerators, (ii) custom ISA extensions tightly coupled to the processor pipeline, and (iii) Near-Memory Computing (NMC) architectures. We present an ongoing comparative study evaluating their applicability to representative automotive AI kernels, including conventional neural networks (CNNs, MLPs), data-driven battery models, and emerging Spiking Neural Networks (SNNs).\r\nWhile all paradigms provide workload-dependent performance benefits, preliminary architectural analysis suggests that Near-Memory Computing offers superior scalability and energy efficiency for memory-bound AI workloads. Complementing the hardware effort, we develop a software ecosystem leveraging MLIR-based compilation flows to efficiently map both conventional and neuromorphic models onto heterogeneous RISC-V accelerators.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "RUE8KK", "name": "DAVID ALBACETE SEGURA", "avatar": null, "biography": "", "public_name": "DAVID ALBACETE SEGURA", "guid": "abc9e568-34d6-5fa0-b2b3-9888b29bd945", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/RUE8KK/"}, {"code": "SKNQVC", "name": "Anestis Athanasiadis", "avatar": null, "biography": "", "public_name": "Anestis Athanasiadis", "guid": "7ebec18a-9ca1-5023-9d9d-ddbf676799ad", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/SKNQVC/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/V33F9K/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/V33F9K/", "attachments": [{"title": "Poster for the session", "url": "/media/eu-summit-2026/submissions/V33F9K/resources/automotive_riscV_pla_0Ravinr.pdf", "type": "related"}]}], "Poster Island C": [{"guid": "e5211ed1-10ec-521a-83e2-a5463d454e4f", "code": "YCVWTV", "id": 328, "logo": null, "date": "2026-06-11T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-328-towards-a-modern-packed-simd-architecture-for-risc-v-learning-from-production-of-et-simd", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YCVWTV/", "title": "Towards a Modern Packed SIMD Architecture for RISC-V: Learning from Production Of ET-SIMD", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The RISC-V Vector Extension (RVV) adopts a vector-length agnostic (VLA) model for exploiting data-level parallelism. We argue that this abstraction imposes significant costs in real silicon: control logic complexity, implicit state tracking in out-of-order pipelines, and runtime overhead that erode VLA\u2019s theoretical portability benefits. Drawing on production experience with the ET-SoC-1, a 1088-core\r\nRISC-V processor, we present ET-SIMD, a fixed-width 256-bit packed SIMD extension that overlays the standard F extension register file. In Flynn\u2019s Taxonomy [2], ET-SIMD is a classical SIMD design: scalar and packed instructions share the same register file, a pattern well understood by GCC and LLVM autovectorizers and proven on competing ISAs, yet absent from RISC-V. We describe the  extension\u2019s architectural rationale, its relationship to contemporary packed SIMD practice, and its availability through the AI Foundry initiative.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BMKL7C", "name": "FelixCLC", "avatar": null, "biography": "Perf & ASM nerd, practical troublemaker\r\nCare about clean specs, clean mandates, HPC, IEEE754 & the BLAS.", "public_name": "FelixCLC", "guid": "40948bbd-3cc3-5e5a-bcef-0c04253f94c2", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BMKL7C/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YCVWTV/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/YCVWTV/", "attachments": []}, {"guid": "054a30d1-463e-5634-8c77-7443de450f3e", "code": "S3LMTB", "id": 315, "logo": null, "date": "2026-06-11T10:40:00+02:00", "start": "10:40", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-315-risc-v-packed-simd-acceleration-for-quantized-edge-ai-inference-on-space-qualified-platforms", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/S3LMTB/", "title": "RISC-V Packed-SIMD Acceleration for Quantized Edge-AI Inference on Space-Qualified Platforms", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Conservative/qualification-sensitive RISC-V ecosystems tend to view large architectural changes as costly due to hardware overhead, integration effort, software/toolchain adaptation, and assurance scope. This is especially relevant for platforms intended for harsh environments and long lifetimes such as space-oriented and radiation-tolerant platforms (e.g., NOEL-V). At the same time, there is growing interest in on-board processing to support time-critical decisions close to the sensor and reduce reliance on transmitting raw sensor data, increasing the demand for compute-intensive Edge-AI inference. In such settings, full vector architectures can deliver high throughput, but they tend to introduce additional architectural state and increase integration complexity across the hardware and software stack. Therefore, to introduce data-parallel acceleration with minimal disruption, we evaluate packed-SIMD as a small-change alternative based on packed subword parallelism that remains close to the existing register and memory model.\r\nWe consider two packed-SIMD options: SWAR and SPARROW. On a NOEL-V softcore, we implement SWAR operator kernels for the most computationally expensive layers and integrate them into the math backend of a space prequalified inference engine, running on a space prequalified RTOS (RTEMS6 SMP). Using a hardware SWAR unit for packed subword operations, we report full-model results with and without SWAR acceleration, showing improved inference performance without requiring a full vector architecture. Finally, we outline future work extending the same backend methodology to SPARROW to compare performance across packed-SIMD options.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "QUKSFK", "name": "Carlos Rafael Tordoya Taquichiri", "avatar": "https://cfp.riscv-europe.org/media/avatars/QUKSFK_fQY574r.webp", "biography": "Rafael Tordoya is a Research Associate at the Zurich University of Applied Sciences (ZHAW) in the fields of Artificial Intelligence (AI) and Embedded Systems. His research focuses on leveraging AI in resource-constrained environments, with particular emphasis on optimized AI inference, mathematical backends, and leveraging available hardware capabilities to enhance inference performance in embedded systems.", "public_name": "Carlos Rafael Tordoya Taquichiri", "guid": "5a41ad79-d581-5b44-a8ef-ef23bddaefb2", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QUKSFK/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/S3LMTB/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/S3LMTB/", "attachments": []}, {"guid": "d9ff8c1b-9a67-5bb1-8cd6-939c53e0280e", "code": "9MT9QK", "id": 240, "logo": null, "date": "2026-06-11T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-240-custom-risc-v-simd-matrix-extensions-with-llvm-support", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9MT9QK/", "title": "Custom RISC\u2011V SIMD Matrix Extensions with LLVM Support", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "The development of our tightly coupled SIMD/Vector accelerator for matrix operations requires extending the RISC-V instruction set. Special compiler support is required for this extension. Our methodology starts from a Sail description of the ISA extension and generates the compiler target description data. The instructions are described in Sail and are tested in the generated simulator. The compiler is generated from the description model and is tested with the accelerator implemented in hardware. The experimental results suggest that for matrix multiplication we obtained speed-ups up to 1413x compared to an ARM A72 core.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "WSLUBK", "name": "Alexandru Puscasu", "avatar": null, "biography": "", "public_name": "Alexandru Puscasu", "guid": "d260d174-3f59-5547-989e-a811584fa8a9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/WSLUBK/"}, {"code": "BPAW73", "name": "Catalin Ciobanu", "avatar": "https://cfp.riscv-europe.org/media/avatars/BPAW73_6RQwdXo.webp", "biography": "Catalin Ciobanu has a MSc and PhD from Delft University of Technology, The Netherlands. He is currently Associate Professor at Transilvania University of Brasov, Romania and Senior Researcher at the National Institute for Research and Development in Microtechnologies - IMT Bucharest, Romania. His research interests include RISC-V processors, embedded systems, high performance computing, SIMD architectures, digital signal processing and reconfigurable hardware.", "public_name": "Catalin Ciobanu", "guid": "68259c63-446a-5c73-a5f0-ad83f7f223a1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BPAW73/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9MT9QK/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/9MT9QK/", "attachments": []}, {"guid": "90c428f3-86c8-58ac-bc7d-93cd330a95ae", "code": "QBSVKB", "id": 265, "logo": null, "date": "2026-06-11T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-265-accelerating-neural-networks-using-simd-isa-extension-for-risc-v-processor-platforms-a-complete-toolflow", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QBSVKB/", "title": "Accelerating neural networks using SIMD ISA-Extension for RISC-V processor platforms: A complete toolflow", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "Our contribution demonstrates how developers can easily run neural networks on RISC-V processors using our custom hardware accelerator TetraEdge.\r\nWe present a complete solution combining three components.\r\n\r\nFirst, we introduce TetraEdge, a custom hardware SIMD accelerator.\r\nTetraEdge contains a four-stage pipeline design to accelerate 8-bit quantized CNNs inference on 32-bit RISC-V processors.\r\nIn comparison to other hardware accelerators, TetraEdge features an innovative automatic data reordering and min/max accumulation.\r\n\r\nSecond, we extend the NeoRV32 open-source RISC-V processor,\r\nby two custom instructions to control TetraEdge without blocking the main processor.\r\nThe CPU continues other tasks while the accelerator handles neural network operations.\r\nBy directly interfacing with the CPU core's register file, TetraEdge minimizes area\r\nand control complexity, enabling seamless integration into existing toolchains.\r\n\r\nFinally, we combine both aforementioned contributions to the open-source framework AIfES (Artificial Intelligence for Embedded Systems).\r\nAIfES is specifically designed to train and run neural networks directly on resource-constrained devices.\r\nIts modular software architecture enables the integration of user-specific hardware accelerators, such as TetraEdge.\r\nAIfES reduces software overhead significantly with up to 54\\% less memory usage and faster execution for CNNs.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "H78NQR", "name": "Alexander Zapp", "avatar": null, "biography": "", "public_name": "Alexander Zapp", "guid": "3372058c-371b-5f5d-8789-6dd25b58ca91", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/H78NQR/"}, {"code": "MUGFSW", "name": "Carsten Rolfes", "avatar": null, "biography": "", "public_name": "Carsten Rolfes", "guid": "c5957833-0305-52a9-8774-c896f04fb5a7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MUGFSW/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QBSVKB/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QBSVKB/", "attachments": []}, {"guid": "8068ce22-9e23-53e2-8069-d59d40203c69", "code": "BXQ73A", "id": 33, "logo": null, "date": "2026-06-11T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-33-starbug-risc-v-hint-instructions-for-lightweight-vliw-execution-on-embedded-dsp-workloads", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BXQ73A/", "title": "STARBUG: RISC-V Hint Instructions for Lightweight VLIW Execution on Embedded DSP Workloads", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This paper presents a standards-aligned microarchitectural extension that leverages architecturally reserved RISC-V HINT encodings to enable lightweight Very Long Instruction Word (VLIW) execution while preserving full backward binary compatibility. Unlike conventional superscalar designs that rely on dynamic scheduling, speculative issue, and complex hazard detection, our approach encodes static scheduling decisions in HINT instructions that execute as NOPs on unmodified cores. Modified implementations interpret these hints to form statically scheduled issue bundles, achieving higher Instruction-Level Parallelism (ILP) without increasing ISA surface area or compromising compliance.\r\n\r\nWe validate the proposal through a full-stack methodology spanning ISA modeling, RTL implementation, and FPGA deployment. ISA semantics were prototyped using Google\u2019s MPACT simulator to evaluate bundle formation and decode behavior. We then extended the OpenHW Group CVW (Wally) core to support 4-wide integer VLIW execution via a widened multi-ported register file and parallel datapaths. The design was verified in Questa and Verilator and synthesized for FPGA-based cycle-accurate measurement.\r\n\r\nEvaluation on representative DSP kernels (FFT, FIR, IIR, and dot product) demonstrates substantial IPC and cycle-count improvements relative to scalar RV32I execution, while maintaining binary compatibility and toolchain transparency. The proposed mechanism provides a path for energy-efficient ILP extraction in embedded and domain-specific systems, illustrating how reserved ISA space can be systematically exploited to deliver microarchitectural innovation without ecosystem fragmentation.", "description": "The pursuit of high Instruction-Level Parallelism (ILP) at lower power has renewed interest in Very Long Instruction Word (VLIW) architectures. Yet, conventional VLIW designs often face challenges such as code density and lack of binary compatibility. This paper introduces a novel hint-based VLIW implementation built on the RISC-V Instruction Set Architecture (ISA). Our proposal utilizes architecturally reserved HINT instructions to encode static scheduling decisions, enabling parallel execution without the need for complex hazard detection hardware.", "recording_license": "", "do_not_record": false, "persons": [{"code": "JJFUJU", "name": "Leo Marek", "avatar": null, "biography": "BS/MS Student from Rice University. Background in computer architecture and hardware infrastructure.", "public_name": "Leo Marek", "guid": "f9310eaf-2836-50f2-bc89-bd711e8cfaf1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/JJFUJU/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BXQ73A/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/BXQ73A/", "attachments": []}, {"guid": "681971ca-72bf-5869-9354-95b521ea1e61", "code": "WKS77D", "id": 166, "logo": null, "date": "2026-06-11T11:20:00+02:00", "start": "11:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-166-hardware-support-in-risc-v-for-ternary-llms", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WKS77D/", "title": "Hardware support in RISC-V for ternary LLMs", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "Language models are becoming increasingly common, and their number of parameters is continuously increasing, imposing huge memory capacities. One of the most common techniques to reduce their memory footprint is weight quantization. Ternary models are one of the most extreme cases of quantization. So far, most hardware proposals focus on FPGA-based accelerators to optimize inference in quantized models, while current general-purpose processors have limited support (up to 8-bit integers). In this work we attempt a preliminary analysis of the potential benefits of moving the quantization hardware support directly to the processor. To do so, we make use of a state-of-the-art inference framework for CPUs and Small Language Models, evaluating what the competitive advantages of having dedicated SIMD hardware for quantized operations. The results show a speedup x2 (tokens/s) on a 350MB Small Language Model with a tendency to increase the speedup with the model size, using a minimal increase of the hardware resources (1.25% in LUTs).", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "GC7XBG", "name": "David Aledo", "avatar": null, "biography": "", "public_name": "David Aledo", "guid": "f16eb3ad-0bbe-5443-8f93-bc53a1948e5a", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GC7XBG/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WKS77D/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/WKS77D/", "attachments": []}, {"guid": "279843e7-108c-5cd2-9a1f-8d61a6aed37b", "code": "ELYZEY", "id": 251, "logo": null, "date": "2026-06-11T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-251-towards-efficient-utilization-of-risc-v-long-vector-register-files-a-characterization-study", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ELYZEY/", "title": "Towards Efficient Utilization of RISC-V Long Vector Register Files: A Characterization Study", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "As RISC-V \"Vector\" (RVV 1.0) architectures scale, the Vector Register File (VRF) becomes a primary bottleneck in area and power. This work characterizes data residency and redundancy patterns in a distributed, long-vector VRF using the gem5 simulator. We identify two primary inefficiencies: resource fragmentation and an entropy-capacity mismatch in active data. Our evaluation of lightweight compression schemes reveals that a 2-entry dictionary-based approach consistently yields a 2.5x compression ratio of the computed vector elements. These results demonstrate that hardware-level data compaction is an interesting path for optimizing the area of future long-vector RISC-V accelerators", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "E8UAFR", "name": "\u00c1lvaro Moreno", "avatar": null, "biography": "Computer Architecture Researcher at Barcelona Supercomputing Center & PHD student at Universitat Polit\u00e8cnica de Catalunya.", "public_name": "\u00c1lvaro Moreno", "guid": "13151605-56c4-5a6a-98a0-35b33289c9ef", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/E8UAFR/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ELYZEY/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/ELYZEY/", "attachments": [{"title": "Poster Submission", "url": "/media/eu-summit-2026/submissions/ELYZEY/resources/PosterExample_TYoApcI.pdf", "type": "related"}]}, {"guid": "d0905969-bc0f-5df5-a1a5-519a13663bbd", "code": "QM3SVB", "id": 83, "logo": null, "date": "2026-06-11T13:20:00+02:00", "start": "13:20", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-83-an-open-source-framework-to-enable-float16-on-device-training-on-risc-v-single-core", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QM3SVB/", "title": "An Open-Source Framework to Enable Float16 On-Device Training on RISC-V Single-Core", "subtitle": "", "track": "Blind Submission (Default)", "type": "Poster", "language": "en", "abstract": "This work proposes an open-source framework that leverages both the Zfh (scalar float16) and the Zvfh (vector float16) extensions to enable complete on-device training on resource-constrained RISC-V single-core. On top of reducing the memory footprint by about 50% as compared to using float32, our approach facilitates transfer learning and fine-tuning scenarios by incorporating layer-freezing capabilities. Our work builds onto AIfES an open-source, modular and generic DNN training and inference framework for embedded systems that can be extended with custom hardware-specific functions.", "description": "Various approaches have been proposed in recent years to mitigate the compute and memory extensiveness of On-Device Training (ODT) of Deep Neural Networks, but these approaches struggle to support full-fledged training or the use of a batch size greater than 1. These limitations primarily stem from the design of hybrid methods, which employ quantized operations for the forward pass while reverting to float32 for the computationally expensive backward pass, ultimately leading to significant learning instability. RISC-V offers the scalar float16 extension Zfh and its vector counterpart Zvfh, which stand as promising candidates to meet the full ODT requirements: lower memory footprint than float32 and SIMD execution from Zvfh. Although existing open-source RISC-V frameworks offer full scalar float16 ODT capabilities, it is specific to multi-core platforms. To address the lack of open-source ODT frameworks optimized for RISC-V single-core supporting Zfh and/or Zvfh, we propose an easy-to-use open-source library which allows PyTorch/Tensorflow models to be deployed and fully trained on RISC-V single-core featuring Zfh/Zvfh support.", "recording_license": "", "do_not_record": false, "persons": [{"code": "U3BGSJ", "name": "Benjamin Hubinet", "avatar": "https://cfp.riscv-europe.org/media/avatars/U3BGSJ_wpT7hwd.webp", "biography": "PhD student in machine learning security at CEA-Leti.", "public_name": "Benjamin Hubinet", "guid": "9f956640-4858-5803-a965-f8c41bea1314", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/U3BGSJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QM3SVB/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QM3SVB/", "attachments": [{"title": "[Poster] An Open-Source Framework to Enable Float16 On-Device Training on RISC-V Single-Core", "url": "/media/eu-summit-2026/submissions/QM3SVB/resources/2026-RISCV_SUMMIT_PO_T9oyhy5.pdf", "type": "related"}, {"title": "[Abstract] An Open-Source Framework to Enable Float16 On-Device Training on RISC-V Single-Core", "url": "/media/eu-summit-2026/submissions/QM3SVB/resources/2026-RISCV_SUMMIT_AB_X92j25L.pdf", "type": "related"}]}, {"guid": "c47ed2a1-d400-5940-baf8-ea7396a43139", "code": "MYRD9A", "id": 234, "logo": null, "date": "2026-06-11T13:30:00+02:00", "start": "13:30", "duration": "00:10", "room": "Poster Island C", "slug": "eu-summit-2026-234-optimizing-iree-compilation-and-end-to-end-object-detection-pipeline-for-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MYRD9A/", "title": "Optimizing IREE Compilation and End-to-End Object Detection Pipeline for RISC-V", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "This work enables optimized, end-to-end inference of the object detection models on RISC-V vector CPU. It includes the implementation of optimized pre- and post-processing pipelines as well as the enablement of efficient execution of the models at FP32, FP16, and INT8 precisions. IREE, an MLIR-based compiler, is used to compile and optimize the model. Model inference on the Banana Pi BPI-F3 is profiled to identify top hotspot ops and their compilation is optimized in the IREE compilation pipeline either by improving vectorization or by implementing ukernels. For accuracy validation, the mean Average Precision (mAP) is computed using the COCO validation dataset. This project is supported by the RISC-V Software Ecosystem (RISE), and all the developed artifacts are open-source.", "description": "This work is done in collaboration with RISC-V Software Ecosystem (RISE) under RISE RP018 - Enabling and Optimizing IREE AI/ML e2e Models for High-Performance RISC-V Hardware - Yolov7/v8. \r\nThis work implements efficient pre- and post-processing pipelines for detection models for RISC-V Vector CPUs and improves IREE compilation for RISC-V, bringing it at par with X86 and ARM. All the artifacts developed in the project are open-source, and improvements made to IREE are planned to be merged into the upstream IREE repository.", "recording_license": "", "do_not_record": false, "persons": [{"code": "GWHRLJ", "name": "Adeel Ahmad", "avatar": "https://cfp.riscv-europe.org/media/avatars/GWHRLJ_DikZTSu.webp", "biography": "I am a compiler engineer at 10xEngineers, working on enabling the compilation of LLMs and vision models for custom hardware/accelerators using IREE, an MLIR-based AI compiler. I have experience in writing optimized kernels for RISC-V Vector (RVV) and custom hardware, LLVM middle-end and backend development.", "public_name": "Adeel Ahmad", "guid": "202a90e8-44be-532e-828d-5399fcd45bd7", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/GWHRLJ/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MYRD9A/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/MYRD9A/", "attachments": []}], "Poster Island D": [{"guid": "7de254ab-d0d3-59e5-9617-73e777682788", "code": "B3ASBU", "id": 349, "logo": null, "date": "2026-06-11T10:30:00+02:00", "start": "10:30", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-349-integrating-risc-v-into-university-education-a-full-stack-approach-to-teaching-system-security", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B3ASBU/", "title": "Integrating RISC-V into University Education: A Full-Stack Approach to Teaching System Security", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The semiconductor industry increasingly requires engineers skilled in both hardware design and software execution. This contribution presents a RISC-V-centric educational pipeline developed at our institute, bridging foundational bachelor's coursework and specialized master's programs. We outline three core courses that integrate practical hardware design, custom ISA extensions, and full-stack security. First, a computer organization course teaches students hardware design in SystemVerilog with the goal of modifying and extending a full RISC-V CPU. Second, a hardware security course tasks students with both the implementation of security-related hardware primitives for open-source RISC-V cores, and the development of software to interact with the extended hardware. Finally, a secure system architectures course addresses memory safety through full system prototyping, requiring students to modify the RISC-V Spike simulator and write custom LLVM compiler passes. This hands-on approach provides the ecosystem with engineers equipped to tackle modern microarchitectural and security challenges.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BBJMPS", "name": "Lorenz Schumm", "avatar": "https://cfp.riscv-europe.org/media/avatars/BBJMPS_G5hSFPx.webp", "biography": "I am a PhD Student at the Institute of Information Security at Graz University of Technology.\r\nMy research focuses on system security, from the perspective of both hardware/software co-design, as well as improving the security for complex software systems.\r\nI am strongly involved in teaching and have, among other things, helped create a new system security course from scratch.", "public_name": "Lorenz Schumm", "guid": "f9ecb9b8-8328-5924-8fba-ff6f79c00c11", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BBJMPS/"}, {"code": "3EWEJR", "name": "Moritz Waser", "avatar": "https://cfp.riscv-europe.org/media/avatars/3EWEJR_ENdlMQF.webp", "biography": "Moritz Waser is a PhD student in the Secure Systems (SESYS) group at ISEC, Graz University of Technology.\r\nHis research interests include memory safety, confidential computing, capability systems and hardware security.", "public_name": "Moritz Waser", "guid": "67ab44fa-5683-58d1-9c5a-ffec5341a39f", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/3EWEJR/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B3ASBU/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/B3ASBU/", "attachments": []}, {"guid": "b69b6670-5c14-5072-9c95-2fd8392488a3", "code": "LCDXJK", "id": 210, "logo": null, "date": "2026-06-11T10:50:00+02:00", "start": "10:50", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-210-x-heep-an-open-hardware-platform-enabling-research-and-education-in-risc-v-soc-design", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LCDXJK/", "title": "X\u2011HEEP: An Open Hardware Platform Enabling Research and Education in RISC\u2011V SoC Design", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "This work presents X-HEEP, an open-source RISC-V System-on-Chip (SoC) platform designed to lower the barrier to chip design for research and education, providing a configurable and extensible infrastructure that enables rapid development of custom RISC-V-based SoCs and hardware accelerators. The platform demonstrates how open ecosystems can accelerate silicon innovation and enable new academic chip design activities. In addition, X-HEEP illustrates how open hardware fosters collaboration between universities and industry, strengthens education in VLSI design, and contributes to broader European initiatives to advance semiconductor capabilities and technological sovereignty.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "Q8NS3J", "name": "Pasquale Davide Schiavone", "avatar": "https://cfp.riscv-europe.org/media/avatars/Q8NS3J_BpzR1y0.webp", "biography": "Pasquale Davide Schiavone (Davide) is a Scientist at the Swiss Federal Institute of Technology Lausanne (EPFL) and Director of Engineering of the OpenHW Group. He was previously working in the ESL lab at EPFL as a PostDoc from 2022 to 2025. He obtained the Ph.D. title at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group in 2020 and the BSc. and MSc. from \"Politecnico di Torino\" in computer engineering in 2013 and 2016, respectively. His main activities are the RISC-V CPU design and low-power energy-efficient heterogeneous computer architectures for smart embedded systems and edge-computing devices.\r\nSince the Ph.D., he delivers training workshops to companies and universities. \r\n\r\nA list of his publications is available at https://scholar.google.ch/citations?user=mfZQ9zUAAAAJ&hl=en\r\n\r\nMy GitHub: https://github.com/davideschiavone", "public_name": "Pasquale Davide Schiavone", "guid": "7d0236f9-5f36-576e-b62c-eccaa8439333", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/Q8NS3J/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LCDXJK/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/LCDXJK/", "attachments": []}, {"guid": "729e7ae1-f87d-5b92-860b-ac6930b9e10d", "code": "C3QQBZ", "id": 70, "logo": null, "date": "2026-06-11T11:00:00+02:00", "start": "11:00", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-70-from-fragmentation-to-systematization-a-standardized-quality-selection-and-reconstruction-approach-for-risc-v-courses", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/C3QQBZ/", "title": "From Fragmentation to Systematization: A Standardized Quality Selection and Reconstruction Approach for RISC-V Courses", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The development of RISC-V technology faces challenges such as the existence of low-quality online courses, fragmented content, a lack of hierarchical and systematic course series, insufficient online experimental practice environments, and limited channels for learning Q&A. The paper sets out to develop a standardized model for assessing the quality of RISC-V courses. In addition, it puts forward a reconstruction method based on course classification tags, organized the individual video into a structured course series. The solution integrates a online RISC-V lab with offline community activities, thereby establishing an integrated online-offline practical teaching environment. This project has produced over 1,000 original RISC-V lecture videos, with total views exceeding 1.3 million. The experimental results demonstrate that the systematically organized course collections generated by this method significantly improve viewership and user engagement, providing a systematic solution for the development of the RISC-V education ecosystem.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "FFQJYM", "name": "Fuyuan Zhang", "avatar": null, "biography": "", "public_name": "Fuyuan Zhang", "guid": "6c26bcc0-381a-5fbf-aa06-4ab52cc195da", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/FFQJYM/"}, {"code": "KNTSHY", "name": "Yunxiang Luo", "avatar": "https://cfp.riscv-europe.org/media/avatars/KNTSHY_n86SpHx.webp", "biography": "Email: luoyunxiang@iscas.ac.cn\r\nIntelligent Software Research Center (ISRC), Institute of Software, Chinese Academy of Sciences (ISCAS)", "public_name": "Yunxiang Luo", "guid": "b618a00a-b794-5236-b4c3-63f3604bfcc9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KNTSHY/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/C3QQBZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/C3QQBZ/", "attachments": [{"title": "poster", "url": "/media/eu-summit-2026/submissions/C3QQBZ/resources/poster_aKMFrZ6.pdf", "type": "related"}]}, {"guid": "e8334bea-263f-59a0-af11-49a6a1fdfe20", "code": "XVSFHN", "id": 42, "logo": null, "date": "2026-06-11T11:10:00+02:00", "start": "11:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-42-one-student-one-chip-initiative-learn-to-build-risc-v-chips-from-scratch-with-mooc", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XVSFHN/", "title": "\"One Student One Chip\" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The \u201cOne Student One Chip\u201d (OSOC) initiative was launched by the University of Chinese Academy of Sciences in 2019. The initiative guides students through designing a RISC-V processor chip from scratch, including tape-out, developing a simple operating system, running it on the chip, running the real game Legend of Sword and Fairy, and completing the physical design process using open-source EDA tools. This enables students to understand the entire processor chip design process. As of February 2026, OSOC enrollments have surpassed 17,000, representing participants from more than 1,200 universities worldwide. This report introduces the implementation of the \u201cOne Student One Chip\u201d initiative and the outcomes of open-source chip talent cultivation.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CKAT8F", "name": "Xiaoke Su", "avatar": "https://cfp.riscv-europe.org/media/avatars/CKAT8F_XRGfkWb.webp", "biography": "", "public_name": "Xiaoke Su", "guid": "664d6d48-1f6e-5994-b0b0-09988d77a5f1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CKAT8F/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XVSFHN/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/XVSFHN/", "attachments": []}, {"guid": "4f04373b-08bd-58bf-811e-ceacd300bdcf", "code": "8CYVSX", "id": 307, "logo": null, "date": "2026-06-11T13:10:00+02:00", "start": "13:10", "duration": "00:10", "room": "Poster Island D", "slug": "eu-summit-2026-307-integrated-development-environment-features-for-unified-database-specification-development", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8CYVSX/", "title": "Integrated Development Environment Features for Unified Database Specification Development", "subtitle": "", "track": "Non-Blind submission", "type": "Poster", "language": "en", "abstract": "The RISC-V Unified Database (UDB) serves as a machine-readable \u201csource of truth\u201d for written RISC-V specifications. To improve the ease of creating these specifications, Qualcomm collaborated with a team of Harvey Mudd College students to develop an Integrated Development Environment (IDE) toolkit that can support architects for RISC-V specifications. The team has worked to develop many of the features one would consider standard for developing in a programming language in a modern IDE, including syntax highlighting, autocompletion, and cross-referencing. The groundwork for this IDE also lays the foundation for other tool developers for the RISC-V ecosystem to use information contained in the UDB more efficiently.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "R9PHCD", "name": "Lughnasa Miller", "avatar": null, "biography": "", "public_name": "Lughnasa Miller", "guid": "08275509-21df-5b46-8c24-eb7e465c8078", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/R9PHCD/"}, {"code": "9R7BCA", "name": "Madeline Seifert", "avatar": null, "biography": null, "public_name": "Madeline Seifert", "guid": "a8b48429-d17e-555b-8a1e-f774e65b1e2d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9R7BCA/"}, {"code": "MDTWH7", "name": "Ajit Dingankar", "avatar": "https://cfp.riscv-europe.org/media/avatars/MDTWH7_Yvb5to7.webp", "biography": "", "public_name": "Ajit Dingankar", "guid": "6fc1768c-047b-5592-ac0b-6de860569c7c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MDTWH7/"}, {"code": "QJHZY9", "name": "Brayden Mendoza", "avatar": null, "biography": "Harvey Mudd College class of 2026 (B.S. in Computer Science)", "public_name": "Brayden Mendoza", "guid": "294a444c-cf30-5b26-aba8-abfba1e2fe21", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QJHZY9/"}, {"code": "KHMJYK", "name": "Isabel Godoy", "avatar": "https://cfp.riscv-europe.org/media/avatars/KHMJYK_ShtnuZq.webp", "biography": "", "public_name": "Isabel Godoy", "guid": "4773e45b-976b-5118-a4c4-8bc9aa93c48d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KHMJYK/"}, {"code": "YVWP8A", "name": "Nina Luo", "avatar": null, "biography": "Recently graduated from Harvey Mudd with a CS degree. I spent the last year building a VS Code extension for the RISC-V Unified Database as part of our Clinic program\u2014think grammar design, validators, and making architectural specs actually usable for developers. Interested in the intersection of tooling, specification, and how good IDE support can make a real difference.", "public_name": "Nina Luo", "guid": "f053c0c7-03bb-56fc-98d7-9252ca1e674c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YVWP8A/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8CYVSX/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/8CYVSX/", "attachments": []}], "Devzone": [{"guid": "2246ea77-e6ad-57f1-976e-52c5835c9b51", "code": "QPRVWP", "id": 358, "logo": null, "date": "2026-06-11T10:30:00+02:00", "start": "10:30", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-358-hardware-acceleration-island-for-safety-critical-applications-based-on-risc-v", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QPRVWP/", "title": "Hardware Acceleration Island for Safety-Critical Applications based on RISC-V", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "The complexity of modern electronics systems and their behavior in harsh environments, demanding performance, fault-tolerance capabilities, and energy efficiency, proves the need to design and implement systems adaptable to applications with mixed-criticality requirements. The Extensible Reliable Offloading Solution (EROS) has been developed as a HW-based accelerator template capable of addressing these requirements. It is compatible with several RISC-V cores from the OpenHW Foundation and eases the integration of both MM accelerators and ISA extensions using CV-X-IF coprocessors. The platform offers a safety wrapper, allowing the selected core to be configured at design time and runtime in different operational modes, from single core execution to fault-tolerant operational modes such as TCLS, DCLS, and staggered. It also provides methods for error detection and recovery. The EROS solution has been implemented as a safety accelerator island in the X-HEEP system, a RISC-V microcontroller platform conceived for ultra-low power scenarios, creating the resulting X-EROS system. This demo evaluates X-EROS, which has been taped out in TSMC 65nm LP technology. The platform is evaluated through performance analysis results obtained from the execution of an AES-256-CBC algorithm. In conjunction, a controlled error injection is performed to prove the functional detection and recovery capabilities. The overall system power consumption is measured to show the different power profiles under different modes of operation, demonstrating the capacity of the platform to adapt itself not only to fault-tolerance requirements but also to low-power requirements.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "9QQKHL", "name": "Luis Waucquez", "avatar": null, "biography": "Luis Waucquez received his BSc and MSc degrees in Electronic Engineering from Universidad Polit\u00e9cnica de Madrid (UPM).\r\nHe is currently pursuing a Ph.D. degree at the Center of Industrial Electronics. His current research interest are open computer architectures and fault-tolerant systems", "public_name": "Luis Waucquez", "guid": "18f81aa9-05aa-582b-94ac-a4df00182ae9", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9QQKHL/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QPRVWP/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/QPRVWP/", "attachments": []}, {"guid": "48b3020a-8578-52b2-aa10-e33cec514c7c", "code": "EGU3RV", "id": 323, "logo": null, "date": "2026-06-11T11:00:00+02:00", "start": "11:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-323-showcasing-the-arcane-in-cache-computing-ip-into-a-risc-v-linux-system", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EGU3RV/", "title": "Showcasing the ARCANE In-Cache computing IP into a RISC-V Linux system", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "The increasing computational demands characteristic of contemporary deep learning models, particularly those associated with computer vision tasks employing Vision Transformers, present considerable constraints for energy-limited smart devices and edge computing platforms. To address this challenge, we demonstrate a RISC-V SoC that incorporates ARCANE, a 512KiB compute-capable Last-Level Cache, which enables In-Cache Computing (ICC). This capability is crucial for substantially mitigating the energy and latency overheads linked to data movement between the central processing unit (CPU) and main memory\u2014a primary architectural bottleneck. To validate the system's operational maturity, we deploy models such as the 22-million parameter DINOv2-S and the lightweight MobileNetV2 utilizing the TVM framework. This deployment serves to demonstrate the platform's capacity to efficiently execute both state-of-the-art, computationally intensive computer vision workloads and standard image classification tasks within a unified environment. The system, instantiated on a ZCU104 FPGA featuring 1GiB of DDR4 memory, operates at a clock frequency of 80MHz and furnishes a Linux operating environment complete with a dedicated suite of user applications. These applications provide quantitative evidence of the significant performance advantages conferred by ARCANE's near-memory computing paradigm when compared against CPU-only execution. By integrating a custom tensor ISA that remains transparent and lock-less to the application programmer, ARCANE establishes itself as a valuable and pioneering contribution to the RISC-V ecosystem, representing one of the first In-Cache Computing IP cores integrated into a Linux operating environment.", "description": "This demonstration showcases user interaction with a CVA6-based RISC-V Linux System-on-Chip (SoC) featuring the 512KiB ARCANE compute-capable Last-Level Cache and 1GiB DDR4 main memory, operating at 80MHz on a ZCU104 FPGA. ARCANE provides the application software programmer with a transparent, convenient, and lock-less custom tensor ISA. Users will execute demanding computer vision applications, notably Meta's DINOv2-S Vision Transformer (comprising 22 million parameters) mirroring high-performance functionalities commonly integrated into commercial smart devices. Furthermore, MobilenetV2 provides the system with image classification capabilities across a diverse range of input images. The Linux environment also furnishes a comprehensive suite of user applications specifically designed to quantitatively demonstrate the significant speed advantages conferred by In-Cache Computing in contrast to conventional CPU-only execution methodologies. This platform establishes ARCANE as a significant and highly valuable contribution to the RISC-V ecosystem. While the user interacts with the system and observes the inference results, we will present the underlying architecture of the system to the audience, address questions, and share insights into some of the technical challenges encountered during the system's development, spanning from the hardware to the application software perspective.", "recording_license": "", "do_not_record": false, "persons": [{"code": "A87H8N", "name": "Vincenzo Petrolo", "avatar": null, "biography": "", "public_name": "Vincenzo Petrolo", "guid": "4af34515-e5b6-505b-8bf0-315bbc2dc6c8", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/A87H8N/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EGU3RV/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/EGU3RV/", "attachments": []}, {"guid": "e618cdef-51f6-5da2-a77e-f0839f90babd", "code": "UC3AZA", "id": 288, "logo": null, "date": "2026-06-11T13:00:00+02:00", "start": "13:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-288-accelerating-matrix-operations-with-a-custom-risc-v-simd-vector-extension-and-automated-llvm-support", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UC3AZA/", "title": "Accelerating Matrix Operations with a Custom RISC\u2011V SIMD/Vector Extension and Automated LLVM Support", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "The development of our tightly coupled SIMD/Vector accelerator for matrix operations requires extending the RISC-V instruction set. Special compiler support is required for this extension. Our methodology starts from a Sail description of the ISA extension and generates the compiler target description data.\r\n\r\nThe accelerator main features are: 32 software defined 2D registers, dedicated hardware for matrix operations and a dedicated memory interface. The accelerator employs the CoreV-eXtension-Interface (CV-X-IF) and could be connected to multiple RISC\u2013V cores that feature this interface. \r\n\r\nThe custom instructions extend the RISC\u2013V ISA and follow their encoding. The custom instructions are of three types: to define matrix registers, matrix operations and memory operations.\r\n\r\nThe instructions are described in Sail and are tested in the generated simulator. adl_tool transforms the Sail architecture description into compiler model artifacts needed to build a functional prototype compiler for the given specification. Additionally, provides automatically generated tests to validate the correctness of the instruction encodings. \r\n\r\nThe compiler was generated from the description model and tested with the accelerator implemented in hardware. The experimental results suggest that for matrix multiplication we obtained speed-ups up to 1413x compared to an ARM A72 core.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "BPAW73", "name": "Catalin Ciobanu", "avatar": "https://cfp.riscv-europe.org/media/avatars/BPAW73_6RQwdXo.webp", "biography": "Catalin Ciobanu has a MSc and PhD from Delft University of Technology, The Netherlands. He is currently Associate Professor at Transilvania University of Brasov, Romania and Senior Researcher at the National Institute for Research and Development in Microtechnologies - IMT Bucharest, Romania. His research interests include RISC-V processors, embedded systems, high performance computing, SIMD architectures, digital signal processing and reconfigurable hardware.", "public_name": "Catalin Ciobanu", "guid": "68259c63-446a-5c73-a5f0-ad83f7f223a1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/BPAW73/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UC3AZA/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/UC3AZA/", "attachments": []}, {"guid": "246f3519-b25b-5df2-94a1-4f4c7893f683", "code": "F7UW8J", "id": 222, "logo": null, "date": "2026-06-11T13:30:00+02:00", "start": "13:30", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-222-integrated-development-environment-features-for-unified-database-specification-development", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UW8J/", "title": "Integrated Development Environment Features for Unified Database Specification Development", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "The RISC-V Unified Database (UDB) serves as a machine-readable \u201csource of truth\u201d for written RISC-V specifications. To improve the ease of creating these specifications, Qualcomm collaborated with a team of Harvey Mudd College students to develop an Integrated Development Environment (IDE) toolkit that can support architects for RISC-V specifications. The team has worked to develop many of the features one would consider standard for developing in a programming language in a modern IDE, including syntax highlighting, autocompletion, and cross-referencing. The groundwork for this IDE also lays the foundation for other tool developers for the RISC-V ecosystem to use information contained in the UDB more efficiently.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "R9PHCD", "name": "Lughnasa Miller", "avatar": null, "biography": "", "public_name": "Lughnasa Miller", "guid": "08275509-21df-5b46-8c24-eb7e465c8078", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/R9PHCD/"}, {"code": "YVWP8A", "name": "Nina Luo", "avatar": null, "biography": "Recently graduated from Harvey Mudd with a CS degree. I spent the last year building a VS Code extension for the RISC-V Unified Database as part of our Clinic program\u2014think grammar design, validators, and making architectural specs actually usable for developers. Interested in the intersection of tooling, specification, and how good IDE support can make a real difference.", "public_name": "Nina Luo", "guid": "f053c0c7-03bb-56fc-98d7-9252ca1e674c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/YVWP8A/"}, {"code": "MDTWH7", "name": "Ajit Dingankar", "avatar": "https://cfp.riscv-europe.org/media/avatars/MDTWH7_Yvb5to7.webp", "biography": "", "public_name": "Ajit Dingankar", "guid": "6fc1768c-047b-5592-ac0b-6de860569c7c", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/MDTWH7/"}, {"code": "QJHZY9", "name": "Brayden Mendoza", "avatar": null, "biography": "Harvey Mudd College class of 2026 (B.S. in Computer Science)", "public_name": "Brayden Mendoza", "guid": "294a444c-cf30-5b26-aba8-abfba1e2fe21", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/QJHZY9/"}, {"code": "KHMJYK", "name": "Isabel Godoy", "avatar": "https://cfp.riscv-europe.org/media/avatars/KHMJYK_ShtnuZq.webp", "biography": "", "public_name": "Isabel Godoy", "guid": "4773e45b-976b-5118-a4c4-8bc9aa93c48d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/KHMJYK/"}, {"code": "9R7BCA", "name": "Madeline Seifert", "avatar": null, "biography": null, "public_name": "Madeline Seifert", "guid": "a8b48429-d17e-555b-8a1e-f774e65b1e2d", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/9R7BCA/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UW8J/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UW8J/", "attachments": [{"title": "Extended Abstract for Submission", "url": "/media/eu-summit-2026/submissions/F7UW8J/resources/HMC_RVI_Summit_Abstr_cAb00Qv.pdf", "type": "related"}]}, {"guid": "c2c3e543-8fa9-5fed-b68c-da68c1c38676", "code": "HXQWPZ", "id": 50, "logo": null, "date": "2026-06-11T14:00:00+02:00", "start": "14:00", "duration": "00:30", "room": "Devzone", "slug": "eu-summit-2026-50-one-student-one-chip-student-board-power-up-demo-video", "url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HXQWPZ/", "title": "\u201cOne Student One Chip\u201d: Student Board Power-Up Demo Video", "subtitle": "", "track": "Demos", "type": "Demo", "language": "en", "abstract": "This video documents the unboxing and functional verification process of the StarrySky development board by participants of the \u201cOne Student One Chip (OSOC)\u201d Program IV, following the successful tape-out and chip delivery. Featuring a fully customized RISC-V processor core independently developed by the trainees, this self-designed board demonstrates remarkable technical achievements through successful execution of classic games like Mario and rendering of the university's emblem.  This helped students strengthen capabilities in hardware\u2013software co-design of computer systems, and cultivated their abilities to understand, build, debug, and optimize complex systems. The student in this video, who is called Tao Zhou, is currently a core technical contributor in the XiangShan frontend team, responsible for the development and performance optimization of the ICache and BPU.", "description": "", "recording_license": "", "do_not_record": false, "persons": [{"code": "CKAT8F", "name": "Xiaoke Su", "avatar": "https://cfp.riscv-europe.org/media/avatars/CKAT8F_XRGfkWb.webp", "biography": "", "public_name": "Xiaoke Su", "guid": "664d6d48-1f6e-5994-b0b0-09988d77a5f1", "url": "https://cfp.riscv-europe.org/eu-summit-2026/speaker/CKAT8F/"}], "links": [], "feedback_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HXQWPZ/feedback/", "origin_url": "https://cfp.riscv-europe.org/eu-summit-2026/talk/HXQWPZ/", "attachments": []}]}}, {"index": 5, "date": "2026-06-12", "day_start": "2026-06-12T04:00:00+02:00", "day_end": "2026-06-13T03:59:00+02:00", "rooms": {}}]}}}