2.0 -//Pentabarf//Schedule//EN PUBLISH B7EASJ@@cfp.riscv-europe.org -B7EASJ RVA23 Profile Support in Linux Kernel: From Extension Definitions to Userspace Export en en 20260609T120000 20260609T121500 0.01500 RVA23 Profile Support in Linux Kernel: From Extension Definitions to Userspace Export By sharing the technical considerations and review discussions from the kernel community, this talk aims to: 1) help community and SoC vendors better understand what is expected when bringing RVA23-compliant hardware to mainline Linux. 2) It also provides feedback to the RISC-V profile specification process on how profile definitions interact with kernel design constraints. (that's a more ambitious goal). My target audience include: Linux kernel and boot firmware developers working on RISC-V architecture support, SoC vendors planning RVA23-compliant products, distribution (such as Debian, Fedora) maintainers interested in generic RISC-V image support, and RISC-V profile specification contributors. PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/B7EASJ/ Plenary Guodong Xu PUBLISH KMNP8Q@@cfp.riscv-europe.org -KMNP8Q The RISE Project: Advancing the RISC-V Software Ecosystem en en 20260609T121500 20260609T123000 0.01500 The RISE Project: Advancing the RISC-V Software Ecosystem PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/KMNP8Q/ Plenary Nathan Egge PUBLISH BTUW3M@@cfp.riscv-europe.org -BTUW3M Building the software ecosystem for a RISC-V datacenter en en 20260609T123000 20260609T124500 0.01500 Building the software ecosystem for a RISC-V datacenter PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/BTUW3M/ Plenary Jon Taylor PUBLISH PC8KYU@@cfp.riscv-europe.org -PC8KYU Why the industry needs CHERI to be able to meet the EU Cyber Resilience Act en en 20260609T170000 20260609T171500 0.01500 Why the industry needs CHERI to be able to meet the EU Cyber Resilience Act PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/PC8KYU/ Plenary Tariq Kurd PUBLISH XFYMDU@@cfp.riscv-europe.org -XFYMDU Practical Implications of SPMP-Based Virtualization in RISC-V en en 20260609T171500 20260609T173000 0.01500 Practical Implications of SPMP-Based Virtualization in RISC-V This work provides information and empirical data about implications derived from the multi-PMP nature of a memory protection architecture using the SPMP for hypervisor (e.g., HW resource usage, timing, etc.), with a complementary discussion about the number of entries that real-world use cases require. This study serves as a response to several concerns raised regarding the impact in HW and timing of having so many PMP entries. PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/XFYMDU/ Plenary Manuel Rodríguez PUBLISH EXN7PD@@cfp.riscv-europe.org -EXN7PD Enabling Confidential Computing on RISC-V: An Open-Source MPT Implementation en en 20260609T173000 20260609T174500 0.01500 Enabling Confidential Computing on RISC-V: An Open-Source MPT Implementation PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/EXN7PD/ Plenary Haoyuan Liu PUBLISH 3EZXZV@@cfp.riscv-europe.org -3EZXZV Heuristic-free system call interception on RISC-V en en 20260609T174500 20260609T180000 0.01500 Heuristic-free system call interception on RISC-V PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/3EZXZV/ Plenary Ottavio Monticelli Iacopo Colonnelli Marco Santimaria PUBLISH ZZ7ADW@@cfp.riscv-europe.org -ZZ7ADW Microarchitectural Side-Channel Attack on RISC-V en en 20260609T103000 20260609T104000 0.01000 Microarchitectural Side-Channel Attack on RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZ7ADW/ Poster Island A Sadia Shamas PUBLISH MKBAZS@@cfp.riscv-europe.org -MKBAZS Evaluating the Vulnerability of RISC-V CPUs Against Cache Timing Attacks en en 20260609T104000 20260609T105000 0.01000 Evaluating the Vulnerability of RISC-V CPUs Against Cache Timing Attacks PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/MKBAZS/ Poster Island A Vasileios Karakostas PUBLISH EFXQQP@@cfp.riscv-europe.org -EFXQQP From Leakage to Exploitability: Empirical Study of Cross-Process L1 Prime+Probe on RISC-V en en 20260609T105000 20260609T110000 0.01000 From Leakage to Exploitability: Empirical Study of Cross-Process L1 Prime+Probe on RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/EFXQQP/ Poster Island A Fortunelli Gianmarco PUBLISH HZQQP9@@cfp.riscv-europe.org -HZQQP9 RISCY Prefetchers en en 20260609T110000 20260609T111000 0.01000 RISCY Prefetchers PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/HZQQP9/ Poster Island A Mohamed Soliman PUBLISH DZKKKP@@cfp.riscv-europe.org -DZKKKP Beyond Bare-Metal: A Lightweight Cross-Privilege Framework for RISC-V RTL Security Evaluation en en 20260609T111000 20260609T112000 0.01000 Beyond Bare-Metal: A Lightweight Cross-Privilege Framework for RISC-V RTL Security Evaluation PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/DZKKKP/ Poster Island A Karim AIT LAHSSAINE PUBLISH CEW33C@@cfp.riscv-europe.org -CEW33C InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment en en 20260609T112000 20260609T113000 0.01000 InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment InjectV is a research framework designed to evaluate the security impact of Fault Injection Attacks (FIAs) on RISC-V systems using full-system simulation. The project focuses on modeling realistic physical attacks that can induce transient faults and alter program execution. The framework is implemented on top of the gem5 microarchitectural simulator in full-system mode, enabling experiments that include the operating system, firmware, and user applications. This allows the study of fault propagation across the entire hardware–software stack in a deterministic and reproducible environment. InjectV introduces an attack-oriented methodology for fault injection so that instead of randomly exploring the fault space, it analyzes execution traces to identify Candidate Injection Points (CIPs) associated with security-relevant operations such as conditional branches, comparisons, and control-flow decisions. Fault injections are then guided toward these points to model realistic attack vectors more efficiently. The system supports transient corruption of both architectural registers and physical memory, with configurable parameters for timing, bit selection, and injection frequency. A campaign manager orchestrates large experimental campaigns, automating simulation execution, parallelization, timeout handling, and result aggregation. The framework was evaluated using the FISSC VerifyPIN benchmark, demonstrating that guided campaigns significantly improve the efficiency of discovering security-relevant faults compared to random exploration. Overall, InjectV provides a reproducible environment for studying how transient hardware faults can be exploited to bypass software protections, enabling early-stage security evaluation of embedded and processor-based systems before physical hardware is available. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/CEW33C/ Poster Island A Niccolò Lentini Giorgio Fardo PUBLISH A9JD3J@@cfp.riscv-europe.org -A9JD3J Exhaustive Security Verification of Access Control in Processors en en 20260609T130000 20260609T131000 0.01000 Exhaustive Security Verification of Access Control in Processors PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/A9JD3J/ Poster Island A Anna Duque Antón PUBLISH SPL3GT@@cfp.riscv-europe.org -SPL3GT CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions en en 20260609T131000 20260609T132000 0.01000 CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/SPL3GT/ Poster Island A Simone Manoni PUBLISH YLJJMH@@cfp.riscv-europe.org -YLJJMH CHERI RVY development support platform en en 20260609T132000 20260609T133000 0.01000 CHERI RVY development support platform PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/YLJJMH/ Poster Island A Alexandre Joannou PUBLISH MD7RVM@@cfp.riscv-europe.org -MD7RVM RV64Y Temporal Safety Exploration en en 20260609T134000 20260609T135000 0.01000 RV64Y Temporal Safety Exploration PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/MD7RVM/ Poster Island A Jonathan Woodruff PUBLISH 9S7HBH@@cfp.riscv-europe.org -9S7HBH The art of zeroing on CHERI RISC-V systems en en 20260609T135000 20260609T140000 0.01000 The art of zeroing on CHERI RISC-V systems PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/9S7HBH/ Poster Island A Yuecheng Wang PUBLISH JFUNQZ@@cfp.riscv-europe.org -JFUNQZ Bao-CHERI: A Pure-Capability RISC-V Hypervisor en en 20260609T140000 20260609T141000 0.01000 Bao-CHERI: A Pure-Capability RISC-V Hypervisor PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/JFUNQZ/ Poster Island A Bruno Sa PUBLISH ZBWRKF@@cfp.riscv-europe.org -ZBWRKF Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V en en 20260609T141000 20260609T142000 0.01000 Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWRKF/ Poster Island A Andreas Hinterdorfer Manfred Schlägl Daniel Große PUBLISH RZD9L9@@cfp.riscv-europe.org -RZD9L9 DASICS: Efficient In-process Protection with Hardware-assisted Dynamic Compartmentalization en en 20260609T153000 20260609T154000 0.01000 DASICS: Efficient In-process Protection with Hardware-assisted Dynamic Compartmentalization PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RZD9L9/ Poster Island A Tianyue Lu PUBLISH RQP9GP@@cfp.riscv-europe.org -RQP9GP Memory Protection for MMU-less RISC-V: Current Status of SPMP and vSPMP en en 20260609T154000 20260609T155000 0.01000 Memory Protection for MMU-less RISC-V: Current Status of SPMP and vSPMP PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RQP9GP/ Poster Island A joseosyx PUBLISH 3JPLFW@@cfp.riscv-europe.org -3JPLFW A Decoupled IOPMP Architecture: Open-Source Implementation with Distributed Bridges for Multi-Master SoCs en en 20260609T155000 20260609T160000 0.01000 A Decoupled IOPMP Architecture: Open-Source Implementation with Distributed Bridges for Multi-Master SoCs PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/3JPLFW/ Poster Island A Hongtuo Yuan PUBLISH FLFBGM@@cfp.riscv-europe.org -FLFBGM An Open-Source RISC-V VM-Level TEE Architecture Implemented on XiangShan Processor en en 20260609T104000 20260609T105000 0.01000 An Open-Source RISC-V VM-Level TEE Architecture Implemented on XiangShan Processor PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/FLFBGM/ Poster Island B Wenhao Wang PUBLISH H87VUG@@cfp.riscv-europe.org -H87VUG CAGE-V: Confidential Computing Architecture supporting Guest Enclaves for RISC-V en en 20260609T105000 20260609T110000 0.01000 CAGE-V: Confidential Computing Architecture supporting Guest Enclaves for RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/H87VUG/ Poster Island B Moritz Waser PUBLISH RT7JWV@@cfp.riscv-europe.org -RT7JWV A Low Latency Real-Time RISC-V MCU for TEE en en 20260609T110000 20260609T111000 0.01000 A Low Latency Real-Time RISC-V MCU for TEE PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RT7JWV/ Poster Island B Paul Shan-Chyun Ku PUBLISH BVHAVM@@cfp.riscv-europe.org -BVHAVM Enhancing Boot Time Security in RISC-V Leveraging Keccak Hardware Accelerator en en 20260609T111000 20260609T112000 0.01000 Enhancing Boot Time Security in RISC-V Leveraging Keccak Hardware Accelerator PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/BVHAVM/ Poster Island B Utku Budak PUBLISH M8ABDU@@cfp.riscv-europe.org -M8ABDU Towards a Secure RISC-V Platform: The Environment Around the CVA6-Core en en 20260609T112000 20260609T113000 0.01000 Towards a Secure RISC-V Platform: The Environment Around the CVA6-Core PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/M8ABDU/ Poster Island B Lukas Füreder PUBLISH NA9Q9H@@cfp.riscv-europe.org -NA9Q9H ACE: Atomic Cryptography Extension for RISC-V en en 20260609T131000 20260609T132000 0.01000 ACE: Atomic Cryptography Extension for RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/NA9Q9H/ Poster Island B Roberto Avanzi, Ruud Derwig, Luis Fiolhais, and Radim Krcmár PUBLISH ZBWEM7@@cfp.riscv-europe.org -ZBWEM7 ANSSI IPECC-Accelerated ECC on CVA6 RISC-V SoC: Integration and Benchmarking en en 20260609T132000 20260609T133000 0.01000 ANSSI IPECC-Accelerated ECC on CVA6 RISC-V SoC: Integration and Benchmarking PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBWEM7/ Poster Island B IGHILAHRIZ Billal PUBLISH QGKMZ7@@cfp.riscv-europe.org -QGKMZ7 Improving ChaCha20 by RISC-V Vector Extension: Design and Engineering Implementation en en 20260609T133000 20260609T134000 0.01000 Improving ChaCha20 by RISC-V Vector Extension: Design and Engineering Implementation The paper is organized as follows: Section 2 reviews the ChaCha20 algorithm; Section 3 introduces the RVV extension and its key instructions for ChaCha20; Section 4 details the vectorized design and engineering implementation; Section 5 presents the experimental results and performance analysis; Section 6 discusses future work; Section 7 concludes the paper. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/QGKMZ7/ Poster Island B Meng Zhuo PUBLISH WEQNRM@@cfp.riscv-europe.org -WEQNRM PQC4eMRTD: Post Quantum Cryptography for Resource Constrained RISC-V Systems en en 20260609T134000 20260609T135000 0.01000 PQC4eMRTD: Post Quantum Cryptography for Resource Constrained RISC-V Systems PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/WEQNRM/ Poster Island B Leonidas Kosmidis PUBLISH PB9JGQ@@cfp.riscv-europe.org -PB9JGQ Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V Secure Elements en en 20260609T135000 20260609T140000 0.01000 Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V Secure Elements PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/PB9JGQ/ Poster Island B Stefano Di Matteo Ivan Sarno Emanuele Valea Hack PUBLISH NEMJHQ@@cfp.riscv-europe.org -NEMJHQ Integrating AES Cryptographic Acceleration with RISC-V Cryptography Extensions in 32-bit processors en en 20260609T140000 20260609T141000 0.01000 Integrating AES Cryptographic Acceleration with RISC-V Cryptography Extensions in 32-bit processors PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/NEMJHQ/ Poster Island B Francisco J. Romero PUBLISH SXGTPT@@cfp.riscv-europe.org -SXGTPT CIRCE: CROSS Integrated RISC-V Cryptographic Extension en en 20260609T141000 20260609T142000 0.01000 CIRCE: CROSS Integrated RISC-V Cryptographic Extension PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/SXGTPT/ Poster Island B Valeria Piscopo aledolme PUBLISH QLUGPK@@cfp.riscv-europe.org -QLUGPK Compiler-Aided Autovectorization of PQC on RISC-V Vector Extensions en en 20260609T153000 20260609T154000 0.01000 Compiler-Aided Autovectorization of PQC on RISC-V Vector Extensions PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/QLUGPK/ Poster Island B Ivan Sarno Stefano Di Matteo PUBLISH ZE8LDR@@cfp.riscv-europe.org -ZE8LDR Performance Characterization and Profiling of HQC Autovectorization on RISC-V Vector cores en en 20260609T154000 20260609T155000 0.01000 Performance Characterization and Profiling of HQC Autovectorization on RISC-V Vector cores This study analyzes the performance characteristics of the HQC post-quantum Key Encapsulation Mechanism on a RISC-V RV64 processor with vector extensions. Multiple polynomial multiplication kernel implementations used in HQC on the Sargantana RV64GBV core are evaluated. Auto-vectorization and cycle-accurate hardware simulation enable comparison of scalar and vectorized implementations across various HQC security levels. Furthermore, the RAVE emulator framework profiles vector execution to identify key performance bottlenecks. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZE8LDR/ Poster Island B Vito Cucinelli PUBLISH ACRS3G@@cfp.riscv-europe.org -ACRS3G CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON en en 20260609T155000 20260609T160000 0.01000 CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ACRS3G/ Poster Island B Enrico Manfredi aledolme Valeria Piscopo PUBLISH ZZQYRH@@cfp.riscv-europe.org -ZZQYRH HORCRUX: a Post-Quantum Cryptography Instruction Set Extension en en 20260609T160000 20260609T161000 0.01000 HORCRUX: a Post-Quantum Cryptography Instruction Set Extension We present a PQC instruction-set extension that prioritizes kernel-level reuse over per-algorithm specialization. The design identifies the recurring computational patterns that dominate PQC workloads and maps them onto a compact set of custom operations executed by a dedicated PQC arithmetic unit. The same accelerated building blocks support NIST-standardized schemes as well as a wider set of candidate designs, without requiring RTL modifications to the host CPU. HORCRUX is implemented in a 65 nm CMOS ASIC flow at 100 MHz, with a synthesized area of 26.3 kGE (less than 2% of the host SoC). Each custom instruction is validated through dedicated micro-tests to capture realistic switching activity; post-synthesis power is estimated with Synopsys PrimePower and combined with measured cycle counts to derive energy per operation. Across the full kernel suite, the proposed instructions deliver approximately 5× average speedup over the software baseline and 47% average energy reduction, up to 99.5% for Karatsuba primitve. Overall, HORCRUX achieves a compact, PQC-ISE that provides consistent acceleration and energy savings across heterogeneous PQC families. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZQYRH/ Poster Island B Valeria Piscopo aledolme PUBLISH 3Y7HQP@@cfp.riscv-europe.org -3Y7HQP Quantum Computing Simulation on RISC-V: Vector and Multithreaded Evaluation en en 20260609T161000 20260609T162000 0.01000 Quantum Computing Simulation on RISC-V: Vector and Multithreaded Evaluation Classical simulation of quantum circuits remains an essential tool for developing and validating quantum algorithms before they can run on real quantum hardware. However, the exponential growth of the quantum state vector quickly makes these simulations computationally demanding, requiring efficient use of modern hardware architectures. In this work, we explore how RISC-V platforms can accelerate quantum simulation by combining vectorization and multithreaded parallelism. A quantum circuit simulator was implemented in C with a focus on optimizing the qubit-wise multiplication kernel, which represents the dominant computational cost in many simulations. Several implementations were evaluated, including a sequential baseline, a multithreaded version using OpenMP, a vectorized implementation using the RISC-V Vector Extension (RVV), and a hybrid approach combining both techniques. Experiments were conducted on a Banana Pi BPI-F3 platform based on the RISC-V SpacemiT K1 processor, with simulations scaling up to 30 qubits. The results show that different optimization strategies become more effective depending on the problem size and memory behavior of the system. The hybrid OpenMP+RVV configuration achieves the best overall performance, reaching a peak speedup of 72.1× and maintaining strong acceleration even for the largest simulations tested. These results highlight the potential of RISC-V architectures for accelerating demanding scientific workloads such as quantum circuit simulation. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/3Y7HQP/ Poster Island B Rebeca Rasco Flores PUBLISH Z8GZYW@@cfp.riscv-europe.org -Z8GZYW RVV Tips & Tricks en en 20260609T103000 20260609T104000 0.01000 RVV Tips & Tricks PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/Z8GZYW/ Poster Island C Olaf Bernstein PUBLISH 8QKTQW@@cfp.riscv-europe.org -8QKTQW Locality-Aware Sparse Matrix Multiplication on RISC-V RVV en en 20260609T110000 20260609T111000 0.01000 Locality-Aware Sparse Matrix Multiplication on RISC-V RVV PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/8QKTQW/ Poster Island C Andrea Herrerías León PUBLISH QUURJD@@cfp.riscv-europe.org -QUURJD Accelerating Myers’ Bit-Vector Alignment With RISC-V Vector Intrinsics en en 20260609T111000 20260609T112000 0.01000 Accelerating Myers’ Bit-Vector Alignment With RISC-V Vector Intrinsics PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/QUURJD/ Poster Island C Elena Espinosa PUBLISH NFYQCV@@cfp.riscv-europe.org -NFYQCV Accelerating LLM Inference on Edge RISC-V CPUs via Vector Extension Instructions and Flash Attention en en 20260609T112000 20260609T113000 0.01000 Accelerating LLM Inference on Edge RISC-V CPUs via Vector Extension Instructions and Flash Attention PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/NFYQCV/ Poster Island C Yueh-Feng Lee PUBLISH QB3TNY@@cfp.riscv-europe.org -QB3TNY Why Edges Matter: A Case Study on Performance Improvements for OpenBLAS GEMM on RISC-V en en 20260609T130000 20260609T131000 0.01000 Why Edges Matter: A Case Study on Performance Improvements for OpenBLAS GEMM on RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/QB3TNY/ Poster Island C Chip Kerchner Rama Malladi PUBLISH WHMPM8@@cfp.riscv-europe.org -WHMPM8 ONNX Runtime Convolution Acceleration on RISC-V via RVV en en 20260609T131000 20260609T132000 0.01000 ONNX Runtime Convolution Acceleration on RISC-V via RVV Our paper proposes an implementation of convolution acceleration in ONNX Runtime for RISC-V using the RISC-V Vector Extension (RVV). The paper explains the context of the contribution and details the two vectorization strategies integrated into ONNX Runtime. Experiments were conducted on a Banana Pi BPI-F3 board, a reference RISC-V hardware for this type of evaluation. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/WHMPM8/ Poster Island C Jose Sanchez-Yun PUBLISH XTDV7A@@cfp.riscv-europe.org -XTDV7A RISC-V Vector 1.0 code Generation in MLIR-xDSL en en 20260609T132000 20260609T133000 0.01000 RISC-V Vector 1.0 code Generation in MLIR-xDSL PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XTDV7A/ Poster Island C Jie Lei PUBLISH 8BXPC9@@cfp.riscv-europe.org -8BXPC9 AI inference on bare-metal RISC-V Microcontrollers: A comparison of ExecuTorch and IREE/MLIR en en 20260609T140000 20260609T141000 0.01000 AI inference on bare-metal RISC-V Microcontrollers: A comparison of ExecuTorch and IREE/MLIR PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/8BXPC9/ Poster Island C Jeremy Bennett PUBLISH VPNYEP@@cfp.riscv-europe.org -VPNYEP From Profiling to Performance: Optimizing Small Language Models on RISC‑V Architectures en en 20260609T141000 20260609T142000 0.01000 From Profiling to Performance: Optimizing Small Language Models on RISC‑V Architectures PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/VPNYEP/ Poster Island C Rama Malladi Chip Kerchner Jose Arnau Dongjie Xie PUBLISH A77QAQ@@cfp.riscv-europe.org -A77QAQ Priority-Aware Scheduling of Multi-Model, Multi-Precision DNN Inference on Multi-Cores RISC-V en en 20260609T142000 20260609T143000 0.01000 Priority-Aware Scheduling of Multi-Model, Multi-Precision DNN Inference on Multi-Cores RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/A77QAQ/ Poster Island C PGA GARREAU PUBLISH PUPQJF@@cfp.riscv-europe.org -PUPQJF End-to-End ML Graph Compiler Fused with Triton Kernel Compiler for RISC-V en en 20260609T153000 20260609T154000 0.01000 End-to-End ML Graph Compiler Fused with Triton Kernel Compiler for RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/PUPQJF/ Poster Island C Hualin Wu PUBLISH CH97A7@@cfp.riscv-europe.org -CH97A7 End-to-End AI Compilation for RISC-V: A Multi-Level Optimization Approach en en 20260609T154000 20260609T155000 0.01000 End-to-End AI Compilation for RISC-V: A Multi-Level Optimization Approach PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/CH97A7/ Poster Island C Hongbin Zhang PUBLISH HAZPKR@@cfp.riscv-europe.org -HAZPKR Code size reduction by advanced near addressing modes en en 20260609T160000 20260609T161000 0.01000 Code size reduction by advanced near addressing modes PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/HAZPKR/ Poster Island C Kajetan Nürnberger PUBLISH DMVSJ8@@cfp.riscv-europe.org -DMVSJ8 ATESOR: A Multi-Stage LLM-based Framework for Autonomous RISC-V Software Porting en en 20260609T161000 20260609T162000 0.01000 ATESOR: A Multi-Stage LLM-based Framework for Autonomous RISC-V Software Porting Software porting often requires deep expertise in target architectures, build systems, and toolchain integration, skills that are not widely available and impose significant manual effort and time costs. To address these challenges, this paper introduces ATESOR, multi-stage, LLM-based framework for autonomous RISC-V software porting. ATESOR uses LLMs with tool-use capabilities to execute a four-stage pipeline: (1) analysis and planning of architecture specific requirements, (2) autonomous generation of build plans and corresponding patches, (3) execution of the build in a RISC-V sandbox environment with automated issue resolution, and (4) verification of build steps and resulting binaries to ensure correctness and reproducibility. To the best of our knowledge, ATESOR is the first LLM-based framework specifically designed for RISCV software porting. The system is trained on an internal dataset comprising over 500 manually ported packages, libraries, and applications, covering a variety of build systems including CMake, Make, and Go, enabling robust learning of architecture-specific build patterns and porting strategies. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/DMVSJ8/ Poster Island C Akif Ejaz PUBLISH XMBLRH@@cfp.riscv-europe.org -XMBLRH RISE and Yocto: Building a RISC-V Board Farm en en 20260609T110000 20260609T111000 0.01000 RISE and Yocto: Building a RISC-V Board Farm This talk will cover the latest in RISC-V support within the Yocto Project ecosystem, including the current state, future plans, and how the wider community can get involved. It could also serve as a BoF or partial BoF format with other speakers. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XMBLRH/ Poster Island D Trevor Gamblin PUBLISH TAK7KZ@@cfp.riscv-europe.org -TAK7KZ Deep Dive into Upstream RISC-V Boot Chain en en 20260609T111000 20260609T112000 0.01000 Deep Dive into Upstream RISC-V Boot Chain PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/TAK7KZ/ Poster Island D Marcel Ziswiler PUBLISH 9G3V9G@@cfp.riscv-europe.org -9G3V9G Implementation of Open RAN software in a RISC-V platform en en 20260609T112000 20260609T113000 0.01000 Implementation of Open RAN software in a RISC-V platform PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/9G3V9G/ Poster Island D Javier Hormigo PUBLISH NJKQXQ@@cfp.riscv-europe.org -NJKQXQ openEuler for RVA23: Building a RISC-V Server OS with Ecosystem Partners en en 20260609T130000 20260609T131000 0.01000 openEuler for RVA23: Building a RISC-V Server OS with Ecosystem Partners PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/NJKQXQ/ Poster Island D Jingwei Wang Sheng Qu YANJUN WU PUBLISH L98NW8@@cfp.riscv-europe.org -L98NW8 openKylin: Empowering the RISC-V AI Ecosystem en en 20260609T131000 20260609T132000 0.01000 openKylin: Empowering the RISC-V AI Ecosystem PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/L98NW8/ Poster Island D Wenzhu Wang PUBLISH K9TL88@@cfp.riscv-europe.org -K9TL88 RuyiSDK Package Manager - A Unified Package Management and Development Environment for RISC-V en en 20260609T132000 20260609T133000 0.01000 RuyiSDK Package Manager - A Unified Package Management and Development Environment for RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/K9TL88/ Poster Island D Weilin Cai Yunxiang Luo PUBLISH XDQWMR@@cfp.riscv-europe.org -XDQWMR Sail-RISCV-WASM A Browser-Native RISC-V Toolchain and Debugging Workbench en en 20260609T133000 20260609T134000 0.01000 Sail-RISCV-WASM A Browser-Native RISC-V Toolchain and Debugging Workbench PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XDQWMR/ Poster Island D Mingzhu Yan Yunxiang Luo PUBLISH 9GW78U@@cfp.riscv-europe.org -9GW78U RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions en en 20260609T134000 20260609T135000 0.01000 RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/9GW78U/ Poster Island D Jonathan Hager Andreas Theiner Matthias Jung Sergio Montenegro Andreas Nüchter PUBLISH YAEZRU@@cfp.riscv-europe.org -YAEZRU Revisiting x86-64 to RISC-V Binary Translation: A Hardware/Software Co-Design Path en en 20260609T135000 20260609T140000 0.01000 Revisiting x86-64 to RISC-V Binary Translation: A Hardware/Software Co-Design Path A semantic-inflation-driven hardware–software co-design approach for x64-to-RV64 binary translation. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/YAEZRU/ Poster Island D Xieyuan Wu PUBLISH 7FMCFX@@cfp.riscv-europe.org -7FMCFX Unlocking High-Performance AVX2 Emulation with RVV 1.0 en en 20260609T140000 20260609T141000 0.01000 Unlocking High-Performance AVX2 Emulation with RVV 1.0 PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/7FMCFX/ Poster Island D Paris Oplopoios PUBLISH RGDVRL@@cfp.riscv-europe.org -RGDVRL Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V en en 20260609T141000 20260609T142000 0.01000 Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RGDVRL/ Poster Island D Frédéric Desbiens Akif Ejaz PUBLISH SFZSB9@@cfp.riscv-europe.org -SFZSB9 Rust on RISC-V: Alignment and Friction at the Hardware-Software Boundary en en 20260609T142000 20260609T143000 0.01000 Rust on RISC-V: Alignment and Friction at the Hardware-Software Boundary This session is aimed at hardware and low-level software engineers working in C and assembly who are curious about Rust but skeptical of its practical fit in RISC-V projects. The talk does not attempt to teach the language. Instead, it provides a structured evaluation of where Rust currently stands in relation to RISC-V workflows. The focus is on architectural and tooling considerations rather than syntax or implementation details. The goal is to support informed technical decision-making rather than promote adoption. As RISC-V systems grow in complexity, the choice of language and tooling becomes a practical engineering decision. This talk frames that decision in concrete terms. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/SFZSB9/ Poster Island D David de Rosier PUBLISH 33798M@@cfp.riscv-europe.org -33798M CREATOR: A RISC-V web simulator based on Sail specification language en en 20260609T154000 20260609T155000 0.01000 CREATOR: A RISC-V web simulator based on Sail specification language PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/33798M/ Poster Island D Juan Carlos Cano Resa PUBLISH 8ALWHG@@cfp.riscv-europe.org -8ALWHG FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor Tomasulo-Style en en 20260609T155000 20260609T160000 0.01000 FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor Tomasulo-Style Educational Tool for SUPERSCALAR RISC-V teaching. Available (and runnable) in GitHub or standalone in portable C. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/8ALWHG/ Poster Island D Roberto Giorgi PUBLISH AVMPST@@cfp.riscv-europe.org -AVMPST RISC-V POWERED QUANTUM SENSOR en en 20260609T103000 20260609T110000 0.03000 RISC-V POWERED QUANTUM SENSOR PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/AVMPST/ Devzone agata.kusnina Marks PUBLISH Q97WYM@@cfp.riscv-europe.org -Q97WYM LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions en en 20260609T110000 20260609T113000 0.03000 LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/Q97WYM/ Devzone Jakob Schäffeler Carsten Trinitis Kun Qin Nima Baradaran Hassanzadeh PUBLISH YQDVJU@@cfp.riscv-europe.org -YQDVJU ML-KEM on a 22 nm ASIC: Protected, Unprotected, and Hardware-Accelerated Implementations en en 20260609T130000 20260609T133000 0.03000 ML-KEM on a 22 nm ASIC: Protected, Unprotected, and Hardware-Accelerated Implementations PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/YQDVJU/ Devzone Stefano Di Matteo Emanuele Valea PUBLISH FZ3AYJ@@cfp.riscv-europe.org -FZ3AYJ OSOC Mambo Robot: RISC-V processor chip showcase using open-source IP, EDA, and PDK en en 20260609T133000 20260609T140000 0.03000 OSOC Mambo Robot: RISC-V processor chip showcase using open-source IP, EDA, and PDK PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/FZ3AYJ/ Devzone Xiaoke Su PUBLISH 78MPFT@@cfp.riscv-europe.org -78MPFT REPTILES: Repeated tiles of Sargantana en en 20260609T140000 20260609T143000 0.03000 REPTILES: Repeated tiles of Sargantana PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/78MPFT/ Devzone Lluc Alvarez Serik Perez Gomez Arnau Bigas Soldevila PUBLISH UCYLJC@@cfp.riscv-europe.org -UCYLJC RVEdge-Vision: A Fully Open, Ultra-Efficient On-Device AI Platform for Smart Eyewear en en 20260610T120000 20260610T121500 0.01500 RVEdge-Vision: A Fully Open, Ultra-Efficient On-Device AI Platform for Smart Eyewear PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/UCYLJC/ Plenary Michele Magno PUBLISH HC7JS8@@cfp.riscv-europe.org -HC7JS8 RIVIERA: A Programmable RISC V Edge Architecture for NFC Signal Processing en en 20260610T121500 20260610T123000 0.01500 RIVIERA: A Programmable RISC V Edge Architecture for NFC Signal Processing PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/HC7JS8/ Plenary Luca Lingardo PUBLISH JKTENR@@cfp.riscv-europe.org -JKTENR Accelerating RISC-V Innovation with open MPACT Tools from Google en en 20260610T123000 20260610T124500 0.01500 Accelerating RISC-V Innovation with open MPACT Tools from Google Summary This submission will detail the use of 4 open-sourced tools to provide simulation and verification support for the CoralNPU, a RISC-V compliant, full-stack, open-source platform designed to address the core performance, fragmentation, and privacy challenges limiting powerful, always-on AI with low-power edge devices and wearables. Importance The open-sourced tools provide immediate support for a wide range of Risc-V architecture extensions, and are easily adaptable to new variations, supporting their development from prototyping to design, and verification. The tools have been tested and are in active use. Contributing to the Ecosystem This work has contributed freely available tools for simulation and verification that can be used immediately, or customized to fit the requirements of new architectural variations. Target Audience ISA Architects, early software developers, designers and verification engineers. Bibliography [1] Google LLC, “GitHub - google/mpact-sim,” GitHub, 2025. http://github.com/google/mpact-sim [2] Google LLC, “GitHub - google/mpact-riscv,” GitHub, May 08, 2023. http://github.com/google/mpact-riscv [3] B. Rutledge, “Introducing Coral NPU: a full-stack Platform for Edge AI,” Googleblog.com, Oct. 15, 2025. https://developers.googleblog.com/introducing-coral-npu-a-full-stack-platform-for-edge-ai/ [4] Google LLC, “GitHub - google-coral/coralnpu-mpact: CoralNPU Behavior Simulator Based on MPACT-Sim,” GitHub, 2025. https://github.com/google-coral/coralnpu-mpact [5] Google LLC, “coralnpu/tests/uvm at main · google-coral/coralnpu,” GitHub, 2025. https://github.com/google-coral/coralnpu/tree/main/tests/uvm PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/JKTENR/ Plenary Tor Jeremiassen Yenkai Wang PUBLISH QVKCU9@@cfp.riscv-europe.org -QVKCU9 SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification en en 20260610T124500 20260610T130000 0.01500 SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/QVKCU9/ Plenary Yinan Xu PUBLISH G7YSXG@@cfp.riscv-europe.org -G7YSXG Ultra Low Power RISC-V core: Retention with Warm Restart Extension en en 20260610T164500 20260610T170000 0.01500 Ultra Low Power RISC-V core: Retention with Warm Restart Extension This paper details the concrete microarchitectural and system mechanisms used to realize the Ultra Low Power Retention with Warm Restart Mode on an in‑house RV32, 4‑stage RISC‑V core family. Beyond the abstract, it precisely defines the power partitioning strategy, where the core power domain is fully shut down while TCMs remain in retention, and explains the implications on context handling, including architectural, non‑architectural, and hardware‑updated read‑only registers. A central contribution is the XSTULP custom extension, mapped in the custom‑0 opcode space, which introduces two atomic instructions, XSTULP.gtr and XSTULP.rtr. These instructions micro‑sequence optimized internal operations (register access, memory transfers with pre/post‑update of a hidden stack pointer XS) to perform complete context save/restore in hardware, while software only needs to prepare a retention stack in TCM and disable interrupts. The paper also describes the request–acknowledge protocol between the core and SoC, specific usage of RISC-V CSR, and the dedicated warm_restart_sequence that determines whether execution follows the normal boot flow or a warm restart path. Finally, the authors report quantitative KPIs (power, latency, area, software overhead) and outline the verification methodology, including UPF‑based dynamic tests and formal verification, demonstrating robustness of the proposed low‑power mode. PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YSXG/ Plenary Anne Merlande PUBLISH 8LUM7U@@cfp.riscv-europe.org -8LUM7U RISC-V Custom Instructions for Automotive Control and DSP Algorithms Compliant with ISO 26262 en en 20260610T170000 20260610T171500 0.01500 RISC-V Custom Instructions for Automotive Control and DSP Algorithms Compliant with ISO 26262 PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/8LUM7U/ Plenary Andreas Mauderer Zdenek Prikryl PUBLISH WWT8EV@@cfp.riscv-europe.org -WWT8EV Proposal of State Sensitive Counter (Sssscnt) en en 20260610T171500 20260610T173000 0.01500 Proposal of State Sensitive Counter (Sssscnt) PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/WWT8EV/ Plenary Fengxue Zhang Bohua Kou PUBLISH MUFY8Z@@cfp.riscv-europe.org -MUFY8Z A Proof-of-Concept RISC-V with 128-bit Extension en en 20260610T173000 20260610T174500 0.01500 A Proof-of-Concept RISC-V with 128-bit Extension PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/MUFY8Z/ Plenary Frédéric Pétrot PUBLISH R7MK7D@@cfp.riscv-europe.org -R7MK7D An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs en en 20260610T174500 20260610T180000 0.01500 An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/R7MK7D/ Plenary Riccardo Tedeschi PUBLISH NMX7W7@@cfp.riscv-europe.org -NMX7W7 An Efficient Approach to Apply the RISC-V Sail Model to Chip Verification en en 20260610T103000 20260610T104000 0.01000 An Efficient Approach to Apply the RISC-V Sail Model to Chip Verification PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/NMX7W7/ Poster Island A Mingzhu Yan Yunxiang Luo PUBLISH WWSLLF@@cfp.riscv-europe.org -WWSLLF Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior en en 20260610T104000 20260610T105000 0.01000 Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/WWSLLF/ Poster Island A Manfred Schlägl Daniel Große Katharina Ruep PUBLISH FYCK9P@@cfp.riscv-europe.org -FYCK9P Spike-RTL: Two technologies for fast and accurate SW-RTL co-simulation en en 20260610T105000 20260610T110000 0.01000 Spike-RTL: Two technologies for fast and accurate SW-RTL co-simulation PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/FYCK9P/ Poster Island A Eugenio Villar PUBLISH 97EAVY@@cfp.riscv-europe.org -97EAVY Simulation-Driven Framework for Custom RISC-V HW/SW Co-Development and Debug en en 20260610T110000 20260610T111000 0.01000 Simulation-Driven Framework for Custom RISC-V HW/SW Co-Development and Debug PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/97EAVY/ Poster Island A Henrik Gustafsson PUBLISH FWXFHU@@cfp.riscv-europe.org -FWXFHU Functional Verification Strategy for a CVA6 MMU en en 20260610T111000 20260610T112000 0.01000 Functional Verification Strategy for a CVA6 MMU PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/FWXFHU/ Poster Island A Tanuj Khandelwal PUBLISH KBLECB@@cfp.riscv-europe.org -KBLECB Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores en en 20260610T112000 20260610T113000 0.01000 Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/KBLECB/ Poster Island A Ihsane Tahir PUBLISH XANKHZ@@cfp.riscv-europe.org -XANKHZ Reproducibility in open-source RISC-V HW flows en en 20260610T130000 20260610T131000 0.01000 Reproducibility in open-source RISC-V HW flows PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XANKHZ/ Poster Island A Petr Kourzanov Anmol Xx PUBLISH VVBBMK@@cfp.riscv-europe.org -VVBBMK kepler-formal: Open Logic Equivalence Checking for RISC-V CI Workflows en en 20260610T131000 20260610T132000 0.01000 kepler-formal: Open Logic Equivalence Checking for RISC-V CI Workflows The rapid growth of the RISC-V ecosystem has led to an increasing number of open hardware projects developed collaboratively through platforms such as GitHub. While software development widely benefits from automated continuous integration (CI) workflows, equivalent verification infrastructure for hardware design remains limited, particularly for formal verification tasks such as logic equivalence checking (LEC). Most industrial LEC tools remain proprietary and difficult to integrate into distributed open development environments. This work presents kepler-formal, an open-source logic equivalence checking tool designed to operate efficiently within CI pipelines for RISC-V hardware development. Built on top of the Naja infrastructure for hierarchical netlist representation and analysis, the tool enables fast equivalence verification between synthesized or transformed netlists. Runtime experiments on open RISC-V designs demonstrate that equivalence checks can be executed within seconds, making them suitable for automated pull-request validation workflows. The tool is integrated into open silicon flows including OpenROAD where it acts as an automated verification gate during development. By enabling lightweight formal verification in collaborative workflows, this approach helps bridge modern software engineering practices and open hardware development. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/VVBBMK/ Poster Island A Christophe Alexandre Noam Cohen PUBLISH QZVQMY@@cfp.riscv-europe.org -QZVQMY RISC-V Tournament: Battle of HDLs en en 20260610T132000 20260610T133000 0.01000 RISC-V Tournament: Battle of HDLs PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/QZVQMY/ Poster Island A Christoph Hazott PUBLISH 8VDLDD@@cfp.riscv-europe.org -8VDLDD Loom: An Open-Source Toolchain for Automatic FPGA Emulation of Simulation-Grade SystemVerilog en en 20260610T133000 20260610T134000 0.01000 Loom: An Open-Source Toolchain for Automatic FPGA Emulation of Simulation-Grade SystemVerilog PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/8VDLDD/ Poster Island A Florian Zaruba PUBLISH NTCH3P@@cfp.riscv-europe.org -NTCH3P Coverage-Directed Smoke Regression Optimization via Greedy Set Cover for RISC-V Verification en en 20260610T134000 20260610T135000 0.01000 Coverage-Directed Smoke Regression Optimization via Greedy Set Cover for RISC-V Verification PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/NTCH3P/ Poster Island A Anish Jaltare Shubham Singla Abhishek Rajgadia Radha Govindaradjou PUBLISH 87KRJS@@cfp.riscv-europe.org -87KRJS Pre-silicon Robustness Assessment of RISC-V Cores using bit-accurate FPGA fault injection en en 20260610T135000 20260610T140000 0.01000 Pre-silicon Robustness Assessment of RISC-V Cores using bit-accurate FPGA fault injection PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/87KRJS/ Poster Island A Ilya Tuzov PUBLISH 33SLKJ@@cfp.riscv-europe.org -33SLKJ AdaMut-RV: FPGA-Accelerated RISC-V Fuzzing with Adaptive Mutation Operator Scheduling en en 20260610T140000 20260610T141000 0.01000 AdaMut-RV: FPGA-Accelerated RISC-V Fuzzing with Adaptive Mutation Operator Scheduling PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/33SLKJ/ Poster Island A Zheng Huazhong PUBLISH JZAHPN@@cfp.riscv-europe.org -JZAHPN A Hardware-Software Heterogeneous Framework for Agile RISC-V Verification with Model-Based Processor Fuzzing en en 20260610T141000 20260610T142000 0.01000 A Hardware-Software Heterogeneous Framework for Agile RISC-V Verification with Model-Based Processor Fuzzing PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/JZAHPN/ Poster Island A Juncheng Huo PUBLISH GJMGHA@@cfp.riscv-europe.org -GJMGHA UCAgent: An End-to-End Agent for Block-Level Functional Verification en en 20260610T142000 20260610T143000 0.01000 UCAgent: An End-to-End Agent for Block-Level Functional Verification PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/GJMGHA/ Poster Island A Junyue Wang YanPi Fangyuan Song yaozhicheng wangsa PUBLISH DMYH7U@@cfp.riscv-europe.org -DMYH7U Fully Automated RISC-V ArchitecturalExploration with Chipyard and A-DECA en en 20260610T153000 20260610T154000 0.01000 Fully Automated RISC-V ArchitecturalExploration with Chipyard and A-DECA PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/DMYH7U/ Poster Island A Lilia Zaourar Bruno Bodin Bruno Bodin PUBLISH BREVML@@cfp.riscv-europe.org -BREVML LLM-Driven Multi-Agent Framework for Automated RISC-V Verification Stimulus Generation en en 20260610T154000 20260610T155000 0.01000 LLM-Driven Multi-Agent Framework for Automated RISC-V Verification Stimulus Generation PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/BREVML/ Poster Island A Kavya Sri Endukuri Nicholas Matus Radha Govindaradjou PUBLISH FFPCHP@@cfp.riscv-europe.org -FFPCHP Concolic Execution Guided Hybrid Whitebox Fuzzing for RISC-V Processors en en 20260610T155000 20260610T160000 0.01000 Concolic Execution Guided Hybrid Whitebox Fuzzing for RISC-V Processors PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/FFPCHP/ Poster Island A Zijian Jiang PUBLISH RP8QNP@@cfp.riscv-europe.org -RP8QNP Scalable Symbolic Quick Error Detection using Lightweight Processor-Level Abstraction en en 20260610T160000 20260610T161000 0.01000 Scalable Symbolic Quick Error Detection using Lightweight Processor-Level Abstraction PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RP8QNP/ Poster Island A Yufeng Li PUBLISH CBLJYX@@cfp.riscv-europe.org -CBLJYX AI-Driven Testlist Generation for RISC-V Core Verification en en 20260610T161000 20260610T162000 0.01000 AI-Driven Testlist Generation for RISC-V Core Verification PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/CBLJYX/ Poster Island A Vikas Dubey Abhishek Rajgadia Shubham Singla Radha Govindaradjou PUBLISH LZ7U8Y@@cfp.riscv-europe.org -LZ7U8Y Using RISC-V E-Trace for effective insights for RISC-V Vector Optimizations en en 20260610T103000 20260610T104000 0.01000 Using RISC-V E-Trace for effective insights for RISC-V Vector Optimizations PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LZ7U8Y/ Poster Island B Harry van Haaren PUBLISH ESQB3N@@cfp.riscv-europe.org -ESQB3N Open E-Trace Infrastructure: Tooling for Evaluation, Analysis, and Research en en 20260610T104000 20260610T105000 0.01000 Open E-Trace Infrastructure: Tooling for Evaluation, Analysis, and Research PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ESQB3N/ Poster Island B Julian Ganz PUBLISH LWYLAF@@cfp.riscv-europe.org -LWYLAF C-Trace: An Open-Source RISC-V Trace Encoder and its Ecosystem en en 20260610T105000 20260610T110000 0.01000 C-Trace: An Open-Source RISC-V Trace Encoder and its Ecosystem PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LWYLAF/ Poster Island B Alexander Weiss Simon Wegener (AbsInt) PUBLISH DVVW8V@@cfp.riscv-europe.org -DVVW8V Window-Level Telemetry for Runtime Performance and Reliability Monitoring in RISC-V Systems en en 20260610T110000 20260610T111000 0.01000 Window-Level Telemetry for Runtime Performance and Reliability Monitoring in RISC-V Systems PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/DVVW8V/ Poster Island B Arda Öztürk PUBLISH RWGSHJ@@cfp.riscv-europe.org -RWGSHJ RETrace EX: Interactive Trace Analysis Framework for RISC-V Hardware Optimization en en 20260610T111000 20260610T112000 0.01000 RETrace EX: Interactive Trace Analysis Framework for RISC-V Hardware Optimization This submission presents a new user-friendly framework to identify and design profitable custom RISC-V extensions. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RWGSHJ/ Poster Island B Jan Zielasko PUBLISH PTSN7C@@cfp.riscv-europe.org -PTSN7C Holographic Execution: A Hyperdimensional Computing Approach for Robust RISC-V Instruction Decoding en en 20260610T112000 20260610T113000 0.01000 Holographic Execution: A Hyperdimensional Computing Approach for Robust RISC-V Instruction Decoding PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/PTSN7C/ Poster Island B Marcello Barbirotta PUBLISH LNBB8V@@cfp.riscv-europe.org -LNBB8V RISCV-Perf: A Performance Modeling Framework for RISC-V Processors Integrated with Spike en en 20260610T130000 20260610T131000 0.01000 RISCV-Perf: A Performance Modeling Framework for RISC-V Processors Integrated with Spike RISCV-Perf is a research framework designed to support microarchitectural performance exploration for RISC-V processors while maintaining tight integration with existing functional simulators. Unlike many trace-driven simulators that require generating and storing large instruction traces, RISCV-Perf follows an execution-driven approach by directly interfacing with the Spike functional simulator. This design avoids trace generation overhead and simplifies modeling of speculative execution behavior. The framework introduces a lightweight instruction interface that extracts essential instruction information during execution and forwards it to the timing model through an instruction pool and instruction buffer. This mechanism decouples functional execution from timing simulation and enables superscalar modeling where multiple instructions can be processed per cycle. The timing model approximates the structure of modern superscalar out-of-order processors, including register renaming, instruction scheduling, memory operation handling, and cache hierarchy interactions. The design follows a modular architecture that allows researchers to experiment with alternative microarchitectural policies, such as different branch predictors or cache replacement algorithms, without modifying the overall simulation framework. RISCV-Perf aims to provide a practical and extensible platform for early-stage architecture exploration, workload analysis, and microarchitectural policy evaluation for RISC-V systems. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LNBB8V/ Poster Island B Tsung-LI PUBLISH ALLVDR@@cfp.riscv-europe.org -ALLVDR STRiVe-VP: LLVM-based performance simulator for RISC-V processors en en 20260610T131000 20260610T132000 0.01000 STRiVe-VP: LLVM-based performance simulator for RISC-V processors PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ALLVDR/ Poster Island B Giorgio Marletta Giovanni Di Guardo PUBLISH RUUDYM@@cfp.riscv-europe.org -RUUDYM Transaction-Level Analysis and Optimization of Decision Diagram Packages on RISC-V en en 20260610T132000 20260610T133000 0.01000 Transaction-Level Analysis and Optimization of Decision Diagram Packages on RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RUUDYM/ Poster Island B Rune Krauss PUBLISH N7AVZD@@cfp.riscv-europe.org -N7AVZD QUICK: QEMU Internal Checkpointing for Gem5 en en 20260610T134000 20260610T135000 0.01000 QUICK: QEMU Internal Checkpointing for Gem5 QUICK implements checkpoint generation directly inside the QEMU TCG execution engine. At fixed instruction intervals, QUICK automatically creates full-system checkpoints in a format compatible with gem5. These checkpoints capture the complete CPU state—including integer, floating-point, and vector registers, as well as miscellaneous registers such as the program counter—along with the entire main memory. Additionally, QUICK records peripheral states such as timers and UARTs, preventing potential kernel-level hangs during restoration. These checkpoints can later be restored in gem5 to enable detailed cycle-accurate performance evaluation. By combining QEMU’s high-speed functional emulation with gem5’s detailed microarchitectural modeling, QUICK leverages the strengths of both platforms. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/N7AVZD/ Poster Island B Qi Shao PUBLISH SCCL9S@@cfp.riscv-europe.org -SCCL9S Virtual Prototyping of Pixel Detector Architecture via Co-Simulation of PixESL and GVSoC en en 20260610T135000 20260610T140000 0.01000 Virtual Prototyping of Pixel Detector Architecture via Co-Simulation of PixESL and GVSoC PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/SCCL9S/ Poster Island B mobradovic00 PUBLISH F7UKA3@@cfp.riscv-europe.org -F7UKA3 Hardware-Synthesized Monitor-Actuator Design Patterns: a Proof-of-Concept Application en en 20260610T140000 20260610T141000 0.01000 Hardware-Synthesized Monitor-Actuator Design Patterns: a Proof-of-Concept Application PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UKA3/ Poster Island B Giann Spilere Nandi PUBLISH F39Y3T@@cfp.riscv-europe.org -F39Y3T EMiX: Emulating Beyond Single-FPGA Limits en en 20260610T141000 20260610T142000 0.01000 EMiX: Emulating Beyond Single-FPGA Limits PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/F39Y3T/ Poster Island B Behzad Salami Alexander Kropotov PUBLISH BWUHVG@@cfp.riscv-europe.org -BWUHVG Unleashing the Penguin: Programmable Device Model for verifying RISC-V IOMMU using Linux en en 20260610T142000 20260610T143000 0.01000 Unleashing the Penguin: Programmable Device Model for verifying RISC-V IOMMU using Linux PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/BWUHVG/ Poster Island B Sai Rajat Goparaju Nicholas Piggin PUBLISH TTPKFR@@cfp.riscv-europe.org -TTPKFR Cycle-Accurate IOPMP Reference Model with Configurable Interfaces, Integration Tests, and a CVA6 SoC Implementation en en 20260610T153000 20260610T154000 0.01000 Cycle-Accurate IOPMP Reference Model with Configurable Interfaces, Integration Tests, and a CVA6 SoC Implementation PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/TTPKFR/ Poster Island B Gull Ahmed PUBLISH B8BJHQ@@cfp.riscv-europe.org -B8BJHQ GPU-Accelerated Parallel Simulation for RISC-V Multi-Core IP Verification en en 20260610T154000 20260610T155000 0.01000 GPU-Accelerated Parallel Simulation for RISC-V Multi-Core IP Verification This work addresses the growing simulation bottleneck in RISC-V multi-core verification by leveraging GPU parallelism for stimulus generation and coverage computation. It is relevant to the RISC-V community because verification cost dominates development timelines, especially as core counts increase. The framework fosters ecosystem growth by enabling smaller verification teams to achieve coverage closure on complex multi-core designs using commodity GPU hardware rather than expensive emulation platforms. Target audience include verification engineers, IP designers, and EDA researchers working on RISC-V multi core SoCs. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/B8BJHQ/ Poster Island B Abinaya Senthil PUBLISH LSXU7K@@cfp.riscv-europe.org -LSXU7K Wolvrix: A SystemVerilog-Native Graph Infrastructure for RTL Research en en 20260610T155000 20260610T160000 0.01000 Wolvrix: A SystemVerilog-Native Graph Infrastructure for RTL Research PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LSXU7K/ Poster Island B Haojin Tang PUBLISH 3AVQMT@@cfp.riscv-europe.org -3AVQMT The RISC-V test platform; an extension of the omnipresent RISC-V test environments en en 20260610T160000 20260610T161000 0.01000 The RISC-V test platform; an extension of the omnipresent RISC-V test environments This paper discusses riscv-test-platform, an extensible test environment collection designed to build versions of a single test routine in multiple target configurations. As mentioned in the abstract, the project is based on the riscv-test-env repository, and makes a case for extensible bare-metal environments that unify common differences in RISC-V designs. It also explores two cases in which it helped our verification team improve test coverage and bug reproducibility. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/3AVQMT/ Poster Island B Eloi Merino PUBLISH ZBRZ7X@@cfp.riscv-europe.org -ZBRZ7X Benchmarking the Vortex RISC-V GPU for Sparse Workloads en en 20260610T161000 20260610T162000 0.01000 Benchmarking the Vortex RISC-V GPU for Sparse Workloads PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZBRZ7X/ Poster Island B Jules Dubois PUBLISH GLCJSG@@cfp.riscv-europe.org -GLCJSG A Doom Demo Journey: Tenstorrent's Ascalon CPU on Synopsys emulation and prototyping systems en en 20260610T103000 20260610T104000 0.01000 A Doom Demo Journey: Tenstorrent's Ascalon CPU on Synopsys emulation and prototyping systems PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/GLCJSG/ Poster Island C Rae Parnmukh Dongjie Xie Brandon Zupan PUBLISH DHQPQB@@cfp.riscv-europe.org -DHQPQB From Open Architecture to Open Silicon: Taping out CORE-ET Many-Core RISC-V Platform en en 20260610T104000 20260610T105000 0.01000 From Open Architecture to Open Silicon: Taping out CORE-ET Many-Core RISC-V Platform The talk is going to cover the building blocks that made it possible, the tooling and processes that are used to support open development and testing, the software that is being brought from a larger ET-SOC-1 design to a smaller unit of compute. Rather than presenting a fully open flow as a solved problem, this talk offers a practical account of how far open silicon development can be pushed today, what still depends on closed tooling, and what this means for the next generation of open RISC-V designs. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/DHQPQB/ Poster Island C Tanya Dadasheva Roman Shaposhnik PUBLISH XXQJQF@@cfp.riscv-europe.org -XXQJQF The ISOLDE Space Demonstrator: a RISC-V Ecosystem for Low-Power On-board Inference en en 20260610T105000 20260610T110000 0.01000 The ISOLDE Space Demonstrator: a RISC-V Ecosystem for Low-Power On-board Inference PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XXQJQF/ Poster Island C Emanuele Valpreda Davide Di Ienno Mattia Paladino PUBLISH G7YQKR@@cfp.riscv-europe.org -G7YQKR Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform en en 20260610T110000 20260610T111000 0.01000 Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/G7YQKR/ Poster Island C Manolis Marazakis PUBLISH XSLFRB@@cfp.riscv-europe.org -XSLFRB Monte Cimone v3: Where RISC-V Stands in High-Performance Computing en en 20260610T111000 20260610T112000 0.01000 Monte Cimone v3: Where RISC-V Stands in High-Performance Computing PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XSLFRB/ Poster Island C Emanuele Venieri PUBLISH VVJ8FY@@cfp.riscv-europe.org -VVJ8FY Vitamin-V: Results and Lessons Learnt en en 20260610T112000 20260610T113000 0.01000 Vitamin-V: Results and Lessons Learnt PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/VVJ8FY/ Poster Island C Ramon Canal PUBLISH 3XNCRH@@cfp.riscv-europe.org -3XNCRH Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW en en 20260610T130000 20260610T131000 0.01000 Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/3XNCRH/ Poster Island C Afonso Oliveira PUBLISH SED3UJ@@cfp.riscv-europe.org -SED3UJ RISC-V Silicon at Scale in Academia: Designing “Big” Open-Source Chips on PULP Platform en en 20260610T132000 20260610T133000 0.01000 RISC-V Silicon at Scale in Academia: Designing “Big” Open-Source Chips on PULP Platform This extended abstract presents large-scale RISC-V silicon developed in academia using the PULP Platform at ETH Zürich and the University of Bologna. Over a decade, the platform has produced more than 70 ASICs, including several “big” chips exceeding one billion transistors across 22–7 nm technologies. We discuss four key enablers: open-source design reuse, forming capable design teams, access to funding and advanced technologies/IP, and assembly and packaging for prototype quantities, enabling complex academic silicon tapeouts. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/SED3UJ/ Poster Island C Yichao Zhang PUBLISH PRU8TZ@@cfp.riscv-europe.org -PRU8TZ PicoNut/RISC-V: One Educational Platform for Hardware and Software Development en en 20260610T133000 20260610T134000 0.01000 PicoNut/RISC-V: One Educational Platform for Hardware and Software Development PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/PRU8TZ/ Poster Island C Johannes Hofmann Gundolf Kiefer PUBLISH G8FEKT@@cfp.riscv-europe.org -G8FEKT Flying V: A Radiation-Hardened L1 Data Cache for RISC-V Aerospace Processors en en 20260610T134000 20260610T135000 0.01000 Flying V: A Radiation-Hardened L1 Data Cache for RISC-V Aerospace Processors PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/G8FEKT/ Poster Island C César Fuguet PUBLISH TYLEYW@@cfp.riscv-europe.org -TYLEYW Fault-Tolerant Open-Source CVA6 Core for Automotive, Aeronautics and Space en en 20260610T142000 20260610T143000 0.01000 Fault-Tolerant Open-Source CVA6 Core for Automotive, Aeronautics and Space Co-authors: Thales / cortAIx Labs, Palaiseau, France: Jérôme Quévremont, Daniel Gracia Pérez, Abdou Lahat Ndiaye, Julien Mallet STMicroelectronics, Agrate Brianza, Italy: Paolo Zambotti, Francesco Diodati, Stefano Bosisio PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/TYLEYW/ Poster Island C Jérôme Quévremont PUBLISH RCLLZH@@cfp.riscv-europe.org -RCLLZH TOXOS: A RISC-V Coprocessor for Non Linear Function Acceleration en en 20260610T153000 20260610T154000 0.01000 TOXOS: A RISC-V Coprocessor for Non Linear Function Acceleration PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RCLLZH/ Poster Island C Luigi Giuffrida PUBLISH HMZYAS@@cfp.riscv-europe.org -HMZYAS Vishwa: A Scalable RISC-V Based GPGPU en en 20260610T154000 20260610T155000 0.01000 Vishwa: A Scalable RISC-V Based GPGPU The Vishwa architecture follows a hierarchical GPU design composed of a host interface, a global Vishwa Work Distributor (VWD), multiple Vishwa Compute Clusters (VCLs), and a hierarchical memory subsystem connected to high-bandwidth memory. Kernels launched by the host processor are distributed across compute clusters through the VWD, which dynamically assigns workloads to available clusters to maximise parallel utilisation. Each Vishwa Compute Cluster integrates multiple Vishwa Compute Cores (VCCs) along with shared resources such as register files, shared memory, scheduling hardware, and instruction and data caches. This organisation enables the architecture to support a large number of concurrent threads while effectively hiding memory latency through hardware multithreading. The architecture consists of multiple Vishwa Compute Clusters interconnected through a shared cache hierarchy and supported by High Bandwidth Memory (HBM) to provide high-throughput data access. Each VCL integrates four Vishwa Compute Cores, forming a scalable compute unit capable of parallel execution. Every VCC can execute 32 threads in parallel, enabling fine-grained data parallelism across workloads. In addition, each VCC supports up to 16 pipelined thread groups, allowing overlapping execution and improving utilisation of the compute pipeline. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/HMZYAS/ Poster Island C PRANOSE J EDAVOOR Prachi Pandey Vivian PUBLISH RRK9ZJ@@cfp.riscv-europe.org -RRK9ZJ Cincoranch: A Heterogeneous Multi-Microarchitecture RISC-V Test Chip – Silicon Bring-Up en en 20260610T155000 20260610T160000 0.01000 Cincoranch: A Heterogeneous Multi-Microarchitecture RISC-V Test Chip – Silicon Bring-Up PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RRK9ZJ/ Poster Island C Hugo Safadi PUBLISH DSMVHN@@cfp.riscv-europe.org -DSMVHN CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems en en 20260610T160000 20260610T161000 0.01000 CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/DSMVHN/ Poster Island C Enrico Zelioli PUBLISH WDXS8R@@cfp.riscv-europe.org -WDXS8R Toward an open-source platform for multi-lead Embedded ECG Processing on RISC-V processors en en 20260610T161000 20260610T162000 0.01000 Toward an open-source platform for multi-lead Embedded ECG Processing on RISC-V processors PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/WDXS8R/ Poster Island C Da Rocha Carvalho Bruno PUBLISH SFGFJE@@cfp.riscv-europe.org -SFGFJE Who Checks the Checker? End-to-End Architectural SEU Tolerance for RISC-V Microcontroller Protection en en 20260610T103000 20260610T104000 0.01000 Who Checks the Checker? End-to-End Architectural SEU Tolerance for RISC-V Microcontroller Protection PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/SFGFJE/ Poster Island D Michael Rogenmoser PUBLISH EZCAXM@@cfp.riscv-europe.org -EZCAXM A Lightweight Multi-Context Architecture for Mixed-Criticality Systems on RISC-V Processors en en 20260610T104000 20260610T105000 0.01000 A Lightweight Multi-Context Architecture for Mixed-Criticality Systems on RISC-V Processors PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/EZCAXM/ Poster Island D Giacomo Valente Leonardo Fazzini PUBLISH YXSRKX@@cfp.riscv-europe.org -YXSRKX CVA6 Optimization en en 20260610T105000 20260610T110000 0.01000 CVA6 Optimization PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/YXSRKX/ Poster Island D Udaya Subedi Angela Gonzalez PUBLISH 3TQ3K9@@cfp.riscv-europe.org -3TQ3K9 Maximizing Performance at Low Area Cost in RISC-V Processors Leveraging Fine-Grained Multithreading en en 20260610T110000 20260610T111000 0.01000 Maximizing Performance at Low Area Cost in RISC-V Processors Leveraging Fine-Grained Multithreading PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/3TQ3K9/ Poster Island D Arbi PUBLISH 8MCLHT@@cfp.riscv-europe.org -8MCLHT Runtime Reconfiguration of Decoders in Minimal-area RISC-V Cores en en 20260610T111000 20260610T112000 0.01000 Runtime Reconfiguration of Decoders in Minimal-area RISC-V Cores PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/8MCLHT/ Poster Island D Tobias Scheipel Lukas Glantschnig PUBLISH 7AQXJK@@cfp.riscv-europe.org -7AQXJK Generator-Driven Functional Safety for RISC-V SoCs with Formal Assurance en en 20260610T112000 20260610T113000 0.01000 Generator-Driven Functional Safety for RISC-V SoCs with Formal Assurance PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/7AQXJK/ Poster Island D Frederik Haxel PUBLISH LNTKNT@@cfp.riscv-europe.org -LNTKNT Heterogeneous Interrupts for Ultra-Low Latency Embedded RISC-V Systems en en 20260610T130000 20260610T131000 0.01000 Heterogeneous Interrupts for Ultra-Low Latency Embedded RISC-V Systems PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LNTKNT/ Poster Island D Antti Nurmi PUBLISH FMQNTD@@cfp.riscv-europe.org -FMQNTD Advanced Interrupt Latency Optimization Approaches in RISC‑V Interrupt Architectures en en 20260610T131000 20260610T132000 0.01000 Advanced Interrupt Latency Optimization Approaches in RISC‑V Interrupt Architectures PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/FMQNTD/ Poster Island D Evgenii Paltsev PUBLISH LQRAW3@@cfp.riscv-europe.org -LQRAW3 SMSIC: Software-Interrupt MSI Controller for RISCV AIA in Large-Scale NoC Systems en en 20260610T132000 20260610T133000 0.01000 SMSIC: Software-Interrupt MSI Controller for RISCV AIA in Large-Scale NoC Systems In a RISC-V system, Message Signaled Interrupt (MSI) is directed not just to a specific hart but to different domains within that hart, such as the machine or supervisor level, or the VM domain. So, SMSIC contains a separate interrupt file for each privilege level. The MSI write to the interrupt file would raise a software interrupt of that privilege level. When a hart also implements the H extension, its SMSIC has additional interrupt files for virtual harts, called guest interrupt files, which are similar to AIA IMSIC. The number of guest interrupt files an SMSIC has is determined by GEILEN, the number of supported guest external interrupts, as defined by the H extension, which is the same as AIA IMSIC. SMSIC reuses CSR_HGEIP to notify the hypervisor of the virtual machine, rather than introducing a new CSR, as in AIA IMSIC. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LQRAW3/ Poster Island D GUO Ren PUBLISH VXCZWW@@cfp.riscv-europe.org -VXCZWW The Next Generation RISC-V SoCs for Space Communications en en 20260610T133000 20260610T134000 0.01000 The Next Generation RISC-V SoCs for Space Communications PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/VXCZWW/ Poster Island D Marco Bertuletti PUBLISH NWCNCN@@cfp.riscv-europe.org -NWCNCN ALPES: Advanced Low-Power Edge Skeleton en en 20260610T134000 20260610T135000 0.01000 ALPES: Advanced Low-Power Edge Skeleton PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/NWCNCN/ Poster Island D Emanuele Valea JEREMIE PESCATORE PUBLISH HKZX8R@@cfp.riscv-europe.org -HKZX8R Towards Open User-Space Power-Management Communication Interfaces en en 20260610T135000 20260610T140000 0.01000 Towards Open User-Space Power-Management Communication Interfaces PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/HKZX8R/ Poster Island D Antonio del Vecchio Emanuele Venieri PUBLISH ZFMXUE@@cfp.riscv-europe.org -ZFMXUE 1W Envelope: Area-Energy Trade-offs of Scalable RISC-V Systolic Arrays in Sky130 en en 20260610T141000 20260610T142000 0.01000 1W Envelope: Area-Energy Trade-offs of Scalable RISC-V Systolic Arrays in Sky130 PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZFMXUE/ Poster Island D Daniel Klünder PUBLISH PYSBZM@@cfp.riscv-europe.org -PYSBZM Low-power Floating Point Unit for RISC-V Processors using FPHUB format en en 20260610T142000 20260610T143000 0.01000 Low-power Floating Point Unit for RISC-V Processors using FPHUB format PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/PYSBZM/ Poster Island D Javier Hormigo PUBLISH UCSJXG@@cfp.riscv-europe.org -UCSJXG Bringing Cloud-Connected Automotive Workloads to RISC-V: A CVA6-Based FPGA Case Study en en 20260610T153000 20260610T154000 0.01000 Bringing Cloud-Connected Automotive Workloads to RISC-V: A CVA6-Based FPGA Case Study PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/UCSJXG/ Poster Island D Tianhai Liu Holger Blasum PUBLISH UZ9UMQ@@cfp.riscv-europe.org -UZ9UMQ RISC-V vs. ARM in an Embedded Real-Time System en en 20260610T154000 20260610T155000 0.01000 RISC-V vs. ARM in an Embedded Real-Time System PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/UZ9UMQ/ Poster Island D Christian Wenzel-Benner Germano Brunacci PUBLISH MKEL9U@@cfp.riscv-europe.org -MKEL9U RISC-V Address-Encoded Byte Order Extension en en 20260610T155000 20260610T160000 0.01000 RISC-V Address-Encoded Byte Order Extension PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/MKEL9U/ Poster Island D David Guerrero Martos Jorge PUBLISH QEAHWX@@cfp.riscv-europe.org -QEAHWX On-Device Context-Informed Incremental Learning for Myoelectric Control on RISC-V-based Wearable Platform en en 20260610T103000 20260610T110000 0.03000 On-Device Context-Informed Incremental Learning for Myoelectric Control on RISC-V-based Wearable Platform PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/QEAHWX/ Devzone Mattia Orlandi Margherita Rossi PUBLISH GQUDKS@@cfp.riscv-europe.org -GQUDKS Running ILP32 on RVA(22/23)S64: AI Glasses Product Demo en en 20260610T130000 20260610T133000 0.03000 Running ILP32 on RVA(22/23)S64: AI Glasses Product Demo PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/GQUDKS/ Devzone GUO Ren PUBLISH LMUL9F@@cfp.riscv-europe.org -LMUL9F RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses en en 20260610T133000 20260610T140000 0.03000 RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/LMUL9F/ Devzone Sebastian Frey Andrea Helga Bernardi PUBLISH QBPTRZ@@cfp.riscv-europe.org -QBPTRZ RISC-V Edge Processing for Real-Time Unobtrusive Driver State Monitoring on the Automotive SoC en en 20260610T140000 20260610T143000 0.03000 RISC-V Edge Processing for Real-Time Unobtrusive Driver State Monitoring on the Automotive SoC PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/QBPTRZ/ Devzone Massimo PUBLISH SRK9TJ@@cfp.riscv-europe.org -SRK9TJ End-to-End On-Device Transformer Training on Ultra-Low Power RISC-V MCU en en 20260610T153000 20260610T160000 0.03000 End-to-End On-Device Transformer Training on Ultra-Low Power RISC-V MCU PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/SRK9TJ/ Devzone Victor Jung RunW PUBLISH MCBEUE@@cfp.riscv-europe.org -MCBEUE World's first lunar exploration rover using FPGA-based RISC-V processor en en 20260611T100000 20260611T101500 0.01500 World's first lunar exploration rover using FPGA-based RISC-V processor PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/MCBEUE/ Plenary Tetsuo YOSHIMITSU PUBLISH WHFNV3@@cfp.riscv-europe.org -WHFNV3 A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt en en 20260611T101500 20260611T103000 0.01500 A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/WHFNV3/ Plenary Xiaogang Fan PUBLISH ETWPMQ@@cfp.riscv-europe.org -ETWPMQ All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom en en 20260611T120000 20260611T121500 0.01500 All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom This extended abstract presents Zvvm, a RISC-V matrix ISA extension that takes a fundamentally different approach from Arm SME and Intel AMX. Where SME requires a dedicated ZA register file and streaming mode, and AMX uses fixed 16×16 tiles that cannot exploit wider datapaths without ISA revision, Zvvm stores all matrix state in the standard V register file, derives tile geometry algebraically from existing CSR fields, and introduces no new architectural state or modes. This presentation offers a rare window into the architects' design rationale behind a matrix ISA approach that has no counterpart in the industry. Rather than presenting a finished specification, we expose the algebraic foundations, the interplay of five independent geometry knobs (VLEN, λ, LMUL, VL, W), and the deliberate trade-offs that allow one ISA — and one binary — to span from a VLEN=128 microcontroller streaming one column at a time to a VLEN=65536 supercomputer computing full tiles. We show how partial-VL streaming and full bulk tiling are two ends of the same VL continuum, how the bidirectional intent vocabulary lets software and hardware independently express their capabilities through the same opcode, and how microscaling (MXFP8, MXFP4, MXINT8) is integrated via vm-bit opcode aliasing with zero overhead. The design is validated by a public QEMU implementation, BLAS kernels, and a parameterized test suite covering all (SEW, λ, LMUL) combinations — enabling concurrent hardware and software development against a stable, machine-testable specification. PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/ETWPMQ/ Plenary Dr. Philipp Tomsich PUBLISH G7Y79Q@@cfp.riscv-europe.org -G7Y79Q ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V en en 20260611T121500 20260611T123000 0.01500 ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/G7Y79Q/ Plenary Flavia Guella Vincenzo Petrolo PUBLISH HNQPKX@@cfp.riscv-europe.org -HNQPKX Evaluating Tenstorrent RISC-V Accelerators for High Performance Scientific Computing en en 20260611T123000 20260611T124500 0.01500 Evaluating Tenstorrent RISC-V Accelerators for High Performance Scientific Computing PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/HNQPKX/ Plenary Elisabetta Boella PUBLISH FRDLL7@@cfp.riscv-europe.org -FRDLL7 CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures en en 20260611T124500 20260611T130000 0.01500 CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures This work presents CHAKRA-GP, a compiler framework targeting RISC-V–based GPGPUs that combines domain-specific optimization pipelines with unified LLVM-based code generation. HPC workloads are compiled through a direct LLVM [5] optimization flow that generates SIMT [6][7] execution and custom memory instructions optimized for throughput-oriented computation. AI workloads are processed using an MLIR-based [8] pipeline that preserves tensor semantics and performs structured transformations before lowering to LLVM IR for final instruction generation targeting tensor and matrix compute cores. By integrating MLIR-driven high-level optimization with LLVM’s mature backend infrastructure, CHAKRA-GP enables efficient mapping of heterogeneous workloads onto customizable RISC-V GPU architectures while maintaining retargetability across evolving designs. The proposed approach demonstrates how compiler architecture can support co-design of open GPU hardware and software ecosystems for next-generation HPC and AI platforms. PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/FRDLL7/ Plenary Prachi Pandey PRANOSE J EDAVOOR PUBLISH RRD8XA@@cfp.riscv-europe.org -RRD8XA Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System en en 20260611T163000 20260611T164500 0.01500 Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/RRD8XA/ Plenary Dave Cremins PUBLISH D3TVFS@@cfp.riscv-europe.org -D3TVFS Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions en en 20260611T164500 20260611T170000 0.01500 Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/D3TVFS/ Plenary Gabriele Ceccolini PUBLISH TX9SGW@@cfp.riscv-europe.org -TX9SGW Optimizing Llama.cpp and GGML for RISC-V Vector (RVV) en en 20260611T170000 20260611T171500 0.01500 Optimizing Llama.cpp and GGML for RISC-V Vector (RVV) This work is performed under RISE RP-014 - Optimizing Llama.cpp and GGML for RVV. All artifacts are open source and either upstreamed to Llama.cpp or in the process of being upstreamed. This contribution not only improves baseline RISC-V vector hardware performance for AI workloads, enabling adoption among AI developers, but also provides first-class software infrastructure support for RISC-V hardware makers to test, benchmark, and optimize standardized hardware solutions for AI workloads. PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/TX9SGW/ Plenary Taimur Ahmad Adeel Ahmad PUBLISH NHUVSR@@cfp.riscv-europe.org -NHUVSR wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture en en 20260611T171500 20260611T173000 0.01500 wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture PUBLIC CONFIRMED Talk https://cfp.riscv-europe.org/eu-summit-2026/talk/NHUVSR/ Plenary Jonathan Hager Yannik Stamm Matthias Jung Timo Grundheber PUBLISH G93SVJ@@cfp.riscv-europe.org -G93SVJ Accelerating the Poseidon2 S-box in a RISC-V SoC with a 4×4 CGRA en en 20260611T103000 20260611T104000 0.01000 Accelerating the Poseidon2 S-box in a RISC-V SoC with a 4×4 CGRA PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/G93SVJ/ Poster Island A Cristian Campos PUBLISH LP7WTL@@cfp.riscv-europe.org -LP7WTL Energy-Efficiency Optimization of a RISC-V Floating-Point Unit for HPC-Oriented Architectures en en 20260611T104000 20260611T105000 0.01000 Energy-Efficiency Optimization of a RISC-V Floating-Point Unit for HPC-Oriented Architectures PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LP7WTL/ Poster Island A Marco Crisologo PUBLISH KGMSLQ@@cfp.riscv-europe.org -KGMSLQ Lessons Learned from Designing Decoupled-Access Hardware Accelerators in a RISC-V Framework en en 20260611T105000 20260611T110000 0.01000 Lessons Learned from Designing Decoupled-Access Hardware Accelerators in a RISC-V Framework PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/KGMSLQ/ Poster Island A Xicu Marí PUBLISH FWGCHN@@cfp.riscv-europe.org -FWGCHN APEX: Accelerating FFT on CVA6 with a Tightly Coupled CV-X-IF Co-processor en en 20260611T110000 20260611T111000 0.01000 APEX: Accelerating FFT on CVA6 with a Tightly Coupled CV-X-IF Co-processor APEX is a hardware/software co-design project targeting FFT acceleration on the CVA6 RISC-V application-class processor. On the hardware side, APEX is a tightly coupled co-processor connected to CVA6 via an enhanced CV-X-IF interface, implementing pipelined radix-2 and radix-4 butterfly units with a dedicated APEX Register File (APR) for wide operand handling in Q1.15 fixed-point arithmetic. On the software side, the KissFFT library serves as the application program, modified to exploit the APEX hardware through custom RISC-V instructions encoded in the reserved custom opcode space. These instructions — covering butterfly computation (`bfly2`, `bfly4`) and APR load/store configuration (`APEX_CFG`, `APEX_RESTORE`) — are integrated into the **LLVM compiler toolchain**, enabling the generation of APEX-aware machine code directly from a high-level C FFT application. The full stack spans RTL design of the co-processor, CV-X-IF integration with CVA6, ISA extension and instruction encoding, LLVM backend modifications for custom instruction emission, and application-level profiling on FPGA. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/FWGCHN/ Poster Island A Abdul Wadood PUBLISH H8SWVM@@cfp.riscv-europe.org -H8SWVM Integration of CVA6 in ESP for ISA extensions and coherent multicore: with FFT-butterfly instruction en en 20260611T111000 20260611T112000 0.01000 Integration of CVA6 in ESP for ISA extensions and coherent multicore: with FFT-butterfly instruction Integration of the CVA6 application-class RISC-V core into the ESP heterogeneous SoC framework, enabling coherent multicore execution and CV-X-IF-based ISA extensions. A custom FFT butterfly instruction is used as case study, showing low overhead and consistent speedup across FFT sizes. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/H8SWVM/ Poster Island A rodrigo olmos PUBLISH 7TD7TB@@cfp.riscv-europe.org -7TD7TB An Embedded RISC-V Vector Extension for Edge-Oriented Acceleration en en 20260611T112000 20260611T113000 0.01000 An Embedded RISC-V Vector Extension for Edge-Oriented Acceleration PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/7TD7TB/ Poster Island A Iñigo Diez de Ulzurrun PUBLISH 88TJXG@@cfp.riscv-europe.org -88TJXG High-Performance CRC/EC Acceleration for RISC-V Server Storage via Novel ISA Extensions en en 20260611T130000 20260611T131000 0.01000 High-Performance CRC/EC Acceleration for RISC-V Server Storage via Novel ISA Extensions PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/88TJXG/ Poster Island A Zhanheng Yang Fengrui Sun PUBLISH VRKMGE@@cfp.riscv-europe.org -VRKMGE RISC-V Hardware Accelerator for 2-D Discrete Cosine Transform en en 20260611T131000 20260611T132000 0.01000 RISC-V Hardware Accelerator for 2-D Discrete Cosine Transform PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/VRKMGE/ Poster Island A Andrei Stan PUBLISH 3HRCLU@@cfp.riscv-europe.org -3HRCLU A RISC-V Accelerator for Convex Optimisation en en 20260611T132000 20260611T133000 0.01000 A RISC-V Accelerator for Convex Optimisation PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/3HRCLU/ Poster Island A David Herrera Marti PUBLISH ZTDS9J@@cfp.riscv-europe.org -ZTDS9J A Fully Integrated FPGA-Based Reconfigurable Intelligent Surface Controller using an Embedded RISC-V Core en en 20260611T133000 20260611T134000 0.01000 A Fully Integrated FPGA-Based Reconfigurable Intelligent Surface Controller using an Embedded RISC-V Core PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ZTDS9J/ Poster Island A Rubén Padial-Allué PUBLISH 3MEHL7@@cfp.riscv-europe.org -3MEHL7 Improving DSP Performance in Processors by Repurposing Existing Multiplier Architectures en en 20260611T134000 20260611T135000 0.01000 Improving DSP Performance in Processors by Repurposing Existing Multiplier Architectures PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/3MEHL7/ Poster Island A Sven Schönewald PUBLISH MARKW9@@cfp.riscv-europe.org -MARKW9 FPGA Lifecycle Management for RISC-V Systems en en 20260611T135000 20260611T140000 0.01000 FPGA Lifecycle Management for RISC-V Systems PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/MARKW9/ Poster Island A Tianhai Liu PUBLISH EHJ3MR@@cfp.riscv-europe.org -EHJ3MR MAGIA-V: A Heterogeneous Zve32d+GEMM Tile for Emerging Mesh-of-Tiles Accelerators en en 20260611T141000 20260611T142000 0.01000 MAGIA-V: A Heterogeneous Zve32d+GEMM Tile for Emerging Mesh-of-Tiles Accelerators PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/EHJ3MR/ Poster Island A Luca Balboni Alessandro Nadalini PUBLISH BSGU8Y@@cfp.riscv-europe.org -BSGU8Y Tightly Coupled Near-Memory Matrix Unit for RISC-V Embedded Computing en en 20260611T104000 20260611T105000 0.01000 Tightly Coupled Near-Memory Matrix Unit for RISC-V Embedded Computing See Abstract. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/BSGU8Y/ Poster Island B Juan Granja PUBLISH WVYG7T@@cfp.riscv-europe.org -WVYG7T Evaluating the Impact of Vector Co-Processors on Memory Hierarchies through Hybrid Simulation en en 20260611T105000 20260611T110000 0.01000 Evaluating the Impact of Vector Co-Processors on Memory Hierarchies through Hybrid Simulation This extended abstract introduces a method for Verilator and Gem5 hybrid simulation in order to explore the impact of a integrated co-processor on the memory hierarchy and vice-versa. The hybrid simulation framework is evaluated through the testing of a simple system with a single level cache hierarchy, main core, and vector co-processor, and compared to the standard evaluation of both the core and co-processor and memory hierarchy separately. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/WVYG7T/ Poster Island B J Parker Jones PUBLISH XYRVET@@cfp.riscv-europe.org -XYRVET Bicameral+: re-assessing split vector and scalar cache designs for increased efficiency en en 20260611T110000 20260611T111000 0.01000 Bicameral+: re-assessing split vector and scalar cache designs for increased efficiency PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XYRVET/ Poster Island B Borja Perez Aitor Echevarría PUBLISH FP7AUZ@@cfp.riscv-europe.org -FP7AUZ AME-PIM: Breaking the Memory Wall with RISC-V Matrix Extensions and HBM-PIM en en 20260611T111000 20260611T112000 0.01000 AME-PIM: Breaking the Memory Wall with RISC-V Matrix Extensions and HBM-PIM PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/FP7AUZ/ Poster Island B Emanuele Venieri PUBLISH ADHZLM@@cfp.riscv-europe.org -ADHZLM Revisiting Transputers with RISC-V en en 20260611T112000 20260611T113000 0.01000 Revisiting Transputers with RISC-V PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ADHZLM/ Poster Island B Rich Neale PUBLISH W3ANF8@@cfp.riscv-europe.org -W3ANF8 Profiling and Optimizing AME for Matrix Multiplication en en 20260611T130000 20260611T131000 0.01000 Profiling and Optimizing AME for Matrix Multiplication PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/W3ANF8/ Poster Island B Xinlei Zhao PUBLISH U38PRX@@cfp.riscv-europe.org -U38PRX A Holistic Approach to Attached Matrix Extension on RISC-V From ISA to Software Stack en en 20260611T131000 20260611T132000 0.01000 A Holistic Approach to Attached Matrix Extension on RISC-V From ISA to Software Stack The XuanTie TPE demonstrates a production-grade, RISC-V-native Attached Matrix Extension approach to AI acceleration that is both performant and practical. Through this work, we aim to contribute to the RISC-V community in several important ways: • Driving Community-Driven Standardization of AME: Our implementation is closely aligned with the RISC-V AME TG's ongoing AME specification efforts. By sharing our design choices, the trade-offs we encountered, and the real-world workload requirements that shaped our ISA decisions, we hope to provide valuable feedback to the standardization process. We believe that practical, silicon-validated implementations are essential for grounding specification discussions in engineering reality. • Highlighting the Unique Advantages of RISC-V for AI Extension: The openness and modularity of RISC-V make it uniquely suited for domain-specific acceleration. Unlike proprietary ISAs where AI extensions must fit within rigid architectural constraints, RISC-V allows the community to co-evolve the ISA, microarchitecture, and software stack together. The TPE is a concrete example of this co-design philosophy — the AME ISA, the hardware engines, and the software ecosystem were developed in concert, each informing and refining the others. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/U38PRX/ Poster Island B Qiu Jing PUBLISH A8BV3C@@cfp.riscv-europe.org -A8BV3C Architectural Scalability Trade-Offs in an RISC-V Vector Processor for Communication Kernels en en 20260611T132000 20260611T133000 0.01000 Architectural Scalability Trade-Offs in an RISC-V Vector Processor for Communication Kernels PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/A8BV3C/ Poster Island B Keivan Fayyazifard PUBLISH RTYDA8@@cfp.riscv-europe.org -RTYDA8 RISC-V Instruction-Subset Processors for Extreme Edge Machine Learning. en en 20260611T133000 20260611T134000 0.01000 RISC-V Instruction-Subset Processors for Extreme Edge Machine Learning. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/RTYDA8/ Poster Island B Konstantinos Iordanou Shengyu Duan PUBLISH 9PWJCZ@@cfp.riscv-europe.org -9PWJCZ Energy-Efficient RISC-V based neuromorphic SoC for Edge AI Applications en en 20260611T134000 20260611T135000 0.01000 Energy-Efficient RISC-V based neuromorphic SoC for Edge AI Applications PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/9PWJCZ/ Poster Island B wenfei PUBLISH EZY7K8@@cfp.riscv-europe.org -EZY7K8 Co-optimizing Custom Instructions RISC-V and LLM Specialized Accelerator for Attention-Based Edge AI en en 20260611T135000 20260611T140000 0.01000 Co-optimizing Custom Instructions RISC-V and LLM Specialized Accelerator for Attention-Based Edge AI PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/EZY7K8/ Poster Island B Joaquin Cornejo PUBLISH PSCKCE@@cfp.riscv-europe.org -PSCKCE An Open Heterogeneous RISC-V AI Acceleration Architecture for Next-Generation Space Computers en en 20260611T140000 20260611T141000 0.01000 An Open Heterogeneous RISC-V AI Acceleration Architecture for Next-Generation Space Computers PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/PSCKCE/ Poster Island B Yvan Tortorella PUBLISH V33F9K@@cfp.riscv-europe.org -V33F9K Exploring AI Acceleration Paradigms for Automotive RISC-V Platforms en en 20260611T141000 20260611T142000 0.01000 Exploring AI Acceleration Paradigms for Automotive RISC-V Platforms PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/V33F9K/ Poster Island B DAVID ALBACETE SEGURA Anestis Athanasiadis PUBLISH YCVWTV@@cfp.riscv-europe.org -YCVWTV Towards a Modern Packed SIMD Architecture for RISC-V: Learning from Production Of ET-SIMD en en 20260611T103000 20260611T104000 0.01000 Towards a Modern Packed SIMD Architecture for RISC-V: Learning from Production Of ET-SIMD PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/YCVWTV/ Poster Island C FelixCLC PUBLISH S3LMTB@@cfp.riscv-europe.org -S3LMTB RISC-V Packed-SIMD Acceleration for Quantized Edge-AI Inference on Space-Qualified Platforms en en 20260611T104000 20260611T105000 0.01000 RISC-V Packed-SIMD Acceleration for Quantized Edge-AI Inference on Space-Qualified Platforms PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/S3LMTB/ Poster Island C Carlos Rafael Tordoya Taquichiri PUBLISH 9MT9QK@@cfp.riscv-europe.org -9MT9QK Custom RISC‑V SIMD Matrix Extensions with LLVM Support en en 20260611T105000 20260611T110000 0.01000 Custom RISC‑V SIMD Matrix Extensions with LLVM Support PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/9MT9QK/ Poster Island C Alexandru Puscasu Catalin Ciobanu PUBLISH QBSVKB@@cfp.riscv-europe.org -QBSVKB Accelerating neural networks using SIMD ISA-Extension for RISC-V processor platforms: A complete toolflow en en 20260611T110000 20260611T111000 0.01000 Accelerating neural networks using SIMD ISA-Extension for RISC-V processor platforms: A complete toolflow PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/QBSVKB/ Poster Island C Alexander Zapp Carsten Rolfes PUBLISH BXQ73A@@cfp.riscv-europe.org -BXQ73A STARBUG: RISC-V Hint Instructions for Lightweight VLIW Execution on Embedded DSP Workloads en en 20260611T111000 20260611T112000 0.01000 STARBUG: RISC-V Hint Instructions for Lightweight VLIW Execution on Embedded DSP Workloads The pursuit of high Instruction-Level Parallelism (ILP) at lower power has renewed interest in Very Long Instruction Word (VLIW) architectures. Yet, conventional VLIW designs often face challenges such as code density and lack of binary compatibility. This paper introduces a novel hint-based VLIW implementation built on the RISC-V Instruction Set Architecture (ISA). Our proposal utilizes architecturally reserved HINT instructions to encode static scheduling decisions, enabling parallel execution without the need for complex hazard detection hardware. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/BXQ73A/ Poster Island C Leo Marek PUBLISH WKS77D@@cfp.riscv-europe.org -WKS77D Hardware support in RISC-V for ternary LLMs en en 20260611T112000 20260611T113000 0.01000 Hardware support in RISC-V for ternary LLMs PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/WKS77D/ Poster Island C David Aledo PUBLISH ELYZEY@@cfp.riscv-europe.org -ELYZEY Towards Efficient Utilization of RISC-V Long Vector Register Files: A Characterization Study en en 20260611T131000 20260611T132000 0.01000 Towards Efficient Utilization of RISC-V Long Vector Register Files: A Characterization Study PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/ELYZEY/ Poster Island C Álvaro Moreno PUBLISH QM3SVB@@cfp.riscv-europe.org -QM3SVB An Open-Source Framework to Enable Float16 On-Device Training on RISC-V Single-Core en en 20260611T132000 20260611T133000 0.01000 An Open-Source Framework to Enable Float16 On-Device Training on RISC-V Single-Core Various approaches have been proposed in recent years to mitigate the compute and memory extensiveness of On-Device Training (ODT) of Deep Neural Networks, but these approaches struggle to support full-fledged training or the use of a batch size greater than 1. These limitations primarily stem from the design of hybrid methods, which employ quantized operations for the forward pass while reverting to float32 for the computationally expensive backward pass, ultimately leading to significant learning instability. RISC-V offers the scalar float16 extension Zfh and its vector counterpart Zvfh, which stand as promising candidates to meet the full ODT requirements: lower memory footprint than float32 and SIMD execution from Zvfh. Although existing open-source RISC-V frameworks offer full scalar float16 ODT capabilities, it is specific to multi-core platforms. To address the lack of open-source ODT frameworks optimized for RISC-V single-core supporting Zfh and/or Zvfh, we propose an easy-to-use open-source library which allows PyTorch/Tensorflow models to be deployed and fully trained on RISC-V single-core featuring Zfh/Zvfh support. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/QM3SVB/ Poster Island C Benjamin Hubinet PUBLISH MYRD9A@@cfp.riscv-europe.org -MYRD9A Optimizing IREE Compilation and End-to-End Object Detection Pipeline for RISC-V en en 20260611T133000 20260611T134000 0.01000 Optimizing IREE Compilation and End-to-End Object Detection Pipeline for RISC-V This work is done in collaboration with RISC-V Software Ecosystem (RISE) under RISE RP018 - Enabling and Optimizing IREE AI/ML e2e Models for High-Performance RISC-V Hardware - Yolov7/v8. This work implements efficient pre- and post-processing pipelines for detection models for RISC-V Vector CPUs and improves IREE compilation for RISC-V, bringing it at par with X86 and ARM. All the artifacts developed in the project are open-source, and improvements made to IREE are planned to be merged into the upstream IREE repository. PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/MYRD9A/ Poster Island C Adeel Ahmad PUBLISH B3ASBU@@cfp.riscv-europe.org -B3ASBU Integrating RISC-V into University Education: A Full-Stack Approach to Teaching System Security en en 20260611T103000 20260611T104000 0.01000 Integrating RISC-V into University Education: A Full-Stack Approach to Teaching System Security PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/B3ASBU/ Poster Island D Lorenz Schumm Moritz Waser PUBLISH LCDXJK@@cfp.riscv-europe.org -LCDXJK X‑HEEP: An Open Hardware Platform Enabling Research and Education in RISC‑V SoC Design en en 20260611T105000 20260611T110000 0.01000 X‑HEEP: An Open Hardware Platform Enabling Research and Education in RISC‑V SoC Design PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/LCDXJK/ Poster Island D Pasquale Davide Schiavone PUBLISH C3QQBZ@@cfp.riscv-europe.org -C3QQBZ From Fragmentation to Systematization: A Standardized Quality Selection and Reconstruction Approach for RISC-V Courses en en 20260611T110000 20260611T111000 0.01000 From Fragmentation to Systematization: A Standardized Quality Selection and Reconstruction Approach for RISC-V Courses PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/C3QQBZ/ Poster Island D Fuyuan Zhang Yunxiang Luo PUBLISH XVSFHN@@cfp.riscv-europe.org -XVSFHN "One Student One Chip" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC en en 20260611T111000 20260611T112000 0.01000 "One Student One Chip" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/XVSFHN/ Poster Island D Xiaoke Su PUBLISH 8CYVSX@@cfp.riscv-europe.org -8CYVSX Integrated Development Environment Features for Unified Database Specification Development en en 20260611T131000 20260611T132000 0.01000 Integrated Development Environment Features for Unified Database Specification Development PUBLIC CONFIRMED Poster https://cfp.riscv-europe.org/eu-summit-2026/talk/8CYVSX/ Poster Island D Lughnasa Miller Madeline Seifert Ajit Dingankar Brayden Mendoza Isabel Godoy Nina Luo PUBLISH QPRVWP@@cfp.riscv-europe.org -QPRVWP Hardware Acceleration Island for Safety-Critical Applications based on RISC-V en en 20260611T103000 20260611T110000 0.03000 Hardware Acceleration Island for Safety-Critical Applications based on RISC-V PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/QPRVWP/ Devzone Luis Waucquez PUBLISH EGU3RV@@cfp.riscv-europe.org -EGU3RV Showcasing the ARCANE In-Cache computing IP into a RISC-V Linux system en en 20260611T110000 20260611T113000 0.03000 Showcasing the ARCANE In-Cache computing IP into a RISC-V Linux system This demonstration showcases user interaction with a CVA6-based RISC-V Linux System-on-Chip (SoC) featuring the 512KiB ARCANE compute-capable Last-Level Cache and 1GiB DDR4 main memory, operating at 80MHz on a ZCU104 FPGA. ARCANE provides the application software programmer with a transparent, convenient, and lock-less custom tensor ISA. Users will execute demanding computer vision applications, notably Meta's DINOv2-S Vision Transformer (comprising 22 million parameters) mirroring high-performance functionalities commonly integrated into commercial smart devices. Furthermore, MobilenetV2 provides the system with image classification capabilities across a diverse range of input images. The Linux environment also furnishes a comprehensive suite of user applications specifically designed to quantitatively demonstrate the significant speed advantages conferred by In-Cache Computing in contrast to conventional CPU-only execution methodologies. This platform establishes ARCANE as a significant and highly valuable contribution to the RISC-V ecosystem. While the user interacts with the system and observes the inference results, we will present the underlying architecture of the system to the audience, address questions, and share insights into some of the technical challenges encountered during the system's development, spanning from the hardware to the application software perspective. PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/EGU3RV/ Devzone Vincenzo Petrolo PUBLISH UC3AZA@@cfp.riscv-europe.org -UC3AZA Accelerating Matrix Operations with a Custom RISC‑V SIMD/Vector Extension and Automated LLVM Support en en 20260611T130000 20260611T133000 0.03000 Accelerating Matrix Operations with a Custom RISC‑V SIMD/Vector Extension and Automated LLVM Support PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/UC3AZA/ Devzone Catalin Ciobanu PUBLISH F7UW8J@@cfp.riscv-europe.org -F7UW8J Integrated Development Environment Features for Unified Database Specification Development en en 20260611T133000 20260611T140000 0.03000 Integrated Development Environment Features for Unified Database Specification Development PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UW8J/ Devzone Lughnasa Miller Nina Luo Ajit Dingankar Brayden Mendoza Isabel Godoy Madeline Seifert PUBLISH HXQWPZ@@cfp.riscv-europe.org -HXQWPZ “One Student One Chip”: Student Board Power-Up Demo Video en en 20260611T140000 20260611T143000 0.03000 “One Student One Chip”: Student Board Power-Up Demo Video PUBLIC CONFIRMED Demo https://cfp.riscv-europe.org/eu-summit-2026/talk/HXQWPZ/ Devzone Xiaoke Su