The welcome address to the RISC-V Summit Europe 2026 will present the novelties of the event, provide an overview of the agenda, venue and events' details.

The RISC-V ISA and ecosystem are redefining computing, enabling new innovations in applications from the smallest, simplest embedded systems to the most demanding high performance deployments. In this session Andrea Gallo, the CEO of RISC-V International, outlines the progress of the RISC-V ecosystem in real world applications from Automotive, to Embedded, to AI and Data Center. He will outline the successes and momentum that have come from the ratification of the RVA23 profile including the latest product news from around the RISC-V ecosystem in both hardware and software enablement.

The traditional model of selecting a CPU from a datasheet and then beginning software development is outdated. Today, customers need to optimize software while being able to influence the hardware. The hardware/software co-design paradigm shift drives new requirements: system-level virtual platforms; standards-based extensible hardware; and open toolchains.

This keynote will explore how virtual platforms for software development and workload optimization bridges the gap between hardware and software, enabling early architecture exploration for a variety of processor cores. Sam will explain how MIPS Atlas Explorer supports RISC-V designs that conform to standard Profiles while still allowing for application-specific extensions. He will showcase Atlas Explorer in action through demos targeting RISC-V core models and deploying to commercially available hardware. Attendees will also get a glimpse of how Atlas Explorer is being used by industry leaders to tailor systems around real workloads, reducing cost and increasing platform confidence ahead of silicon.

Drawing from hands-on experience building Europe's first RISC-V HPC cluster (Monte Cimone), E4 Computer Engineering argues that RISC-V's main barrier to industrial adoption is no longer hardware, but mindset. The community must evolve from an ISA-focused culture to a full ecosystem vision: industry-grade CPUs and accelerators, robust OS and tooling support, a solid certification program, application porting, and active engagement with industrial users, ISVs, ODMs and OEMs. Only by combining a developer-first with a customer-first approach and actively listening to industrial users can RISC-V make the leap to mainstream adoption.

XiangShan is an open-source high-performance RISC-V processor project launched in 2020. After six years of development, XiangShan has become the most active open-source hardware project internationally, with over 7,000 Stars and 900 Forks on GitHub. XiangShan is the highest-performance open-source RISC-V processor core in the world. The third-generation core, Kunminghu (KMH), supports RVA23 Profile and achieves a measured performance of 16.5 points/GHz on SPECCPU2006, reaching the level of ARM Neoverse‑N2 and meeting the requirements of data center and AI application scenarios. More importantly, XiangShan has achieved product‑level delivery and large‑scale deployment. Multiple companies have successfully taped out chips based on XiangShan and deployed them at scale, with shipments reaching 50,000 units. This talk introduces how XiangShan accelerates its iteration through agile design and achieves product‑level delivery quality through agile verification.

Side-channel attacks leveraging microarchitectural features are well-studied on x86 and ARM, but less so on RISC-V. This work implements and evaluates Flush+Reload cache-side-channel attacks on user-space software in a RISC-V system simulated in gem5 full-system mode. We develop both eviction-based and cache-block-invalidate (cbo.inval) probes, establishing an attack methodology for an unprivileged process using the RISC-V cycle counter. Our experiments reveal timing differences between cached and evicted accesses, confirming the existence of exploitable timing channels. While key recovery remains partial, these results demonstrate the feasibility of cache side-channel attacks on RISC-V and validate gem5 as an effective platform for microarchitectural security research.

Demo proposal presents a RISC-V powered quantum sensor designed for ultra-precise magnetic field measurements even at room temperature using nitrogen-vacancy (NV) center defects in diamond. Quantum magnetometers have a wide range of applications including localization, microscopy, and system control. With RISC-V processor being integrated into the developed system, the aim is to achieve world’s most efficient sensor readout and unlock quantum sensing potential for widespread adoption. For the demonstrator, generic event-based architecture was developed, where the RISC-V plays a vital role in coordinating the hardware and provides a foundation for future miniaturization of the sensor electronics and readout ASIC design. The developed prototype enables pulsed optically detected magnetic resonance (ODMR) measurements, that provide significantly higher precision and improved experimental control in comparison to continuous-wave (CW) techniques. The goal is to showcase RISC-V powered quantum sensor with EDI (Institute of Electronics and Computer Science, Latvia) integrated setup incorporating analogue electronics for generating and sampling microwaves, digital electronics for pre-processing and control, and application-level software for users. However, even if hardware issues arise, the live demonstrator will showcase the complete RISC-V-powered quantum sensing system using the PolarFire SoC Video Kit based sensor platform. Open-source RISC-V processor grants more freedom for future ASIC implementation of the measurement system.

Efficient resource isolation remain critical challenges for RISC-V-based cloud computing, where workloads such as confidential virtual machines (CVMs) and containers face threats from unauthorized memory access, DMA attacks, and cross-privilege&cross-workload attacks. Existing hardware isolation mechanisms like Physical Memory Protection (PMP) suffer from static resource partitioning and inflexible dynamic configuration. This work presents Shield-XS, a lightweight workload isolation model for RISC-V. Shield-XS leverages a bitmap-based mechanism with a Shield-bit (1 bit per 4KB physical page) to dynamically mark and isolate sensitive and normal workloads. It implements hardware-enforced access control integrated into the Memory Manage Unit pipeline, with a dedicated Bitmap Cache to minimize performance overhead. It supports configurable one-way isolation, blocking unauthorized access from non-sensitive workloads to protected memory, I/O, and interrupt resources. Evaluated on a 7nm process, it introduces only 0.3% CPU hardware area overhead. SPEC06 benchmarking shows a mere 0.72% performance overhead. This work provides a flexible, low-overhead isolation solution for virtualization and containerization workloads within the RISC-V ecosystem.

Trusted Execution Environments (TEEs) are essential for cloud security, with Confidential Virtual Machines (CVMs) as the prevailing approach. While proprietary solutions dominate deployments, the RISC-V ecosystem lacks mature open-source CVM implementations despite CoVE progress. This paper presents a VM-level TEE architecture on the open-source XiangShan RISC-V processor, featuring physical isolation of Enclave Management Tasks via dedicated secure cores. We implement bitmap-based page-granularity memory isolation and multi-key memory encryption for fine-grained access control and software-defined full-memory cryptographic protection. Evaluation on FPGA prototypes demonstrates minimal EMS area overhead (<1% of SoC area).

Assessing the vulnerability of caches against side-channel attacks is of critical importance when enhanced microarchitectural security is a primary requirement for multicore CPU implementations. Previous works have proposed various metrics and methodologies to assess such vulnerabilities. However, those works suffer from limitations regarding either the range of target cache attacks, the support for the RISC-V ISA, or the reliance on in-house simulators and tools. The goal of this paper is to provide support for systematically evaluating RISC-V multicore CPUs against a wide range of cache timing attacks. Our approach enables the assessment of both hardware implementations and simulated systems, facilitating early-stage security evaluation during the processor design phase using the open-source gem5 microarchitectural simulator. Specifically, we extend the Cache Timing Vulnerability Score (CTVS) methodology along two axes. We port CTVS to RISC-V, and then we integrate it with gem5 to support both RISC-V and x86 simulated systems. Finally, we evaluate our enhanced CTVS framework on simulated RISC-V and x86 multicore CPUs to demonstrate its effectiveness.

The RISC-V vector extension introduces SIMD instructions to RISC-V, however many known patterns in other SIMD extensions don't translate 1-to-1.
Therefore, the goal of this document is to share various RVV tips and tricks as well as some common pitfalls.
It should help people familiar with other SIMD ISAs to figure out how to efficiently express many common patterns in RVV.
We collected these paradigms while porting various software and algorithms to RVV.

Confidential VMs enable cloud service providers to operate a secure and trustworthy multi-tenant cloud infrastructure.
While confidential VMs ensure comprehensive protection for cloud workloads, such heavy-weight isolation is often omitted for serverless applications that co-locate thousands of cloud workers within the same process to optimize FaaS overheads through efficient context switches.
In this work, we present CAGE-V, a novel confidential computing architecture that supports lightweight enclave-based isolation for individual cloud workers running inside confidential VMs.
Guest enclaves support fast context switches within the confidential VM, as TLB entries are tagged with Domain Identifiers, eliminating overheads that stem from TLB flushes.
We present a CAGE-V prototype, consisting of a hardware extension for the CORE-V CVA6 processor and a small security monitor, and evaluate our design in terms of system performance, demonstrating a minor performance impact.

Cache timing attacks against AES are well studied on x86 and ARM, but their end-to-end exploitability on commercially deployed RISC-V systems under realistic OS scheduling is less documented. This paper presents an experimental evaluation of a Prime+Probe attack targeting the private L1 data cache of a PolarFire SoC RISC-V platform running Linux, where attacker and victim are independent user-space processes time-multiplexed on the same core. We separate three stages, leakage observability, cache-set classification, and key inference, and show that first-round T-table lookups induce measurable per-set interference enabling reliable inference of the most significant 4 bits of AES key bytes. We also find substantial cache-set variability highlighting a practical gap between observable leakage and end-to-end exploitability on real RISC-V systems.

Compilers play a central role in unlocking the full performance potential of rapidly evolving RISC-V processors. In the practice of optimizing SPEC CPU 2006 and SPEC CPU 2017 using LLVM for RISC-V, a few compiler optimizations targeting RISC-V have been implemented, involving approaches that both enhance the effectiveness of individual optimization passes and refine how passes interact within the optimization pipeline.
This work introduces four such optimizations integrated into LLVM: (1) extending loop interchange to support loops containing reduction patterns, (2) enhancing loop strength reduction for nested loops, (3) eliminating unnecessary loop counters to unlock further optimizations such as loop unroll, and (4) refactoring multi-dimensional array accesses to enable subsequent redundant computation elimination. While motivated by RISC-V performance tuning, the proposed techniques can also benefit other architectures such as x86. Evaluated on SPEC CPU 2006 and SPEC CPU 2017, these improvements achieve performance gains ranging from 6\% to 54\% across Intel i9-11900K, SpacemiT Key Stone K1, and XiangShan KMHv3 platforms.

In modern embedded security architectures, the Trusted Execution Environment (TEE) serves as the fundamental tool for isolation, ensuring that critical assets in applications like Electric Vehicles (EVs) and robotics remain protected from compromised software. However, restricted by current RISC-V specifications for MCUs, implementing this isolation typically imposes a severe penalty on real-time performance due to the prolonged software prologue required for context switching. To resolve this, we present a lightweight 2-mode (M-mode and U-mode) secure-domain-aware RISC-V MCU architecture designed for security-sensitive, real-time applications. This architecture introduces a hardware-managed "Trusted State" (TS) used to dynamically filter valid enhanced Physical Memory Protection (ePMP) entries in U-mode. To eliminate register preservation overhead, the MCU features a dedicated "Snapshot Buffer" for every General Purpose Register (GPR) and Control and Status Register (CSR) subject to backup. Crucially, the hardware captures the execution context into this buffer in a single cycle, allowing the CPU to immediately begin executing the Interrupt Service Routine (ISR). The captured data is then pushed to an SP-based Data Local Memory (DLM) via a 128-bit wide data-path in the background. By overlapping this memory write with the ISR's preamble execution, this design effectively hides the context save time, ensuring the system is seamlessly prepared for nested interrupts. This architecture guarantees hardware-enforced isolation while satisfying the real-time requirement.

The RISC-V Vector (RVV) extension introduces powerful yet complex semantics for data-parallel execution, including dynamically sized vectors, per-lane masking, and flexible element widths and groupings. While these features offer high performance and portability, they also complicate debugging, as existing tools, such as GDB, do not present RVV registers in a configuration-aware manner. Consequently, raw and verbose register dumps must be manually interpreted relative to the current vector register state. With register widths of up to 65,536 bits this quickly becomes impractical, making it difficult to understand effects of individual instructions and spot values of interest efficiently.

This demo presents LIBERO, a lightweight visualization tool integrated directly into GDB through its Python API. LIBERO augments GDB’s Text User Interface (TUI) with a custom register view that continuously displays vector contents alongside the relevant configuration state during program execution. LIBERO allows users to select which vector registers to display and automatically renders them based on the width specified in the status register. By embedding these capabilities into GDB, LIBERO enables developers to reason about RVV code more efficiently while preserving the familiar GDB workflow.

Sparse matrix–dense matrix multiplication (SpMM) is a fundamental workload in high-performance computing and emerging edge workloads, yet its performance is typically memory-bound due to irregular and indirect memory accesses. While the RISC-V Vector Extension (RVV) provides flexible data-parallel execution, efficiently exploiting it for sparse workloads remains challenging.

This work evaluates an iterative SpMM kernel on an RVV-enabled RISC-V processor (Spacemit X60, 8 cores) and investigates the combined impact of locality-aware data layout and explicit vectorization. We compare scalar, compiler-vectorized, library-based, and manual intrinsic implementations. Additionally, we apply Morton (Z-order) reordering to improve spatial locality in memory.

Experimental results show that vectorization alone provides limited benefits in memory-bound regimes. However, when combined with Morton reordering, manual RVV vectorization achieves the best performance. Microarchitectural analysis confirms reduced cache misses and improved IPC, although the workload remains fundamentally bandwidth-limited.

The study highlights the importance of data layout co-design when targeting sparse workloads on emerging RISC-V platforms.

While hardware prefetchers accelerate memory performance, they inadvertently leave microarchitectural footprints that attackers can exploit. Previous work showed that instruction and data prefetchers on Intel, AMD and Apple processors are prone to microarchitectural side-channel attacks. In this paper we investigate the data stride prefetcher in the Xuantie C910 -- a server-grade RISC-V processor newly deployed in cloud environments. Furthermore, we present the first microarchitectural attack targeting a hardware prefetcher on a RISC-V processors. In that regard, we port StrideRE on RISC-V processors to reverse engineer its hardware prefetcher. Finally, we provide two Proof-of-Concept (PoC) attacks: partial memory address disclosure and control flow leakage. We find that both attacks are effective across privilege levels.

The Yocto Project is an open-source collaboration providing the tools which developers and organizations need to create custom embedded systems for a variety of architectures. This nominally includes both 32- and 64-bit RISC-V platforms, but until recently, official support and testing has been limited to emulated systems and a community-managed board-support layer (targeting hardware compliant with RVA22 and earlier) called meta-riscv. With the impending mass-availability of RVA23-compliant development boards and growing community interest, the RISE Project aims to ensure that Yocto is ready, by providing developer support for triaging RISC-V specific issues, while simultaneously improving test coverage and board support in the meta-riscv layer. To this end, a set of RVA22-based development boards have been deployed alongside some periodic build and test pipelines implemented with Forgejo and Labgrid, allowing early prototyping of longer-term validation workflows that Yocto and the community can build upon in the future. The foundation that this provides will ensure that as more organizations investigate RISC-V platforms for inclusion in their projects, a proven and reliable level of support will be waiting for them.

Pairwise sequence alignment is a key component of many bioinformatics workflows and is often a performance bottleneck. Recent advances in sequencing technologies have improved accuracy, while also increasing the need for accelerators that can efficiently handle long reads. Myers’ bit-vector algorithm is well suited to acceleration, and AVX-512 has enabled high-performance implementations, such as SeqMatcher. However, these solutions rely on a fixed register width and AVX-512-specific instructions, which creates a scalability ceiling and limits portability. We implement Myers’ algorithm using RISC-V Vector (RVV) intrinsics and focus on the addition step, which we identify as the main bottleneck in our vectorized kernel. We evaluate two RVV addition alternatives across LMUL values and dataset sizes on a Banana Pi and find that the iterative carry-propagation variant achieves up to 10.29x speedup over the scalar baseline.

Mitigating transient execution attacks like Spectre in RISC-V processors requires cycle-accurate Register Transfer Level (RTL) simulation. However, existing methodologies face a severe dichotomy: simple bare-metal benchmarks lack crucial architectural features (e.g., virtual memory, privilege boundaries), while full-OS simulations incur prohibitive execution times. To bridge this gap, we propose a novel, lightweight RTL simulation framework that accurately models cross-privilege transitions (User and Supervisor modes) and virtual address translation without the overhead of a full OS payload. We validated this approach by simulating a realistic, cross-privilege Spectre-PHT attack on the out-of-order NaxRiscv core, achieving secret recovery in approximately 100,000 cycles. This drastically accelerates vulnerability characterization compared to Linux-boot environments. Ultimately, this low-noise environment provides hardware designers with an efficient tool to rapidly analyze transient vulnerabilities and evaluate the performance overhead of hardware countermeasures.

While porting Freedesktop SDK to the EBC7700 for my FOSDEM'26 talk [1], I encountered some UEFI boot issues, which motivated me to dig deeper and uncover all the mysteries about the RISC-V boot chain. This talk looks in-depth at the RISC-V boot chain on the virtualised QEMU target. Starting from the boot ROM, selecting the boot source, usually containing some form of an SPL, like the one from U-Boot. Such SPL, in turn, loads U-Boot proper, which contains OpenSBI, implementing the Supervisor Binary Interface, in so-called FW_DYNAMIC form, meaning it does not require any platform-specific configuration parameters because all required information is passed by the previous booting stage at runtime. OpenSBI gets executed first and stays resident. The handover to the U-Boot boot loader, which implements the UEFI specification, marks the next boot stage. It may either directly load the Linux kernel, an optional initial RAM disk and the device tree, particularly useful during bring-up/development, or launch a UEFI boot loader like systemd-boot or GRUB. Handover to the Linux kernel marks the last and final stage in the boot chain. This talk not only looks at the software involved, but also how it may be built, deployed and debugged. As usual, I complete my talk with a live demo.

[1] https://fosdem.org/2026/schedule/event/LX3NNU-upstream-embedded-linux-on-risc-v-sbcs

Secure boot verifies the integrity and authenticity of code before execution; otherwise, it terminates the boot process. In contrast, measured boot produces verifiable evidence of code integrity at boot time, for example using the Device Identifier Composition Engine (DICE). However, in both mechanisms, hashing large code is the main performance bottleneck. This work combines secure boot and DICE-based measured boot, implements the design on a CVA6-based RISC-V platform, incorporates post-quantum cryptography for quantum-resistant secure boot, and accelerates computationally intensive hash computations through a custom Keccak hardware accelerator.

In this work, we optimize LLM inference on edge RISC-V CPUs using vector extension instructions. We leverage 4-bit vector load and efficient 8-bit dot-product instructions to accelerate quantized and repacked 4-bit kernels in llama.cpp. In addition, we implement RVV support for tiled flash attention, which further improves performance in the prefill stage. Experimental results show that the proposed optimizations achieve 1.72x-2.14x speedup over the upstream implementation while maintaining near-linear scaling for prefill workloads on an RVV-enabled multi-core platform.

The use of open-source stacks with the Open~RAN (Radio Access Network) architecture has been predominantly restricted to x86 and ARM architectures. This work presents the first successful porting of the srsRAN Project to RISC-V, targeting the low-cost Banana Pi BPI-F3 (SpacemiT K1 SoC) board. We describe the cross-compilation toolchain, the removal of AVX/NEON dependencies in favour of a scalar C fallback, and a preliminary performance evaluation across two 5G NR FDD scenarios. Profiling with Linux perf identifies key data-parallel physical layer (PHY) bottlenecks, establishing primary targets for RVV 1.0 vectorisation. Results show that RISC-V offers promising real-time MIMO performance for a single user, even with a scalar fallback, suggesting that vectorisation will elevate it to highly competitive levels.

Fault Injection Attacks (FIAs) induce transient hardware faults to subvert software security mechanisms, yet assessing fault resilience, especially during early design phases, remains impractical without specialized laboratory equipment. Microarchitectural simulation provides a reproducible and scalable alternative. This paper presents InjectV, a gem5-based fault injection framework targeting RISC-V systems, which employs trace-guided fault injection by identifying Candidate Injection Points (CIPs) at security-critical operations including control-flow branches and conditional comparisons. Supporting transient corruption of architectural registers and physical memory under full-system simulation, InjectV demonstrates that guided fault injection requires 95.8% fewer injections than random exploration to expose successful attacks on the FISSC VerifyPIN benchmarks.

The rising adoption of RISC-V in real-world applications raises the requirement of security solutions within its processors. Secure boot enables the product owner to control which software may be booted on it, preventing execution of malicious software. That requires a hardware root-of-trust, typically in conjunction with public key cryptography, establishing the infrastructure to verify software. We propose a secure boot concept for the widely adopted CVA6 core with revocation capabilities. We also modernized the CVA6 software stack to be able to continue the verification steps in later software stages and leverage modern security hardware extensions.

Many people in the past have said "Don't make the same mistakes that other architectures have" when it comes to the development of Linux for RISC-V. Despite this warning, many of the same things keep happening, directly affecting the future success of RISC-V. This talk will go into an opinionated description of some of these issues, and why we should learn from previous mistakes in order to save millions of dollars, and not waste precious effort.

RVA23, ratified by RISC-V International in October 2024, defines the mandatory extension baseline for application-class RISC-V. Eighteen months on, is the profile real inside the software stack? This talk answers from one vantage point — the Linux kernel — through a shipping part.

SpacemiT's K3 is the first mass-produced RVA23 SoC. Bringing it up in mainline (RISCstar with SpacemiT), we found the kernel's RVA23 mandatory coverage stuck near 68% for a year, with bindings missing several extensions. Over several revisions those gaps closed, and Linux v7.0 reached 100%.

From that experience, I examine how the community decides what "supporting" an extension means: a data-backed classification by whether an extension adds architectural state the OS must save and restore — showing roughly two-thirds are stateless and only need to be discoverable, not implemented. This explains the principles maintainers apply.

I then cover two complementary halves now in review for v7.1.

1) Runtime detection: a unified series, carried forward from Andrew Jones' (Qualcomm) RFC, resolving rva23u64/rva23s64 base behaviour and exporting it via /proc/cpuinfo and hwprobe.

2) Compile-time specialisation, presented by co-speaker Charlie Jenkins (Meta), builds the kernel for RVA23. I share review feedback — including Paul Walmsley's call for hardware measurements — answered with numbers from the K3.

Complete mainline RVA23 lets distributions ship generic images and reduce fragmentation; Ubuntu 26.04 has adopted it while Debian, Fedora and Red Hat wait.

The RISC-V Software Ecosystem (RISE) Project is a Linux Foundation Europe initiative where hardware, software and services companies collaborate to bridge the gap between architectural potential and commercial software readiness. While the RISC-V community is highly impactful, industrial-grade software often requires an extra push. RISE provides this through direct engineering, an RFP process that has already deployed over €1M in contracts, and individual support through the RISE Developer Appreciation Program.

This session highlights how RISE is accelerating RISC-V adoption within key upstream open-source projects. We will detail our strategic push to enable AI/ML workloads through targeted investments in PyTorch, Llama.cpp, IREE, oneDNN, and OpenBLAS. We’ll demonstrate how RISE is lowering the barrier to entry by providing free GitHub and GitLab runners for riscv64, alongside self-service remote hardware access via the RISE Board Farm. Finally, we will share our long-term roadmap for ecosystem performance and stability, focusing on LLVM auto-vectorization for RVV at scale and the RISE Build Farm’s role in proactive bug detection across kernel, toolchain and system libraries.

The RISC-V software ecosystem has grown steadily over the last few years. For embedded software it is reasonably complete, with good compiler, RTOS, and IDE support. The Linux kernel is also well supported, with RISC-V long having upstream support, and RVA23 now supported too. Canonical moved to requiring RVA23 with the release of Ubuntu 25.10, ready for the next generation of RISC-V silicon. But building out a data center takes more than just a good desktop experience. This poster/paper will examine the other elements required including provisioning, hypervisors, containers, orchestration, and also discusses how to manage custom instructions, security, maintenance. Going beyond theory, it discusses the data center Canonical will be building to include RISC-V RVA23 silicon supporting the Launchpad.net community website as well as other uses.

Abstract: RISC-V provides the ability to provide organizations of all sizes with greater flexibility and more opportunity for custom compute. We are seeing rapid adoption in a wide range of markets from automotive to mobile to data center, to aeronautics and space! Companies around the world are innovating for and on RISC-V to drive the era of open compute. In this session, we will hear directly from companies who have recently launched new solutions helping to power the era of open compute and how RISC-V helps them differentiate.

These are not your ordinary product pitches. Selected companies are given tight time constraints to hit the high points and make the case for their new solution. If they go over, the audience get to clap them off stage!

Presenters:
Breker Systems
CEA
Epic Semi
SiFive
Tenstorrent
TRISTAN / ISOLDE
ESWIN Computing
Xauntie

Access control is a foundation of security and is implemented in the hardware of Systems-on-chip. The entire system stack relies on the secure and correct functioning of these access control mechanisms. However, contemporary security verification methods face major challenges in exhaustively detecting targeted security vulnerabilities while also being scalable. We address these challenges with a novel formulation of security property sets. Our approach introduces interlocked property sets, which have a mathematical characteristic that enables scalable and exhaustive verification of general security targets. We propose an interlocked property set for access control verification in processors and have evaluated our approach in several case studies on RISC-V processor cores. Our approach detected multiple security vulnerabilities.

Post-Quantum Cryptography is becoming a key building block for future secure systems, as quantum computers threaten widely deployed public-key cryptographic algorithms. In response, the NIST standardization process has selected new quantum-resistant schemes, among which ML-KEM plays a central role for key establishment. Deploying these algorithms efficiently on embedded processors is therefore a critical step toward practical adoption, particularly because embedded systems face strict constraints in terms of computational resources, memory footprint, and energy consumption. At the same time, they are more exposed to physical threats, making resistance to side-channel attacks a key requirement. These constraints make RISC-V especially attractive: its open instruction set and extensibility allow experimentation with software optimizations as well as hardware acceleration for PQC. To explore these aspects, CEA has developed VASCO3, a 22 nm ASIC chip designed to experimentally evaluate PQC implementations and side-channel countermeasures directly on silicon. The chip integrates a RISC-V–based System-on-Chip (SoC) together with several ML-KEM hardware accelerators, enabling the study of different hardware/software partitioning strategies around an embedded RISC-V CPU. In this demonstration, we present a comprehensive exploration of ML-KEM. We first showcase a pure software implementation running on the RISC-V, then progressively introduce hardware acceleration and a fully dedicated ML-KEM accelerator. We also demonstrate protected implementations based on first-order masking, including a masked software version and a masked hardware-assisted design.

We present a practical RSS (Root Security System) which not only conforms to HW RoT security requirement in RISC-V Server SoC and Platform Specification but also could be integrated into Server and AI SoC as HW RoT to offer security services applicable to system security service and user application. Beside already defined security rules to HW RoT, we found RSS also requires new function to enhance system security and support server Reliability, Availabitliy and Servicable. we present new 4 security rules proposal to HW RoT according to new function. Finally, we discuss an effective solution for RSS to security compliance certification as TOE.

Matrix multiplication (GEMM) sits at the heart of scientific computing, data analytics, and modern AI workloads. While much attention is given to peak throughput and ideal matrix sizes, real-world performance often hinges on the “edges” i.e., non-ideal dimensions, cache boundaries, and vector tail cases that quietly dominate execution time. In this paper, we present a practical case study of optimizing GEMM in OpenBLAS for RISC-V vector architectures. We show how careful handling of edge conditions, cache reuse, and vectorization strategy can deliver measurable performance gains. Techniques include maximizing cache and register reuse with single-pass data traversal, swapping operands and deferring transposition for easier storage, combining full- and half-vector operations with scalar instructions to efficiently handle irregular dimensions, and leveraging strided segmented load/store vector intrinsics to sustain throughput even in non-ideal layouts. These optimizations are not just academic; small inefficiencies in GEMM propagate directly into AI inference latency and energy. By focusing on edge cases and architectural nuance, we can unlock meaningful improvements for real-world workloads. These optimizations give substantial gains; for example, a 6 x 3072 × 3072 SGEMM MatMul efficiency improves from 23.5% to 68.7% of the peak.

In early 2026, the openEuler community, together with the Institute of Software, Chinese Academy of Sciences (ISCAS) and industry partners, released the openEuler 24.03 LTS SP3 for RISC-V server bring-up. The release aligns with ongoing RISC-V Server Platform efforts and adds practical support for RVA23-related vector and virtualization features across toolchains, user-space components, and the kernel. A central part of this work is RVCK (RISC-V Common Kernel), a shared kernel baseline designed to reduce duplicated per-vendor enablement work and improve reuse across platforms. This talk presents the engineering lessons behind that effort, including cross-vendor coordination, upstream collaboration, and the challenges of building a reusable software baseline for server-class RISC-V systems.

The Atomic Cryptographic Extension (ACE) is an ISA extension to enable secure cryptographic implementations. ACE separates key provisioning from key usage, enabling distinct environments to perform the two functions. For example, keys could be delivered to user software by a TEE applet. Unlike existing round-based AES extensions, which inherently expose key material, ACE performs cryptographic operations atomically. Keys are associated with metadata that ties them to specific algorithms and usage policies. Keys and metadata are bonded to each other by writing them in Context Registers (CRs). The contents of CRs can only be exported in encrypted and authenticated form for secure re-import, enabling secure context switches and VM migrations. ACE is work in progress of the High Assurance Cryptography (HAC) TG of RISC-V International.

This work presents the first design and evaluation of the standard RISC-V Control-Flow Integrity (CFI)
extensions. The Zicfiss and Zicfilp extensions protect vulnerable software from control-flow hijacking through shadow stack and landing pad mechanisms. We integrate dedicated hardware support for both extensions into the open-source CVA6 core. Synthesis in 22 nm FDX technology shows only 1.0% area overhead, while evaluation on the MiBench automotive benchmark subset reports up to 15.6% runtime overhead.

Inference engines are specialized software systems designed to execute pre-trained Machine Learning models. ONNX Runtime (ORT) emerges as a leading open-source inference engine for the Open Neural Network Exchange (ONNX) format, allowing models to be deployed regardless of the framework in which they were trained.
While ORT provides a flexible architecture for deploying models across diverse hardware, it currently lacks architecture-specific optimizations for RISC-V. Consequently, computationally intensive tasks such as the convolution operation—which accounts for the majority of inference time in Convolutional Neural Networks (CNNs)—suffer from hardware underutilization by relying on standard scalar instructions. In this paper, we address this gap by proposing an optimized convolution implementation leveraging the RISC-V Vector Extension (RVV) and integrating it as a custom Execution Provider in ORT. We evaluate our solution on a Banana Pi BPI-F3 board across six standard reference CNN models. Experimental results show that our RVV-accelerated implementation achieves speedups of up to 3x compared to the official scalar ORT release, significantly improving CNN inference performance on RISC-V platforms.

In the AI era, the RISC-V architecture represents a transformative force due to its inherent modularity and extensibility. However, the transition from hardware potential to a production-ready AI ecosystem is fraught with challenges, primarily the fragmentation of hardware-software interfaces and the relative immaturity of the AI software ecosystem. As a leading Tier-1 operating system community, openKylin serves as the critical architectural glue, addressing these obstacles by empowering the RISC-V AI landscape through foundational OS construction, software stack optimization, and application innovation. By harmonizing hardware diversity with a unified software infrastructure, openKylin not only lowers the barrier to AI deployment but also defines a scalable roadmap for RISC-V across multi-scenario environments, transforming RISC-V into a premier, open-standard architecture for the global AI revolution.

This presentation introduces Nuclei’s RISC-V automotive ecosystem, delivering ISO 26262 ASIL-D safety and full-spectrum CPU IP for modern vehicle electronics. As a leading Chinese RISC-V provider, Nuclei offers scalable cores from ultra-low-power N-class to high-performance UX-class, plus NA-series automotive cores meeting ASIL-B/D requirements. With 18+ customers, 5+ mass-production projects, Nuclei’s solutions power LiDAR, radar, MCU, and ADAS applications, enabling safe, scalable RISC-V adoption for next-generation automotive systems.

In this paper, we present the system-level integration and evaluation of IPECC, an open-source side-channel-resistant ECC hardware accelerator developed by by the French national agency ANSSI, is integrated into the CVA6 RISC-V SoC and prototyped on a Genesys 2 (XC7K325T) FPGA. Using the libecc cryptographic library, we evaluate eight signature scheme/curve combinations in three configurations: software-only execution, hardware acceleration without countermeasures, and fully protected hardware acceleration. With all countermeasures active, IPECC reduces ECDSA P-256 signature latency from 1.13 s to 180 ms (a 6.3x speedup), reaching 7.8x for Schnorr-based schemes and scaling up to 9.1x for P-521. On the FPGA target, the countermeasure overhead varies drastically from +3% (hash-dominated EdDSA) to +279% (Schnorr-based schemes). We demonstrate that this variance is fundamentally driven by the physical True Random Number Generator (TRNG) latency and each protocol’s specific reliance on scalar multiplication. In its compact P-256 configuration, the accelerator occupies only 4.2% of the FPGA LUT fabric (3,602 LUTs, 12 DSP48E1). This platform provides a reproducible basis for benchmarking ECC acceleration and side-channel countermeasures on RISC-V SoCs.

We present the development flow and platform we have built to support CHERI development and ratification of the RVY extension. CHERI is an ISA extension providing hardware support for capabilities - unforgeable memory references embedding a memory address as well as bounds and permissions metadata. It enables spatial and temporal memory safety by design. We have developed a comprehensive workflow used to validate the proposed RVY extension both for functionality and performance. We maintain and make use of a formal golden model, which we leverage for design verification effort through directed-random fuzz testing of architectural features under development. We gather core CHERI functionalities in a reusable RTL library to use across multiple commercial and research implementations, maximising reuse of verification effort. We build and boot soft-core images of CHERI-enabled systems on FPGA at scale, enabling software development and performance
evaluation of RV64Y microarchitectures and software stacks. This infrastructure has enabled rapid convergence for the development of the RVY extension with a high level of confidence in functionality and performance. We are now making use of this infrastructure to further enable various streams of research.

The fragmented RISC-V ecosystem demands portable, high-performance code generation for the Vector Extension (RVV 1.0). Upstream MLIR (LLVM 22.0) lacks two critical lowering stages needed for this: it cannot flatten dynamic memref ma- trix references into C pointers, nor emit Vector-Length-Agnostic (VLA) RVV intrinsics. This paper closes that gap with a six-stage hybrid MLIR–xDSL compilation workflow that automatically generates parameterized, hardware-aware C micro- kernels for GEMM entirely in Python, without modifying the MLIR C++ codebase. On a COTS BananaPi F3 board (SpaceMiT K1, 256-bit RVV 1.0), we show: (i) isolated micro-kernels match or exceed hand-written reference code (0.98×– 1.05×), peaking at 16.2 GFLOPS at the optimal 16×15 tile; (ii) on BERT-Large transformer layers (B1–B5), generated micro-kernels consistently surpass OpenBLAS, reaching up to 12.2 GFLOPS against the baseline’s 5.1 GFLOPS (a 2.4× speedup) and maintaining an average 15–27% performance advantage across all layer dimensions.

New RISC-V CPU cores are released every year, and while these cores typically conform to standardized RISC-V ISA profiles, vendors frequently introduce additional proprietary extensions. This growing diversity makes it difficult for developers to accurately determine the exact instruction sets supported by a specific CPU core, thereby complicating the selection of appropriate toolchains, firmware, and operating system images. The RuyiSDK Package Manager addresses this challenge by aggregating information on RISC-V CPUs, MCUs, and development boards together with their corresponding toolchains, firmware, and system images. It establishes a comprehensive mapping between CPU architectures, development boards, and required software resources. This mapping is maintained in a structured packages index, which provides a unified, metadata-driven representation of RISC-V hardware and software resources, along with associated download links. This paper presents the overall architecture and design of the RuyiSDK Package Manager, focusing on three core components: package management, virtual environment isolation, and device provisioning. The system currently supports most commercially available RISC-V development boards. Beyond toolchain integration, it lays the foundation for IDE integration and other developer utilities. By streamlining access to software resources and standardizing development workflows, the system lowers the barrier to entry for RISC-V software development, facilitates developer onboarding, and improves visibility into software support across heterogeneous RISC-V platforms.

As more complex RISC-V devices emerge, the verification of the sub-systems in which they are integrated becomes more of a concern. Ensuring that overall system-level operation executes correctly is as critical as the behavior of the devices themselves. Sub-system verification is generally a complex procedure that involves multiple components, issues such as load-store behavior, coherency, performance bottlenecks and hazards, and other factors in addition to the functional behavior of the components operating together. Verifying these issues requires advanced test solutions. This talk will discuss how the requirements of this verification process may be met, which could involve processor providers and end-users. Interaction around the AIA and the IOMMU sub-system components will be leveraged to show examples of sub-system behavior verification.

As digital systems become ever more interconnected, the global cost of cybercrime continues its steep rise. 70% of the vulnerabilities leading to these attacks stem from memory safety issues, which have remained persistent for several decades. After 15 years of research, the Capability Hardware Enhanced RISC Instructions (CHERI) technology has matured into a practical solution to this challenge now moving toward standardization within RISC-V.
While CHERI has been validated through extensive academic research and multiple industrial prototypes, the next critical step is a broad, sustainable transfer from research labs into commercial RISC-V products. This paper outlines how collaborative ecosystem building—across academia, industry, open-source communities, and government stakeholders—is essential to enable the adoption of CHERI on RISC-V. The CHERI Alliance plays a central role in this transition, acting as a bridge, amplifier, and catalyst for a memory safe ecosystem.

ChaCha20 is a high-performance stream cipher widely deployed in TLS and SSH, typically combined with Poly1305 for authenticated encryption. This paper presents a practical vectorized implementation of ChaCha20 using the RISC-V Vector (RVV) extension, with complete engineering code in the Go ecosystem. We outline how ChaCha20's add--xor--rotate structure maps to RVV instructions and describe a fully vectorized design covering register allocation, rotation implementation, and 64-byte block processing. Experiments on a real RISC-V 64 platform (Spacemit X60) show up to 1.5X throughput improvement on large data blocks and a 35.58% geometric mean speedup over the generic Go implementation. The implementation is suitable for direct integration into open-source cryptographic stacks on RVV-enabled RISC-V platforms.

The Mambo XiaoXin Robot uses the StarrySky C2-Pico open-source development board as its core controller, paired with ASR-PRO voice recognition module, forming a compact robotic system that integrates motion control, voice interaction, and intelligent response.
The StarrySky C2-Pico board is equipped with the RetroSoC chip independently developed by the ECOS(EDA, Chip, One Student One Chip, System) team. This chip is fabricated using the ICSprout 55 nm open-source PDK process flow and represents a technological achievement that combines the open instruction set RISC-V, open-source EDA, open-source IP, and open-source PDK. Its functionality and performance are benchmarked against the low- to mid-end products of ST’s F1 series.
Internally, the chip integrates the classic lightweight open-source RISC-V processor core PicoRV32, fully implementing the RV32IMC instruction set architecture, with a maximum clock frequency of up to 72 MHz. The chip includes 128 KB of on-chip SRAM, while the board further expands storage with 8 MB PSRAM and 16 MB SPI Flash, forming a multi-level memory system. In addition, the chip integrates a rich set of open-source peripheral drivers, including UART, SPI, I2C, PS/2, PWM, GPIO, timers, and more, meeting diverse embedded development requirements.

This paper presents Sail-RISCV-WASM, which addresses three common limitations of existing browser-based RISC-V tools: fragmented capabilities, limited configurability, and disconnected build/debug pipelines. The system uses sail-riscv as its semantic baseline and compiles it to WebAssembly, forming a three-layer architecture in a pure browser environment: a Sail decode/execute layer, a toolchain layer (gas/ld/objdump), and a metadata layer based on the RISC-V UDB. Based on this architecture, the paper defines two core workflows. The first is configuration-sensitive online encode/decode with instruction metadata navigation for cross-configuration behavior comparison. The second is an in-browser assemble-to-ELF, execute, and interactive debugging loop, supporting instruction-level stepping, source-line stepping, synchronized source/disassembly views, and register/memory tracing. Results show that the system provides a complete single-page flow from exploration to build to diagnosis, with strong extension coverage and configuration flexibility.

The RISC-V architecture has experienced rapid growth in recent years, evolving from an academic research project into a global ecosystem spanning industry, academia, and open-source communities. However, achieving competitive application performance across the diverse RISC-V microarchitectures requires a mature compiler infrastructure capable of realizing the performance potential of the underlying hardware. In this work, we present XSCC, a high-performance compiler built on LLVM 19.1.0, designed to meet industrial-grade performance demands while actively contributing to open-source ecosystem development. XSCC performs a systematic cross-architecture optimization analysis, distilling compiler insights from mature architectures into a cohesive set of optimizations for RISC-V, including enhanced loop transformations, memory access reordering, and microarchitecture-specific scheduling models. Four of these optimizations have been upstreamed to the LLVM project. Experimental evaluation demonstrates consistent improvements over baseline LLVM 19 and GCC 12, achieving up to 1.14x speedup on SPEC CPU 2006 FP on the simulated XiangShan KMHv3 and up to 1.30x speedup on SPEC CPU 2006 INT on commercial RISC-V hardware SpacemiT X60.

Accelerating the Future Computing with RISC-V

Vector architectures are widely used in multicore systems to exploit data-level parallelism, but their bursty, high-bandwidth memory behavior can exacerbate contention for shared resources such as caches and DRAM, increasing timing variability. This paper introduces the principles behind InterFinder, a unified interference analysis framework for RISC-V vector architectures that combines compiler-based analysis, formal SW/HW modeling, and microarchitectural abstraction to support interference-aware timing analysis.

The PQC4eMRTD is a CSA (Coordination and Support Action) project funded by the European Commission, which focuses on monitoring and influencing the standardization space of Post Quantum Security with a particular focus on machine readable travel documents (MRTDs) such as national identification cards, passports and other personal documents. These types of documents include tiny microprocessors which interact with RFID devices in order to read sensitive personal information (e.g. biographic and biometric data) stored securely on the document, and allows the authentication of a person. Existing documents use conventional cryptographic algorithms which will be vulnerable to quantum computer attacks, especially considering the long validity period of such documents. For this reason, there is an interest in planning their migration to post quantum cryptographic algorithms in a standardized way. This abstract focuses on the work performed in the project within RISC-V systems, which extends to other types of resource constrained systems.

We present the studies leading up to the temporal safety support included in the RV64Y “CHERI” capability RISC-V extension. Memory safety enforcement is increasingly important for new programs, languages, and architectures. RV64Y enforces spatial memory safety natively, and provides the necessary invariants to enforce temporal safety in software.
To ensure that RV64Y systems can enforce temporal safety with reasonable performance and memory overhead, we have reproduced experiments from previous CHERI research, optimised CheriBSD revocation support, and explored simplified state machines for virtual memory pages encoded in Page Table Entry (PTE) bits. We managed to optimize revocation in CheriBSD to reduce overhead in Spec2006 by 12%. We then explored the simplest PTE encoding with generational capability read support, and found that they incurred an overhead of about 33% over the optimised baseline, justifying the inclusion of generational capability dirty states in the frozen RV64Y specification. Finally, we discuss ongoing work that has the potential to further optimize temporal safety for RV64Y with vendor-specific or future ratified extensions.

This work implements two ports of the Real-Time Operating System RODOS on RISC-V. The first port targets QEMU with the RV32E_ZICSR ISA variant. This enables easy development and testing without requiring additional hardware. The other port targets the BeagleV-Ahead board, which is an open-source RISC-V single board computer. RODOS provides benchmarks that give a rough estimate of the performance. These benchmarks are carried out on the BeagleV-Ahead board and compared to results of already existing ports. Our benchmarks show that this RISC-V port on the BeagleV-Ahead is about 20% faster than other boards like an STM32F4. This shows that RISC-V is a promising platform for future applications of RODOS.

This paper provides a quantitative analysis of the costs and benefits of integrating a dedicated hardware accelerator for the Post Quantum Cryptography (PQC) algorithm ML-KEM into a 32-bit RISC-V SoC. We compare a software-only implementation on the CV32E40P core against a full-hardware datapath offloading the entire algorithm. We implemented the system on a 22 nm ASIC chip, and we measured the results: the dedicated hardware achieves a 139x speed-up over the software baseline. This performance gain requires an area overhead of 301 kGE, representing only a 6% increase in the total SoC silicon footprint. This study provides a data-driven assessment of the silicon-to-latency trade-off for Post-Quantum Cryptography (PQC) in resource-constrained RISC-V systems.

RISC-V is a major breakthrough in the computing ecosystem. It open
opportunities for hardware research, innovation for
industry. Researcher or industrial can customize a CPU core for a
given specific application, thus provide industrial advantage.

It would be strange not to take advantage of this opportunity to
revisit the ecosystem of software tools.

In this article, we propose a new compiler for generating a part
of the binary code at runtime.

This has several advantages: (1) generating code by leveraging
knowledge of user data which provide speed optimization, (2)
generating code with knowledge of the accelerators available on a
given platform, and (3) taking advantage of unconventional
accelerators specific to a computing platform.

The 2 later points are specifically interesting for the RISC-V
community which already show a wide variety of platforms.

RISC-V provides an open and extensible ISA foundation, but its adoption in desktop and server environments remains limited by the existing x86-64 software ecosystem. Dynamic binary translation (DBT) is a practical compatibility layer, yet translating CISC-style x86-64 binaries to RV64 often introduces substantial dynamic instruction-count inflation. Reducing translated instruction count is a necessary first-order condition for improving DBT performance when CPI and frequency changes are bounded. This paper presents a micro-op-guided methodology for analyzing and reducing x86-64-to-RV64 translation overhead. We use x86 micro-ops as a reference for the intrinsic execution complexity of source instructions. This allows us to distinguish unavoidable CISC instruction complexity from additional semantic compensation introduced by cross-ISA translation. Based on this model, we estimate optimistic instruction-count lower bounds for specific optimization classes and identify indirect control-flow resolution as a major source of semantic inflation. We then propose a lightweight Jump Table Cache (JTC) extension for RISC-V and evaluate it in gem5. A 1024-entry, 4-way JTC achieves over 90% hit rates on most SPECint workloads and reduces estimated execution cycles by 6.0%--14.6%.

Memory zeroing is a common operation for enforcing system security. Zeroing is used to clear memory contents to prevent information leakage and initialise memory contents to prevent uninitialized memory access. Vendors such as Intel and ARM support fast memory zeroing instructions to improve system performance efficiency. The cache management operation (CMO) extension has also been recently been added to RISC-V which can be used for improving memory zeroing performance. Compared to the standard systems, memory zeroing is more frequently used in capability systems such as CHERI to prevent capability leakage. In this work, we evaluate different memory zeroing strategies on CHERI, and implement hardware support for improving the performance and efficiency of memory zeroing on CHERI-Toooba: a CHERI-extended RISC-V CPU.

Tenstorrent is bringing a differentiated RISC-V story to market by combining open, licensable CPU IP with the real-world experience of building and shipping AI systems at scale. This presentation highlights how Tenstorrent turned an internal need for high-performance, customizable compute into a broader IP business, and why that matters for customers seeking greater roadmap control, architectural flexibility, and freedom from vendor lock-in. Backed by proven silicon, production systems, and RISC-V deployments measured in the millions of cores, Tenstorrent’s approach shows how open IP can move beyond theory to enable scalable, production-ready innovation across CPUs, AI accelerators, chiplets, and full-system platforms.

We have previously demonstrated that it is practical to bring up ExecuTorch on a low power bare metal microcontroller. ExecuTorch is a project derived from the PyTorch AI framework for inference on embedded devices using traditional eager (“interpreted”) evaluation of AI models. In this paper, we provide a short overview of how to run ExecuTorch on a bare metal microcontroller. We then illustrate the features of 32-bit RISC-V [4] which make it attractive for use in edge AI applications, using the Open Hardware Foundation’s CORE-V CV32E40Pv2 microcontroller as deployed in a real world design by two of the co-authors and their colleagues at . We have now ported IREE for the same platform. IREE is a Linux Foundation experimental project, which uses lazy (“compiled”) evaluation of AI models, with LLVM MLIR as an intermediate representation. We give a short overview of how to run IREE on a bare metal microcontroller, and then assess what aspects of 32-bit RISC-V make it attractive for IREE. We conclude by comparing the feasibility of using IREE instead of ExecuTorch and an assessment on the performance of both when carrying out AI inference.

We present our work on porting CHERI to the open-source Bao hypervisor targeting the RISC-V architecture. A preliminary evaluation of our implementation shows a 30.2% increase in code size, an additional 1 KiB of runtime memory usage, a 20% increase in boot time, and a 13.43% increase in interrupt latency. To the best of our knowledge, this is the first publicly available implementation of a hypervisor incorporating CHERI for RISC-V that supports both CHERI and the RISC-V hypervisor extension. The port is publicly available as an open-source artifact for the RISC-V and CHERI communities.

The complexity of modern electronics systems and their behavior in harsh environments, demanding performance, fault-tolerance capabilities, and energy efficiency, proves the need to design and implement systems adaptable to applications with mixed-criticality requirements. The Extensible Reliable Offloading Solution (EROS) has been developed as a HW-based accelerator template capable of addressing these requirements. It is compatible with several RISC-V cores from the OpenHW Foundation and eases the integration of both MM accelerators and ISA extensions using CV-X-IF coprocessors. The platform offers a safety wrapper, allowing the selected core to be configured at design time and runtime in different operational modes, from single core execution to fault-tolerant operational modes such as TCLS, DCLS, and staggered. It also provides methods for error detection and recovery. The EROS solution has been implemented as a safety accelerator island in the X-HEEP system, a RISC-V microcontroller platform conceived for ultra-low power scenarios, creating the resulting X-EROS system. This demo evaluates X-EROS, which has been taped out in TSMC 65nm LP technology. The platform is evaluated through performance analysis results obtained from the execution of an AES-256-CBC algorithm. In conjunction, a controlled error injection is performed to prove the functional detection and recovery capabilities. The overall system power consumption is measured to show the different power profiles under different modes of operation, demonstrating the capacity of the platform to adapt itself not only to fault-tolerance requirements but also to low-power requirements.

This work introduces a compatible acceleration approach for AES encryption that retains the standardized ISA interface while enhancing execution time for AES-128 on 32-bit processors, including the key-schedule phase. By reformulating the behavior of existing Zk instructions without altering their opcodes, we preserve binary and source compatibility with software written for Zkne, without the performance losses of having to perform key expansion only by software. The result is an integration strategy suitable for constrained IoT or automotive devices that delivers improved throughput with reduced area overhead, enabling systems to realize the intended benefits of RISC-V’s cryptographic extension without sacrificing portability and standardization.

The x86-64 instruction set has a long history of backwards compatibility, and a large body of performance-intensive software exists that may never be ported to RISC-V. In this paper, we implement AVX and AVX2 support in the felix86 JIT-recompiling emulator using RVV 1.0, and the performance benefit of enabling AVX and AVX2 support in the emulator is measured and compared with the benefit observed on native x86-64 hardware using SIMD-intensive workloads. We find that the percentage-wise improvement from enabling AVX/AVX2 in x86-64 software is closely matched on RISC-V hardware when AVX is emulated with RVV 1.0, demonstrating that felix86's vector translation faithfully captures the performance characteristics of AVX and that the RVV instruction set is capable of efficiently emulating AVX.

As RISC-V moves from experimental silicon to mass-market industrial applications, the availability of proven, safety-certified Real-Time Operating Systems (RTOS) is a key enabler for adoption. Eclipse ThreadX (formerly Azure RTOS) has long been a cornerstone of the embedded industry. Yet, its immature support for the RISC-V ISA, particularly 64-bit implementations, remained a barrier for high-performance adoption.

In this session, you will learn how 10xEngineers, in collaboration with the Eclipse ThreadX project team, brought first-class RISC-V support to the ThreadX kernel. You will go on a deep dive into the architectural challenges of porting the kernel's core components to both RV32 and RV64, including context switching, interrupt nesting, and timer management tailored for the RISC-V privileged architecture. You will also explore the practical enablement of this port on the SpacemiT K1 SoC (Banana Pi BPI-F3), bridging the gap between virtual prototyping in QEMU and physical hardware deployment. Finally, you will gain insights into the low-level kernel modifications required for RISC-V compliance and discover a roadmap for deploying ThreadX in the next generation of RISC-V embedded systems.

Post-Quantum Cryptography (PQC) is moving from algorithm selection to deployment, where performance, energy, and portability are key constraints, especially on embedded and IoT-class processors. Many PQC schemes stress general-purpose cores with large arithmetic workloads and heavy memory traffic. Instruction-set extensions (ISE) offer a practical middle ground: they speed up dominant kernels while preserving programmability.
In this context, we target post-quantum digital signatures, which remain under active evaluation, as reflected by NIST's 2023 call for additional schemes. We focus on CROSS, a code-based signature built from zero-knowledge proofs and the Restricted Syndrome Decoding Problem, and present CIRCE: a RISC-V–integrated extension connected through the Core-V eXtension Interface (CV-X-IF). CIRCE supports both R-SDP and R-SDP(G), runs across all official parameter sets without hardware retuning, and achieves an average 2x speed-up on a Zynq UltraScale+ FPGA with an ultra-compact footprint (down to 800 LUTs / 100 FFs).

CHERI extends conventional ISAs with hardware-enforced capabilities to provide fine-grained memory protection and its integration in RISC-V is gaining momentum with RVY. As adoption grows, implementations must be evaluated to ensure working CHERI protection mechanisms. We show that existing memory-corruption exploit implementations do not directly carry over to CHERI-enabled architectures, and that observed exploit failures (i.e., unsuccessful exploits) do not necessarily imply effective protection. To resolve this ambiguity, we propose a methodology that temporarily disables CHERI enforcement within a RISC-V VP. Comparing exploit behavior with and without CHERI enforcement under otherwise identical conditions makes it possible to distinguish exploit failure from effective CHERI protection.

Small Language Models (SLMs) are increasingly critical for edge AI, yet their performance on RISC-V requires rigorous profiling to identify architectural bottlenecks. This work evaluates the performance of SLMs including Gemma3, Llama-3.2, Qwen-2.5, DeepSeek, and Phi-3.5 on the Tenstorrent Ascalon RISC-V Core. We developed a profiling methodology to analyze workload distribution, which revealed that Matrix Multiplication (MatMul) contributes ~90% of total compute across all evaluated models. Given the computational complexity of running full-model emulations, we extract these critical kernels for targeted benchmarking. Our implementation on the HAPS platform achieves significant performance leaps over standard baselines. FP32 execution, utilized for maximum precision, was optimized by transitioning from traditional SGEMM to a new high-performance implementation. Simultaneously, INT8 performance, targeted for efficient inference, was accelerated by migrating from standard RVV to a specialized IGEMM (with a VQDOT) implementation.

The adoption of capability-based architectures such as Capability Hardware Enhanced RISC Instructions (CHERI) in constrained RISC-V systems raises open questions regarding performance overheads, verification complexity, and practical evaluation methodologies. Virtual prototyping provides an effective means to explore these questions early in the design process, before committing to Register-Transfer Level (RTL) implementations. In this paper, we present a CHERI-enabled RISC-V Virtual Prototype (VP) targeting constrained embedded systems and demonstrate its use for early architectural evaluation. We describe VP-based verification workflows for both software and hardware and report early performance insights focusing on CHERI tagged memory management. Our experiences highlight the benefits of VPs for guiding CHERI adoption decisions and identify practical challenges, including the need for lightweight benchmarks suitable for constrained environments.

We present HBENCH, a microbenchmark suite for instruction-level characterization of RISC-V (scalar and RISC-V Vector Extension (RVV)) and x86 (scalar and Advanced Vector Extensions (AVX)2), enabling accurate simulator performance models. HBENCH maps scalar and vector microkernels to gem5 latency groups and reports latency and peak throughput for Floating-Point (FP)32, FP64, and Integer (INT) operations. We evaluate a Banana Pi F3 (SpacemiT K1, X60, RVV 1.0, 256-bit Vector Length (VLEN)) and derive a gem5-compatible performance model. Coverage is validated against RIVEC workloads using dominant RVV instruction mixes.
Our results span over 329 microkernels, providing per-latency-group latency and throughput, cache hierarchy probes, and Instructions Per Cycle (IPC)-based classification, demonstrating HBENCH’s ability to support high-accuracy instruction-level performance modeling.

Recent advances in quantum computing threaten conventional public-key cryptographic algorithms, necessitating the adoption of post-quantum schemes such as ML-KEM and ML-DSA. The performance of these schemes is constrained primarily by two computationally intensive kernels: the Number-Theoretic Transform (NTT) and the Keccak-f1600 permutation.

This work introduces PQCUARK, a scalar RISC-V Instruction Set Architecture (ISA) extension that accelerates both kernels through two tightly integrated units: a packed-SIMD butterfly unit for the NTT and a Keccak engine capable of delivering two rounds per cycle with direct access to the Load-Store Unit.

Implementation of PQCUARK on an RV64 core and deployment on an FPGA achieves up to a 10.1× speedup over NIST reference software and a 4.2× improvement over optimized implementations, surpassing state-of-the-art solutions by factors ranging from 1.4× to 12.3×. ASIC synthesis in GF22-FDSOI demonstrates only an 8% core-area overhead at 1.2 GHz, with no impact on the critical path.

Efficient deployment of Deep Learning (DL) models on RISC-V-based multi-core platforms remains a significant challenge, especially when multiple models with heterogeneous structures and precision requirements must run concurrently. Existing frameworks offer optimized execution for single-model inference but lack support for multi-model scheduling, as well as priority-based resource allocation.
In this work, we extend the capabilities of such frameworks by formalizing the problem of multi-model, multiprecision inference scheduling on constrained many-core architectures like Parallel Ultra-Low Power (PULP). We define a scheduling space where multiple Deep Neural Networks (DNNs), varying in size, type and precision, compete for limited computing and memory resources. We introduce a simple, priority-aware scheduling layer that allocates cores and memory tiles across models, aiming to either minimize overall inference latency or find a tradeoff satisfying each model’s deadline.
To demonstrate the effectiveness of our approach, we leverage the existing Deployment Oriented to memoRY (DORY) framework, and apply a greedy scheduling strategy. We conducted experiments with several models across several tasks and showed that even basic scheduling policies can significantly improve latency, core utilization, and memory efficiency over static and sequential baselines.

As RISC‑V enters high‑performance computing (from traditional data‑center servers to edge infrastructure, telecom systems, and industrial compute platforms) a unified platform definition is essential. Without a consistent hardware and firmware contract, system‑software vendors face fragmented bring‑up, slowing ecosystem adoption.

The RISC‑V Server Platform Specification solves this by defining a clear baseline that supports high‑performance RISC‑V platforms. Built by composing existing standards such as the RVA23 profile, Server‑class SoC requirements, UEFI/ACPI boot via BRS, SBI interfaces, and modern security foundations including roots of trust, secure boot, attestation, and BMC‑based management, the specification enables OS and hypervisor developers to target a single portable binary.

This talk outlines the goals, structure, and key requirements of Server Platform Specification 1.0, explaining how it reduces fragmentation, accelerates system‑software portability, and provides a stable foundation for interoperable, production‑ready RISC‑V platforms across diverse deployment environments.

Across applications from low-power embedded to High Performance Computing, the success of the RISC-V ISA is directly tied to the maturity of software support and enablement. In this panel we bring experts together from across the RISC-V ecosystem and beyond, to debate the current state of the RISC-V software enablement and discuss future priorities.

RISC-V already has strong compiler support, but what have been the most recent performance optimizations, and what do we need to prioritize in terms of next developments?
What does compiler support look like for specific use cases, like safety certification for automotive, or vectorization for AI?
Rust is increasing in use across Linux and Zephyr. What is the status of RUST support on RISC-V
How can the RISC-V ecosystem and the Linux development team work together more efficiently?
How mature is the support for the open source software ecosystem beyond compilers?
What software infrastructure are we missing and what should we prioritize?
What does software support look like as we move beyond profiles to platforms?
What does software compatibility look like for a single ISA that scales from MCU to HPC, but relies on specific profiles and extensions?
How will the use of AI in software development accelerate porting to RISC-V?

Moderator:
Tom Gall - RISC-V International
Panelists:
Greg Kroah-Hartman - Linux Foundation
Lars Bergstrom - Google
Paul Carpenter - Barcelona Supercomputing Center

this panel will provide broad insight into the future of the software enablement on RISC-V!

This paper introduces a new version of the CREATOR tool. CREATOR is a web-based simulator that lets users code, compile, and execute assembly-language programs. The architectures that can be simulated in CREATOR are MIPS and RISC-V. Until now, CREATOR allowed the simulation of the RISC-V architecture with a reduced instruction set (RISC-V IMFD), but this has changed thanks to Sail. Sail is an instruction specification language used by RISC-V to define both its architecture and the entire instruction set. This language has enabled the development of a complete RISC-V architecture simulator for web environments, without requiring any installation. It also allows users to develop their own instructions for research purposes or to adapt the implementation of existing ones for their own industrial purposes. This simulator also integrates an editable cache memory module into its architecture to explore the functioning of the architecture in greater depth. The tool includes a multi-file code-editing module that allows users to import, export, and edit assembly-language programs; an integrated compiler; and a program-debugging module during execution. To develop this simulator for web environments, the simulator implementation in Sail was exported to a high-level language (C), and the exported code was transpiled with Emscripten to generate executable code for web environments while maintaining performance, as if it were a native application.

Post-Quantum Cryptography (PQC) is rapidly becoming a security requirement, and ML-KEM (FIPS 203) is emerging as a foundational primitive for future secure systems. On RISC-V platforms, performance evaluations frequently emphasize custom extensions or dedicated accelerators, while the optimization potential of the standard ISA remains comparatively underexplored. This paper establishes a rigorous performance baseline for the main computational kernels of ML-KEM using only the standard RISC-V Vector Extension (RVV). Rather than relying on handwritten assembly, we apply targeted C-level program transformations that systematically enable effective compiler autovectorization, achieving up to a 10× reduction in instruction count for NTT while preserving portability across all RVV-compliant implementations.

Hardware-assisted in-process compartmentalization is an effective method for addressing security threats within complex software applications. This paper proposes DASICS, an efficient design of hardware-assisted in-process compartmentalization, including flexible permission management, sufficient security metadata protection, complete resource access control, and little hardware-to-software ABI modification requirements. DASICS divides the process into trusted and untrusted region and uses boundary registers and user-level interrupts to achieve dynamic permission management, thereby avoiding the overhead of privilege-level switching in traditional methods.
We implemented a hardware prototype of DASICS on the RISC-V XiangShan out-of-order processor and validated its effectiveness on FPGA. Experimental results show that DASICS incurs an average performance overhead of only 1.53% in SPECint2006 tests while effectively defending against common vulnerabilities such as stack/heap overflows and control-flow hijacking in security test suite.

RISC-V AI acceleration faces a combinatorial explosion: hundreds of kernel variations across shapes, data types, and vendor platforms create unsustainable complexity. We present an end-to-end compilation solution fusing ML graph compilation with Triton DSL kernel compilation in a unified MLIR-based framework targeting RISC-V scalar (RV64IM) and vector (RVV) instruction sets.

With the rapid evolution of RISC-V extensions such as Vector, Matrix, and other custom instructions, RISC-V platforms are becoming capable of executing modern AI models. However, achieving high-performance deployment while maintaining a unified software stack across diverse extensions remains a key challenge. This paper introduces RuyiAI Buddy Compiler, an end-to-end AI compiler designed to provide a unified interface for AI model integration, multi-level compilation optimizations, and extensible code generation targeting diverse RISC-V extensions. Buddy Compiler adopts a multi-level architecture consisting of a frontend, middle-section, and backend, enabling reusable high-level optimizations while supporting specialized backends for RISC-V architectures. The frontend provides a graph infrastructure that interfaces with mainstream AI frameworks and converts imported models into a unified representation expressed with high-level MLIR dialects. The middle-section is built on MLIR and performs multi-level compilation optimizations, including operator fusion, memory access optimization, and vectorization. The backend implements dedicated MLIR dialects for RISC-V extensions, such as RVV, IME, AME, and Gemmini, and performs target-specific code generation. Through multi-level compilation, the RuyiAI Buddy Compiler and its runtime system enable efficient deployment of AI models on RISC-V platforms, achieving performance comparable to manually optimized implementations such as llama.cpp, triton-cpu, and Tenstorrent TTNN.

FREESS (Free Educational Superscalar Simulator) is an open-source teaching environment for instruction-level parallelism in a RISC-V-inspired superscalar processor. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering in a Tomasulo-style machine. The simulator exposes the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation, so the evolution of the hardware state can be followed on screen and reproduced on paper. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed easily, enabling direct comparison among alternative superscalar organizations. The tool has supported Advanced Computer Architecture teaching for about fifteen years and is publicly available on GitHub.

As RISC-V expands into embedded critical domains like IoT and automotive automotive require predictable isolation mechanisms. Traditional MMU-based virtualization is often impractical for these resource-constrained environments due to the latency of page-table walks and significant memory overhead. In contrast, MPU-style region-based protection offers deterministic access checks with minimal footprint, making physical memory protection essential for secure, mixed-criticality systems.

While RISC-V PMP provides such mechanisms at machine privilege level, modern embedded software stacks, including RTOSes, separation kernels, and lightweight hypervisors, require similar capabilities at supervisor level. The proposed Supervisor-mode Physical Memory Protection (SPMP) extensions address this gap by allowing supervisor software to define access permissions over physical memory regions, enabling robust compartmentalization of software components in systems without virtual memory.

Virtualization further increases the need for such mechanisms. Embedded hypervisors are increasingly used to consolidate multiple operating systems or software domains on a single microcontroller-class platform while maintaining strict isolation guarantees. To support this model, SPMP is being extended to interact with the RISC-V Hypervisor extension through a two-stage protection approach (vSPMP), enabling the hypervisor to enforce global isolation while allowing guest operating systems to manage their own protection domains.

This talk presents the current status of the SPMP and SPMP for Hypervisor specifications, their architectural design and rationale, and their integration with the RISC-V privilege architecture. We will discuss the design rationale, implementation considerations, and potential deployment scenarios in secure IoT microcontrollers and automotive mixed-criticality systems.

The emergence of quantum computers threatens traditional cryptographic schemes, requiring the development of post-quantum algorithms. In this paper, we study the performance of the Hamming Quasi-Cyclic (HQC) scheme, the new Key Encapsulation Method (KEM) ratified by NIST in March 2025. We analyze different implementation approaches for the Sargantana RV64GBV core using the standard RISC-V bit-manipulation (B) and vector (V) extensions. We compare reference implementations against auto-vectorized code and then provide an overview of how to analyze and profile these implementations using RAVE.

Contrail AIX™ is the world's first RISC-V AI Execution Platform, purpose-built for the next phase of artificial intelligence as the industry transitions from training models to deploying and executing intelligent applications at scale. Unlike traditional AI infrastructure, which separates CPUs for system management and GPUs for model processing, Contrail AIX is designed to support emerging workloads such as AI inference, reasoning, agentic AI, retrieval-augmented generation (RAG), autonomous systems, and physical AI, all of which require continuous orchestration, memory management, information retrieval, and workflow execution. Built on an open RISC-V architecture, the platform combines high-performance compute, AI acceleration, and a modern cloud-native software ecosystem, supporting technologies such as Ubuntu, Kubernetes, Docker, LLVM, GCC, MLIR, IREE, Ceph, and SPDK. By enabling intelligent agents to collaborate, access tools, retrieve knowledge, and execute complex tasks efficiently, Contrail AIX provides a unified and scalable foundation for the emerging AI Execution Era, where the ability to execute intelligence becomes as critical as the ability to train it.

This paper presents a distributed Input-Output Physical Memory Protection (IOPMP) architecture featuring a decoupled I/O bridge and checker. The architecture enables distributed placement of I/O bridges to accommodate multi-master SoC configurations while sharing a single centralized checker, significantly reducing area overhead. The design is implemented in a 7nm process, with a single I/O bridge occupying less than 1200 µm². It incurs less than 0.2% performance overhead under 4KB large-packet transmission. The code has been merged into the OpenXiangShan Git repository and is available as open-source hardware.

As the NIST Lightweight Cryptography (LWC) standard, ASCON is pivotal for securing IoT ecosystems. This work presents CHIMERA, a multipurpose cryptographic engine for RISC-V, supporting AEAD and Hashing. We propose two architectural paradigms integrated via the Core-V eXtension Interface (CV-X-IF): a high-performance Complete Round (CR) version utilizing a state-register bank, and a minimalist Bitwise Rotation Unit (BRU) version focusing on Instruction Set Extensions (ISE). Our designs suit throughput-critical workloads, delivering up to 6x speed-up, as well as footprint-constrained deployments on ASIC and FPGA.

To achieve both high performance and productivity, modern software stacks rely on linear algebra libraries that encapsulate decades of optimization efforts. These libraries derive from empirical studies and analytical models developed primarily for high-end general-purpose systems, particularly the vector/SIMD extensions of x86-64 processors (e.g., SSE, AVX, and AVX-512). As a new and open-standard architecture, RISC-V software programming models target systems with unprecedent hardware diversity since pivotal extensions, such as the RISC-V V, may be realized on processors for domains ranging from edge to supercomputing. In this work, we advocate for flexible code generation tools to foster vendor-agnostic performance on high-performance software stacks, highlighting the most impactful software-level performance optimizations on early RISC-V vector systems and our insights on how to handle them on the context of linear algebra library development.

Rust is increasingly discussed in embedded and safety-aware systems, yet it remains uncommon in serious RISC-V projects. For teams working in C and assembly, the question is whether Rust meaningfully complements the RISC-V ecosystem at all.

This presentation offers an engineering-level exploration of that question. Rather than a migration guide or code-heavy tutorial, it examines where Rust aligns with low-level RISC-V work - and where real friction remains.

Topics include:
- How Rust’s abstractions translate in bare-metal contexts,
- Toolchain realities, including LLVM constraints and custom ISA extension workflows,
- Practical limits around vector extension,
- Incremental adoption strategies for mixed C/Rust systems,
- Build reproducibility and multi-target configuration,
- Off-hardware testing and separation of logic from hardware layers.

The goal is to give engineers enough practical insight to judge whether Rust has a place in their RISC-V workflow. This is an exploratory presentation, not a language tutorial - no prior Rust experience is required or assumed.

This work details a high-performance Vector Processing Unit (VPU) architecture designed to exploit data-Level Parallelism (DLP) within the strict power and area constraints of embedded environments. Addressing the parallelization needs of data-intensive tasks, the proposed modular architecture implements a subset of the RISC-V Vector (RVV) Zve32x sub-extension, focusing on essential 32-bit integer operations. The VPU is integrated as a co-processor to a CV32E20 core within the eXtendable Heterogeneous Energy-efficient Platform (X-HEEP) ecosystem. It leverages the Core-V eXtension Interface (CV-X-IF) 1.0 for low-latency instruction offloading and the Open Bus Interface (OBI) v1.0 protocol to ensure high-throughput data memory access during load/store operations. The implementation, featuring a Vector Register Length (VLEN) of 128 bits, was validated through Register Transfer Level (RTL) simulation and in hardware using a Xilinx Pynq-Z2 FPGA. Performance was evaluated using standard data-parallel kernels including AXPY, Indexed Arithmetic, and Matrix Multiplication (Matmul). Additionally, this research investigates the RISC-V GNU Compiler Toolchain, comparing standard C auto-vectorization against manual vectorization using RISC-V Vector C Intrinsics.

To enable debugging and calibration of real time systems, which are in interaction with the real plant, the software used on those systems often has a huge number of global variables. The huge number of global variables exceed the range addressable relative to the global pointer. Therefore, addressing these variables normally needs two instructions. Other CPU architectures commonly used in the real time control systems domain address these by various near addressing modes. This results in significant code size reductions and performance boost. This paper discusses different variants to add such near addressing features to the RISC-V ISA. The impact on the code size is evaluated with different representative workloads

This paper introduces HORCRUX, an open RISC-V instruction set extension for post-quantum cryptography (PQC). A modular PQ-ALU, integrated through the Core-V eXtension Interface (CV-X-IF) accelerates the core kernels shared by hash-, lattice-, and code-based schemes, including Keccak processing, sampling, modular/polynomial arithmetic, finite-field operations, and coefficient compression. The design targets NIST-standardized algorithms (ML-KEM, ML-DSA, SLH-DSA, HQC) and additional candidates under evaluation. We release the complete hardware/software stack as open source and report 65 nm ASIC post-synthesis results: with a compact footprint of ~26.3 kGE and energy savings up to 99.5%, the extension provides a practical route to energy-efficient PQC on RISC-V with minimal integration effort.

The RISC-V instruction set architecture (ISA) has seen rapid adoption over the past few years. Despite
this growth, the software ecosystem remains a major challenge to broader adoption. In contrast to x86 and ARM platforms, where precompiled binaries are widely available, RISC-V developers often face a significant software availability gap. Consequently, many packages, libraries, or applications must be built from source, requiring substantial expertise in build systems and target architectures. This process is largely manual and time-consuming, creating a significant barrier to widespread adoption of the RISC-V. To address this critical gap, this paper presents ATESOR, a multi-stage LLM-based framework for autonomous RISC-V software porting. The framework uses large language models to plan build requirements, compile packages, debug failures, and test generated binaries in RISC-V sandboxed environments. ATESOR supports both containerized RISC-V environment and native execution on RISC-V hardware such as the Banana Pi BPI-F3 and Milk-V Pioneer, provided by Cloud-V. ATESOR is trained on an internal dataset of more than 500 manually ported packages spanning build systems including CMake, Make, Ninja, and Go. For 100 CMake and Go-based packages, ATESOR demonstrated a 80% successful porting rate and experiment completed in approximately 1.5 hours, corresponding to an average porting time of about 54 seconds per package.

Classical quantum computing simulation is computationally demanding due to exponential state-vector growth.This work evaluates parallelization strategies on the RISC-V SpacemiT K1 using the RISC-V Vector Extension (RVV v1.0) and OpenMP. The dominant qubit-wise multiplication kernel was implemented in four variants: Sequential, OpenMP (MIMD), RVV vectorized (SIMD), and hybrid (OpenMP+RVV). Benchmarks up to 30 qubits 230 show size-dependent behavior: SIMD benefits small systems, multithreading improves medium scales, and large systems become memory-bound. The hybrid configuration achieves a peak speedup of 72.1× at 16 qubits and maintains 34.7× at 30 qubits, demonstrating the benefits of vector extensions and multi-core parallelism for quantum computing simulation workloads.

The open-standard RISC-V instruction set architecture (ISA) represents a paradigm shift in processor design and development, with its modular and customizable nature enabling a new era of processors uniquely tailored to their software workload. At RISC-V Summit 2025, AWS explored the potential of hardware / software co-design in the cloud for advanced testing and simulation, enabled by scalable, cloud-based solutions that combine high-performance FPGA instances with advanced emulation capabilities. This talk will give an update on how this democratized access is accelerating innovation cycles, reducing costs, and enabling organizations of all sizes to participate in RISC-V development, and addresses how RISC-V core developers can use AWS to monetize their designs in the cloud without the need to go to silicon.

This talk surveys the RISC‑V isolation toolbox—spanning PMP/ePMP, SPMP, privilege levels, virtualization, Risc-V Worlds, and emerging Supervisor Domains—and shows how these mechanisms can be combined to build scalable, composable security and safety systems beyond traditional privilege separation.

RISC‑V has steadily developed a rich and diverse set of isolation mechanisms, including ePMP for physical memory protection, privilege levels for execution control, page‑based virtual memory for scalable address isolation, hypervisor extensions for virtualization, and Worlds for hardware‑enforced compartmentalization. Each of these tools addresses different isolation challenges, from resource‑constrained microcontrollers to full server‑class systems.

Modern platforms increasingly demand fine‑grained, composable isolation rather than coarse, monolithic privilege separation. Mixed‑criticality systems, safety‑certified embedded platforms, and confidential computing environments all require isolation techniques that can be layered, combined, and adapted to different threat models and deployment constraints.

This talk presents a toolbox‑oriented view of RISC‑V isolation.

Supervisor Domains are introduced as an emerging architectural direction within this toolbox, exploring finer‑grained isolation within supervisor mode itself. While still evolving, Supervisor Domains illustrate the broader move beyond privilege levels toward more modular and composable execution domains and provide a useful lens for understanding how future RISC‑V systems may further decompose trusted software.

The Cyber Resilience Act is fully enforced in for all products "with a digital element" sold in the EU from December 2027. It has highly stringent requirements on manufacturers, such as products being “secure by design and by default” and “having no known vulnerabilities” at the point of going on sale. Discovered vulnerabilities in the product must be reported within 24 hours for critical exploits. All vulnerabilities must be patched within a short time frame, and support must be for 5 years or longer depending on the product.
As a specific example of the effect of the CRA on consumer products, the Linux kernel had 4336 reported exploits (CVEs) in 2024 (12 per day) and 5779 in 2025 (16 per day). Linux is used in an increasingly large range of consumer devices, not least a large proportion of the world’s smartphones. The able to continue to sell these products in Europe, then the industry really needs to move to a much more securely constructed systems. CHERI systems have memory safety bult-in which resolves 70% of vulnerabilities seen in weaker non-CHERI legacy systems.
Resolving such a large proportion of vulnerabilities at source will greatly reduce the support and maintenance costs, if nothing else. As a result of the CRA, there will be a large shift in the industry to make systems much more secure.
We expect that much of that shift will be towards CHERI systems as manufacturers wake up to the cost savings.

The RISC-V SPMP for Hypervisor specification enable MMU-less virtualization through a multi-layered memory protection architecture. While this model provides strong isolation for mixed-criticality MCUs, concerns have been raised regarding the hardware overhead and timing impact of multiple PMP layers. In this work, we present an empirical evaluation of an SPMP for Hypervisor proof-of-concept implementation. We analyze FPGA resource utilization and timing behavior as a function of entry count and discuss realistic entry requirements for MCU-based virtualization workloads, providing insights for hardware designers adopting SPMP-based architectures.

Memory Protection Tables (MPT) is an emerging RISC-V extension under community discussion that enables fine-grained multi-supervisor domain physical memory isolation and access control for multi-tenant computing, addressing the security and isolation limitations of the traditional PMP mechanisms. This work presents the first open-source hardware implementation of the MPT draft specification (v0.4). Our design features a multi-level cache for accelerated permission checking and an L1TLB extension to reduce query frequency, with a decoupled architecture for portability. Evaluation shows only 2.32\% average SPEC06 performance overhead and a 0.244\% core area overhead, providing a hardware reference for SMMPT standardization.

Many applications benefit from the ability to intercept, block, or modify system calls efficiently. Binary rewriting is one of the fastest techniques to achieve this, but it often relies on instruction-dependent heuristics that limit its applicability. To date, exhaustive rewriting techniques (introduced by zpoline) are only available for x86-64 ISA. This work introduces vpoline, the first fully heuristics-free system call interception library for RISC-V. By leveraging the RISC-V linker relaxation mechanism, vpoline achieves the same benefits as zpoline while overcoming the intrinsic limitation of requiring privileged access.

In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI. Krste will discuss new developments in the RISC-V ISA, including security extensions and matrix extensions for AI, as well as new profile and platform initiatives.

This presentation introduces Nuclei’s Subsystem Architector, a game-changing automation tool for RISC-V SoC design. As a leading Chinese RISC-V IP vendor, Nuclei delivers a full lineup of self-developed cores from M0-class ultra-low-power to A78-class high-performance processors, plus a complete SoC IP portfolio. Featuring an intuitive GUI, the tool enables end-to-end subsystem configuration, auto-verification, and one-click generation of production-ready deliverables. It cuts design/verification efforts by up to 95%, slashing iteration time from months to hours. Proven in IoT, industrial, automotive and multimedia projects, it empowers efficient, differentiated SoC development.

Yiftach will introduce NextSilicon’s Arbel program, which includes a few generations of RISC-V out-of-order super scalar core systems, including a silicon chip and mini computer, and the plans for the first RISC-V server-grade high-performance RISC-V CPU.

Autonomous systems' (robots, cars, satellites...) capabilities will be driven by Physical AI, Energy efficiency is not the only key constraint for future physical AI chips, as safety and robustness are extremely critical for autonomous operation To tackle the compound challenge, we need to aggressively optimize efficiency, leveraging specialization across all levels of the chip design hierarchy, pushing into domain-specific design automation tools and methodologies, while at the same time accounting for the increasing reliability concerns in advanced IC technology. In this talk, I will give concrete examples of how RISC-V enables deep domain specialization, for efficient and safe, reliable Physical AI, emphasizing the strategic importance of an open-platform approach.

The Sail RISC-V Model can generate an executable file from its formal specification,. Currrently RISC-V tests only provides limited test cases and cannot comprehensively test your RISC-V implementation. Some chips may use self-developed simulators for testing, but they cannot obtain formal verification-based guarantees like RISC-V Sail Model, nor can they offer full configurability. This work introduces a new test framework that uses the RISC-V Sail Model as the ref model, ensuring the model's completeness and accuracy. To improve simulation performance, we choose to use Pydrofoil, which is an improved version of the Sail Model that delivers ultra-high performance. To enhance test compatibility and usability, we provide a set of simple test interfaces (including register access, memory access, etc.) and support customizing model configurations. Currently, it has successfully integrated tests for some open-source RISC-V implementations.

We are going to talk about a fully open tapeout - from first schematics published for community review to sending the design to the Fab over the course of 6 months. Leveraging ET-platform and ecosystem around it, open source tools and now open CORE-ET silicon platform (part of OpenHW group), we present many-core RISC-V-based design with MRAM, creating a basis for the next generation open designs.
This talk presents an increasingly open development model, highlighting both the progress already made and the practical gaps that remain in today’s silicon ecosystem.

This live demonstration showcases our custom surface electromyography (sEMG) armband, enabling 16-channel monopolar acquisition. It features the RISC-V-based GAPWatch platform, which integrates two ADS1298 ADCs, an ESP32 radio module, GAP9 (a programmable multi-core RISC-V processor), and an STM32U5 microcontroller acting as a system gateway.
The armband is used to control a cursor in a 2D reach-and-hold task through EMG gestures. The system runs a context-informed incremental learning pipeline directly on GAP9. EMG signals are acquired, filtered, and fed to a tiny CNN, which predicts one of four gestures mapped to cursor directions (e.g., index finger contraction for LEFT, middle finger contraction for UP, etc.). Predictions are transmitted via BLE to a computer running the GUI with the task. The GUI updates the cursor position and derives a pseudolabel from the task context. If the predicted movement brings the cursor closer to the target, the pseudolabel acts as a reward signal; otherwise, it provides corrective feedback. This pseudolabel is returned to the device, where the CNN is updated via stochastic gradient descent (SGD). A replay mechanism is also implemented to stabilize training. EMG processing, inference, and SGD are all executed on GAP9.
During the demo, a participant will perform the task starting from an untrained model. As the task progresses, attendees can observe real-time on-device adaptation. The demonstration highlights how parallel RISC-V processing enables fully embedded, adaptive HMIs without reliance on the cloud or external PCs for recalibration.

RISC-V E-Trace is a powerful tool for observing the execution of a CPU. Optimizing code to use RISC-V Vector instructions brings novel challenges, and gaining real-time insight into the code as it executes helps quickly iterate to better solutions. The ability of E-Trace to capture runtime "vector length" (vl CSR) and instruction execution, together with its very compressed nature makes it an ideal choice as a tracing format. This keeps traces small, allows live-streaming E-Trace data for post-processing, and ultimately allows the software developer to easily understand the utilization of the vector unit. The end result is a very powerful workflow allowing fast iteration and development of low-level optimized software, with the execution of the code underpinned by QEMU and the RISC-V E-Trace format.

RISC-V-based microcontroller units (MCUs) are increasingly adopted in radiation-heavy environments such as space, where single-event upsets (SEUs) can cause bit-flips in sequential and combinational logic. RISC-V-based designs are ideally suited for these domains, as open architectures allow for fault-tolerance modifications, enhancing readiness for architectures and systems-on-chip (SoCs). While component-level architectural protection methods, such as error correction codes (ECC) and triple modular redundancy (TMR), can individually harden each component, they leave critical gaps: the voters, encoders, and decoders that implement these protections themselves remain unprotected and become single points of failure.
We propose an overlapping protection approach that addresses this fundamental “who checks the checker?” problem. By extending each protection domain to encompass the checking logic of adjacent domains, we achieve end-to-end fault tolerance across an entire RISC-V MCU without requiring radiation-hardened standard cells. We build on croc, an open-source, extensible RISC-V MCU platform based on the CVE2 core, incrementally applying ECC-protected SRAM, triple-core lockstep cores, a reliable OBI interconnect, and TMR peripherals.
Fault injection campaigns in both RTL and synthesized netlist show that the fully protected RISC-V MCU achieves over 99.9% fault coverage at 2.71× area overhead, 22% less than fine-grained triplication. Critically, without overlapping protection, 16.33% of faults in voter signals cause failures; with overlapping, this drops to 0.26%. All designs are implemented using the fully open-source IHP 130nm technology, Yosys, and OpenROAD.

In this talk, I will present a novel approach for accelerating real-time motor control applications using a MIPS defined trigonometric math custom instruction extension on RISC V. One of the most widely used algorithms in motor control is Field Oriented Control (FOC). Within the FOC loop, the Park and Inverse Park transformations require repeated sine and cosine computations, which can be a significant performance bottleneck in software-based implementations.

I will walk through a simple software implementation of the FOC loop and demonstrate the minimal code changes required to take advantage of custom trigonometric instructions. By offloading these operations to dedicated execution units integrated directly into the CPU pipeline, the solution delivers substantial performance improvements at the algorithm and system level while maintaining a software-friendly programming model.

The talk will also discuss why tightly integrated custom execution units can provide better performance, power efficiency, and area utilization compared to traditional accelerators or heterogeneous compute approaches. Using RISC V custom instructions, software developers can access application-specific hardware acceleration with minimal complexity and without rewriting core algorithms.

I will conclude by showing how accelerating motor control algorithms enables more precise, faster, lighter, and more efficient motors—benefiting applications in robotics, industrial automation, electric vehicles, and emerging real-time AI systems.

Mixed-criticality systems incorporating software components with different criticality levels demand strong isolation mechanisms to guarantee dependability. High-end and mid-end architectures accomplish this through rigorous temporal and spatial partitioning, backed by multiple privilege levels and memory management units. Nevertheless, low-end processors, constrained to two privilege levels, encounter difficulties in realizing effective temporal and spatial partitioning without undermining system composability. This paper presents a novel multi-context framework for low-end RISC-V processors, exploiting a lightweight hardware extension and enabling efficient temporal and spatial partitioning. The proposed approach not only guarantees robust isolation and system composability but also offers flexibility to trade off hardware and software overhead, pushing forward the state of the art in dependability for resource-constrained embedded systems.

Tracing allows capturing timing sensitive behavior that would be obscured by other means of extraction that rely on code running on the HART itself, such as debugging hardware or instrumentation. The ratified specification “Efficient Trace for RISC-V” (E-Trace) defines a highly compressed yet relatively simple RISC-V-specific instruction and data tracing format. In combination with the program binary, E-Traces allow the complete reconstruction of a program’s execution path. We present an open source Rust library and CLI tool that allows both inspection of traces via an intuitive text interface and converting traces to other formats for analysis by downstream tools. While proprietary solutions for consuming E-Traces exist, this is, to our knowledge, the first open source tool suitable for use in production. Our tooling makes E-Trace-based augmentation of CI flows feasible. Based on traces collected during program execution, the CLI tool enables additional checks and metrics (e.g., coverage). Engineers may also use the tool to gain a better understanding of a failure. Use-case-specific checks may be implemented using the library. We also developed a QEMU plugin that enables experimenting with and evaluating such CI and development flows before any hardware investment, significantly lowering the entry barrier. The plugin serves as a configurable trace encoder, controlled solely by plugin arguments, that produces a trace file on the host.

In recent years, the executable specification generated from Sail-RISC-V has increasingly been considered as a successor to the widely used Spike ISA Simulator as golden reference for RISC-V, including the complex and highly configurable RISC-V Vector Extension (RVV). In this paper, we compare the RVV behavior of Sail-RISC-V against Spike using the automated testing framework RVVTS. While Sail-RISC-V largely matches Spike under positive testing (0.23% deviations), negative testing reveals substantially more deviations (3.73%), highlighting remaining issues in Sail-RISC-V’s RVV instruction validity checking under dynamic configurations.

Integrating AI-based capabilities into satellites improves spacecraft autonomy, but poses considerable obstacles in designing the hardware and software ecosystem.
The orbit-dependent generation of power with solar cells, the limited thermal dissipation and weight present significant challenges in designing a compute platform capable of edge inference, forcing the trade-off between high-performance for complex AI models and strict power/area budget.
Moreover, AI models must share the same resources of traditional algorithm that are executed onboard concurrently with the inference, such as avionics, attitude orbit control, data handling and signal processing.
However, benefits of onboard processing comprise secure and private computation, decreased data uplink/downlink demands, autonomous detection and resolution of anomalies, enabling autonomous spacecraft operation.
Therefore, it is necessary to adapt a hardware-aware codesign approach in designing software components to implement energy-efficient and secure edge inference without decreasing the performance of traditional applications.
The ISOLDE space demonstrator comprises several RISC-V cores and accelerators, and its hardware architecture and software ecosystem are presented, with a particular focus on the interactions of several open-source and open-hardware IPs developed by various academic and industry European partners.

As cybersecurity threats continue to evolve, hardware security has become a critical issue in the design of electronic devices. The advent of quantum computing has forced standardization bodies to rethink cryptographic foundations, leading to the rise of Post-Quantum Cryptography (PQC) as a strategic priority. At the same time, the RISC-V open-source instruction set architecture is emerging as a key enabler of secure hardware, offering new opportunities to design intrinsically secure microarchitectures.
To address these research opportunities, CEA has developed VASCO, an ASIC platform designed to innovate, implement and characterize secure hardware primitives. It supports the development of robust countermeasures against side-channel attacks, fault injection and other physical security threats. In addition, VASCO Is adopted for characterization of security primitives such as True Random Numbers Generators (TRNGs) and Physically Unclonable Functions (PUFs). VASCO focuses also on PQC, which requires specialized hardware accelerators to achieve efficient and secure implementations. This demo will present the latest advancements made with VASCO#3, which was fabricated in 2025.

Embedded tracing is essential for validating reliability, optimizing performance, and debugging complex embedded software. Despite rapid innovation in the RISC-V ecosystem, open and interoperable trace solutions have remained limited. C-Trace, developed in the context of the European TRISTAN project, addresses this gap with an open-source trace encoder and an extensible ecosystem approach. C-Trace introduces a modular trace-encoder architecture designed for efficient, continuous “live” observation. Beyond standard program-flow tracing, it supports hardware-assisted instrumentation that can automatically emit trace messages on access to selected control/status registers (CSRs) or on configurable watchpoints. This enables trace streams that carry richer runtime context (e.g., program counter, timestamps, direct data, and selected performance counters) and can support application use cases such as worst-case execution time (WCET) estimation, timing optimization, test-case prioritization, and integration-level coverage measurement. In addition to off-chip export, C-Trace can forward trace-triggered events internally to an on-chip CPU, enabling watchdog, runtime verification, or control-flow integrity (CFI) checking functionality. Finally, C-Trace is provided under a dual-licensing model (CERN-OHL-S and a non-copyleft commercial option) to balance open collaboration with industrial IP needs.

CVA6 is an open-source RISC-V core with highly configurable parameters for tailoring the core to various
applications. An optimization-oriented analysis of the current implementation showed that the scoreboard (SB) and controller are the biggest combinational modules involved in the critical path. The SB is in charge of many crucial functions, including issuing, forwarding, writeback, and committing, while the controller manages all the stages of the core. This work presents two optimization proposals: re-order buffer (ROB) and Issue logic separation from the Scoreboard and registering Controller output. Preliminary results show promising outcomes in implementing the core, relaxing the timing, which in turn enables operating at a higher frequency. With this optimization, we get to improve the maximum frequency of operation by 14% for the existing FPGA configuration from OpenHW for Xilinx FPGA.

This extended abstract reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V cloud server and accelerator prototypes capable of running fully-featured Linux-based software stacks. Building on processor IP from the EPI and EUPILOT projects, RISER targets Europe's open strategic autonomy in cloud infrastructure. We present the RISER Microserver Platform, an FPGA-assisted prototype that integrates the EPAC1.5 RISC-V vector-processor test-chip in a standalone computing node with its own boot firmware, NVMe storage, and 100 Gbps Ethernet connectivity, and discuss the integration challenges encountered during bring-up

The verification of integrated systems traditionally relies on detailed Register Transfer Level (RTL) simulations to ensure functional correctness before hardware implementation. While RTL simulation provides cycle-accurate behavior and can even achieve event-level precision when combinational delays are modeled, it suffers from extremely long execution times. Simulating complex software workloads such as booting an operating system may require several days of simulation time.
Instruction Set Simulators (ISS) provide a faster alternative for software execution. In the RISC-V ecosystem, Spike is the reference ISS and can achieve simulation speeds several orders of magnitude faster than equivalent RTL processor models. However, replacing the processor RTL model with an ISS introduces temporal discrepancies that may affect the accuracy of system-level simulations. This work presents Spike-RTL, a HW/SW co-simulation framework that integrates the Spike ISS with RTL models of the remaining hardware components. The tool supports both Verilog simulation and C/SystemC HW models (e.g. generated using Verilator). Experimental results show simulation speedups of up to 40× compared to Verilog simulation and 4× compared to Verilator, while maintaining timing errors on the order of 10%. The framework also introduces configurable timing models for instruction execution, cache miss latency integration, and variable-granularity synchronization mechanisms between ISS and RTL components.

Verification has become one of the most time-consuming stages in modern high-performance processor development. Co-simulation compares the Design Under Test (DUT) against a reference model (REF) at instruction granularity, providing strong debuggability, but existing software-based solutions are limited to KHz-level speeds and cannot meet industrial-scale verification demands. FPGA platforms can accelerate processor simulation to tens of MHz; however, massive and frequent hardware-software communication between the FPGA-hosted DUT and software REF still constrains co-simulation throughput.

We present DiffTest-H, an FPGA-accelerated co-simulation framework for industrial-scale RISC-V processor verification. By exploiting the structural, ordering, and behavioral characteristics of verification data, DiffTest-H optimizes communication through compression and packaging while preserving instruction-level comparison and debugging capability. It reduces communication overhead by up to 99.7% with 3.2% additional area overhead on Xilinx VU19P, achieving co-simulation speeds beyond 10 MHz and enabling faster verification iteration.

DiffTest-H has been deployed to verify XiangShan, a high-performance out-of-order RISC-V processor, covering interrupts, memory hierarchy behaviors, vector extensions, and virtualization. Across FPGA and emulator platforms, it has helped uncover more than 151 complex bugs in XiangShan, demonstrating its effectiveness for large-scale industrial processor verification.

Embedded applications increasingly rely on highly efficient, low-area RISC-V processors. However, short 3-stage pipelines often suffer from data and control hazards that degrade performance by introducing frequent stalls. This paper presents the implementation of Fine-Grained Multithreading (FGMT) on STRIVE-L an industrial 32-bit RISC-V core supporting the RV32ECM instruction set. By interleaving two hardware threads, the design effectively hides pipeline stalls and simplifies branch target calculation without requiring complex branch prediction. To further mitigate structural hazards and the underutilization caused by inactive thread contexts in fixed round-robin scheduling, we introduce a novel "Thread Forwarding" (TF) technique which enables a form of TLP (Thread-Level Parallelism). Implemented in 40nm (C40) technology with a target frequency of 300MHz, the standard FGMT achieves a 14\% IPC improvement over the baseline at the cost of a 9\% area overhead within an MCU SoC featuring 16 KBytes of instruction and data memory. The TF architecture achieves a Pareto optimal configuration, further boosting IPC to 0.958 (+18.8\% over baseline) while maintaining the same area footprint as the standard FGMT implementation.

The Monte Cimone project provides a RISC-V testbed for High-Performacne Computing cluster. This paper presents Monte Cimone v3 (MCv3), the third iteration of the Monte Cimone RISC-V HPC cluster, integrating the SOPHGO Sophon SG2044 processor, an evolution of the SG2042 used in MCv2. We characterize MCv3 using HPL and STREAM benchmarks coupled with power measurements, and compare it against two reference platforms: the Intel Xeon Platinum 8480+ (Sapphire Rapids) and the NVIDIA Grace CPU Superchip. Our results show that the SG2044 more than doubles single-core performance and improves scalability compared to SG2042. MCv3 achieves an energy efficiency of 3.08GFLOPs/W which improves of 10x w.r.t. MCv1 and is in the range of x86-64 and Arm servers. On pure performance when normalized on the SIMD/Vector length MCv3 on its peak efficiency point (16 cores) achieves 46% performance of Intel Sapphire Rapids server and 91% performance of NVIDIA Grace CPU superchip.

Custom RISC‑V implementations increasingly require tight coupling between hardware and software development to ensure correctness, performance, and rapid iteration. This paper presents the RISC‑V Unified DB Instruction Set Simulator (RVUDB‑ISS), an open-source simulation‑driven framework that enables early‑stage HW/SW co‑development, configuration validation, and full‑stack debug prior to RTL availability. The ISS is automatically generated from a formally specified configuration, producing an implementation‑accurate model for custom RISC‑V cores and extensions.

RVUDB‑ISS supports configuration‑optimized binaries, enforcement of architectural corner cases, and precise modeling of implementation‑defined behaviors.
A key functionality is the ISS’s integrated debug experience: developers can run custom workloads, halt execution at the first instruction, and attach standard tools such as GDB and VS Code to provide a familiar SW debug environment. This enables full symbolic debug of custom cores without hardware availability, significantly reducing time‑to‑bring up, and improving quality at bring up.

Overall, RVUDB‑ISS demonstrates that simulation‑based debug for custom RISC‑V configurations enables earlier validation, higher code quality, and more reliable HW/SW co‑development compared to traditional pre and post‑silicon workflows.

RISC-V–based processors and ML accelerators are increasingly targeted for latency-sensitive domains such as automotive Software-Defined Vehicle platforms and edge systems, where runtime observability is essential for performance validation and early fault diagnosis. Although RISC-V standardizes architectural and hardware performance monitoring counters, raw cumulative snapshots do not directly provide window-level deltas or streaming metrics required for real-time analytics. To bridge this gap, we present a monitoring tool that implements a window-level telemetry pipeline to enable real-time observability. It converts cumulative counters into per-window delta values, selects a curated metric set, and computes derived metrics. The resulting telemetry is recorded simultaneously as CSV and structured logs (NDJSON) and streamed to external consumers via ZeroMQ for runtime processing. The approach is validated using a cycle-level gem5 RISC-V simulation, demonstrating 2–3 ms host-side processing per 10 ms window with minimal overhead. The modular design incorporates a source-agnostic acquisition layer, allowing the input backend to be replaced by hardware performance counters with minimal changes to the core processing and output interfaces.

Floating-point unit (FPU) verification is inherently challenging due to IEEE-754 corner cases, multiple rounding modes, exception handling, subnormal behavior, and the large input space introduced by mixed precision. The CORE-V Floating-Point Unit (CVFPU) released as open source, provides a highly configurable multi-format implementation but lacks an industrial-grade functional verification framework. This work addresses that gap by proposing a structured UVM-based verification strategy tailored to its configurable architecture. The approach integrates a variable-precision C++ reference model, directed and constrained-random stimulus, assertion-based checks, and coverage-driven closure.

Identifying the optimal hardware configuration for running complex workloads on edge devices is critical for reducing cost and maximizing performance. Tailoring hardware designs to specific applications significantly increases resource efficiency, which is essential to meet the strict performance constraints. Unfortunately, exploring the design space at the hardware-level is difficult due to the complexity of the hardware design processes.
We present an interactive analysis framework for identifying profitable hardware optimizations from system-level execution traces. The tool automatically identifies custom ISA extensions and estimates their performance impact as well as the expected area cost. To adjust the optimization goal for arbitrary systems and design capabilities, the user can choose from a range of preset scoring functions or specify a custom one. Applied to a wide range of representative embedded and edge artificial intelligence workloads, we are able to identify individual custom instructions that yield expected performance improvements of up to 32 % for Embench and 60 % for MLPerf Tiny benchmarks. The framework is provided as open source.

Processor implementations designed to occupy minimal areas, such as SERV or FazyRV, are becoming increasingly popular. Some of these designs focus on flexibility and configurability while maintaining their compact design. However, due to their minimal area, implementations often involve compromises in specific components to achieve this level of efficiency. The FazyRV decoder, e.g., is highly optimized for area and therefore omits certain checks for illegal instructions.
To address these drawbacks, we propose a concept that uses partial runtime reconfiguration to dynamically replace the decoder's logic with a more robust variant to enable stricter instruction checking. These modifications introduce an area overhead of up to 39% more flip-flops than the original implementation. Dynamic partial reconfiguration can be triggered during runtime via a memory-mapped register, enabling the processor to continue normal operation seamlessly.

Vitamin‑V (2023–2025) is a Horizon Europe project building a production‑grade, open‑source RISC‑V ecosystem for cloud environments. It extends RISC-V ISA support in three execution platforms (QEMU, gem5, FPGA), enables virtualization and contributes to the development of full cloud‑native stacks—OpenStack, Kubernetes, Kata Containers, RustVMM. The project also boosts commercial developments from Semidynamics, ZeroPoint, and Virtual Open Systems. This paper summarizes the technical outcomes and lessons learned.

Functional safety (FuSa) in modern SoC designs demands rigorous fault detection mechanisms alongside standardized error reporting. We present a fully automated, generator-driven design flow that automatically applies dual modular redundancy (DMR) through a pass implemented in CIRCT, an MLIR-based hardware compiler framework, without requiring manual RTL modification. To validate the correctness of the generated design, we apply formal verification, providing strong assurance that the DMR composition itself introduces no spurious faults. In addition, we address the system-level integration of the generated fault detection signals by routing them to a safety controller that adheres to the "RISC-V RERI Architecture Specification" for error reporting across the SoC, capturing each error's severity, nature, and location. We validate our generation flow through fault injection, demonstrating reliable fault detection across arbitrary hardware modules and correct propagation, recording, and reporting of detected errors in the safety controller. Combined, our contributions form an automated path from module-level fault hardening to system-level error observability, advancing the practical adoption of FuSa practices in generator-based RISC-V SoCs.

The evolution of modern computing towards emerging paradigms, such as In-Memory Computing (IMC), is severely limited by the high intrinsic noise of these memory technologies.
Simultaneously, conventional Von Neumann architectures exhibit data-dependent execution and power profiles, leaving embedded systems highly vulnerable to physical Side-Channel Attacks.
In this extended abstract, we propose a novel paradigm based on Hyperdimensional Computing for encoding and decoding RISC-V instructions. By mapping standard assembly instructions into a neural-inspired holographic representation and storing them in superposition, leveraging the capacity of high-dimensional spaces, the traditional decoding logic is replaced by a highly parallel Associative Memory. Our Design Space Exploration compares 1-bit Binary and 8-bit Integer representations, evaluating the trade-off between instruction capacity (chunk size) and dimensionality. Furthermore, we demonstrate the intrinsic fault tolerance and security-by-design of the architecture: a binary HDC system maintains 100% decoding accuracy even when subjected to a 5% physical memory corruption, while its constant-time execution and massive pseudo-random switching activity inherently mask side-channel leakages. This paradigm paves the way for ultra-robust, secure, and ECC-free RISC-V pipelines tailored for next-generation processing cores.

Smart glasses must run multiple demanding applications—speech enhancement, eye tracking, and automatic speech recognition—simultaneously within tens of milliwatts of power budget. This poses a significant challenge for platforms constrained by milliampere-hour batteries and gram-scale form factors.
Open hardware ecosystems, and RISC-V in particular, have proven invaluable. Rather than a contribution target, RISC-V provides a foundation to build on. Recent industrial and academic efforts have produced rigorously validated, ultra-low-power microarchitectures and extensive open knowledge that significantly lowers the barrier to custom silicon for teams whose expertise lies outside traditional semiconductor IP development.
The second key challenge is on-device ML inference in a field where model architectures evolve faster than fixed-function accelerators. Hyper-specialized NPUs risk obsolescence before shipping. The solution is heterogeneous SoCs: systems where dedicated NPUs handle heavy-lifting for characterized inference workloads, tightly coupled with programmable RISC-V cores for pre/post processing and new operations.
Crucially, RISC-V cores are extensible. Their ISA can be extended with custom instructions to efficiently cover emerging operators without full hardware redesigns—avoiding the obsolescence problem entirely.
This talk offers a high-level perspective on how a product-driven company approaches custom silicon for smart eyewear, and why RISC-V sits at the center of that strategy.

Smart eyewear promises unobtrusive, context-aware human–computer interaction by leveraging strategically placed multimodal sensors and on-device intelligence. However, integrating high-bandwidth sensing and machine learning inference within a compact and lightweight form factor remains challenging due to strict constraints in power consumption, memory footprint, and computational efficiency.This work presents RVEdge-Vision, an open hardware and software platform built on the RISC-V ecosystem that enables rapid prototyping and evaluation of next-generation smart glasses. The platform adopts a modular architecture supporting both frame-based and event-based vision sensors. To the best of our knowledge, this is the first open smart-glasses platform integrating event-based vision sensing in a glasses form factor, enabling ultra-efficient visual perception for wearable edge AI systems.
The system incorporates a hardware–software co-designed power management framework optimized for battery-operated edge devices and continuous sensing workloads. As a reference implementation, we present a compact smart-glasses prototype that integrates multimodal sensing and on-device ML acceleration. The device can operate for several hours on a 300 mAh battery while sustaining real-time embedded vision workloads. A YOLOv8-based hand gesture recognition runs on-board with a few ms latency without relying on cloud connectivity. By releasing the platform as open hardware, OpenEdge RV aims to accelerate innovation within the RISC-V and open-edge AI communities, providing a reproducible foundation for research in wearable sensing, neuromorphic vision, and ultra-efficient on-device intelligence.

RIVIERA core, developed within Chips-JU TRISTAN Project, is a valid alternative to State-of-Art DSP architectures used in NFC Readers downlink signal processing. Instead of relying on custom hardware, RIVIERA employs an open source RISC-V core and its ISA extension interface to implement a software defined-radio (SDR) architecture, thus moving processing to the extreme edge of an NFC communication system. The first RIVIERA prototype targets decoding of NFC Type A tags responses and is ready by-design to cover other NFC standards and rates. By replacing hardened logic functions with SW data processing supported by a general-purpose DSP accelerator, RIVIERA reduces pre-silicon engineering effort, enables continuous post silicon improvements, and facilitates portability across SoCs designs and technology nodes. This work demonstrates how application-specific custom RISC V ISA extensions can effectively and efficiently handle RF baseband workloads, paving the way for the adoption of SDR architectures in RF communications for the IoT mass market.

The MPACT Tools portfolio provides open-source tools that increase the velocity of HW-SW co-design and development of RISC-V based systems.

MPACT-Sim [1] is an ISS framework in C++ that makes it easier to create ISSs from scratch, and supports rapid changes in response to ISA design changes or user-needed functional enhancements. Using DSLs to describe the instruction set and encoding, it automatically generates instruction decoder source, and provides support for generating assemblers and disassemblers. MPACT-Sim enables rapid HW/SW co-design and early pre-Silicon software development.

MPACT-RiscV [2] (built using MPACT-Sim) is a highly configurable RiscV ISS, with an interactive command interface for assembly level debugging and a customizable assembler which generates both relocatable and executable output files.

To demonstrate the practical impact of the MPACT ecosystem, we present the real-world case study of the CoralNPU machine learning core [3], which is focused on development and execution of ML kernels. The CoralNPU-MPACT ISS [4] development was significantly accelerated by leveraging the fundamental MPACT-Sim and MPACT-RiscV infrastructure, requiring only limited modifications to support the additions to the CoralNPU's instruction set and memory access rules.

The CoralNPU UVM testbench [5] captures every retired instruction via the standardized RISC-V Verification Interface (RVVI) and steps the MPACT ISS model using a SystemVerilog DPI bridge. The testbench then retrieves golden reference values from the model to verify equivalence against the CoralNPU RTL, detecting functional bugs during development.

The growing complexity of RISC-V processors, driven by rapidly expanding ISA extensions and sophisticated microarchitectures, has made functional verification a dominant bottleneck. Contemporary CPU verification commonly relies on RTL co-simulation against a software reference model, but on hardware-assisted simulation platforms (e.g., FPGAs) this workflow is fundamentally limited by high-volume communication between the accelerated RTL and the host-executed reference, preventing verification throughput from scaling. This paper addresses this by eliminating the RTL-host interaction bottleneck and proposing a Synthesizable Verification Methodology (SVM). We re-architect a RISC-V reference model as synthesizable hardware and deploy it alongside the design under test on the same acceleration platform, enabling fully hardware-based co-simulation at near-native speeds (60 MHz on FPGAs) while preserving reference-model checking and debug observability.

Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified Database (UDB) as the source of truth for extension definition and a Large Language Model (LLM) connected through Model Context Protocol (MCP) tools to accelerate migration into compliant custom opcode space. In Phase 1, the agent inspects instruction encodings, identifies conflicts against ratified and reserved space, and proposes remappings for human approval. In Phase 2, it generates hardware and software artifacts from the approved mapping and validates them through automated build-and-test loops. To evaluate the flow, we are open-sourcing two packed-SIMD extensions and the supporting hardware and software, including a full-system simulator, GNU assembler support, Zephyr runtime support and even the RTL design for the more than 140 migrated instructions. The result is a working open-source end-to-end stack, from decoder to application code, demonstrating AI assistance as a practical aid for ISA architects and as an automation layer for the associated hardware and software engineering.

Reactive real-time systems rely on preemption and, by extension, context switching (CS) to schedule critical tasks. Short, frequent interrupt routines may use a disproportinally large ammount of time and energy for CS rather than core application functionality. Replicated register files (RRFs) are an established solution for fast CS, but area-intensive and poorly scalable. This abstract presents the heterogeneous interrupt architecture, a solution for targeted use of RRFs that maintains area-efficiency, and the parallel context stack (PCS), a novel RRF microarchitecture. The proposed concepts are evaluated with implementations in TSMC 22-nm and a periodic task case study. The implementation in a RISC-V microcontroller system demonstrates a 1.2% area overhead with no timing detriment for the PCS, while the case study demonstrates a reduction in clock cycles and retired instructions of up to 26% and 21%, respectively.

Microarchitectural performance evaluation is an essential step in modern processor design and architecture exploration. However, developing a cycle-accurate simulator from scratch requires implementing both instruction semantics and detailed microarchitectural models, which significantly increases development complexity.

This work presents RISCV-Perf, a lightweight performance modeling framework designed to integrate with the Spike RISC-V functional simulator. The framework decouples functional execution from cycle-level timing simulation through a minimal instruction interface that captures key instruction attributes such as program counters, operand registers, and memory access information. By reusing the functional correctness provided by Spike, RISCV-Perf focuses solely on modeling microarchitectural timing behavior.

RISCV-Perf adopts an execution-driven simulation approach, enabling cycle-level modeling of superscalar out-of-order processors without generating execution traces. The timing model represents major microarchitectural components including an instruction flow model, register renaming mechanism, memory operation pipelines, and cache hierarchy interactions. In addition, the framework is implemented using a modular policy-based design, allowing architectural components such as branch predictors and cache policies to be easily replaced or extended.

Experimental evaluation using the MiBench benchmark suite on an RV64GC configuration demonstrates that RISCV-Perf can effectively generate performance insights such as CPI behavior and branch prediction miss rates across workloads. These results show that the framework provides a practical platform for workload characterization and microarchitectural policy exploration.

Open-source hardware is booming. To prevent fragmentation, encourage collaboration and reuse we propose the RISC-V to join forces with Reproducible Builds communities and concentrate innovation potential where its needed most: creation of new micro-architectures, IPs and their integration into new SoCs and applications. To facilitate this goal, we chose Guix, a rigorous solution for reproducible software artefacts. We apply it to dependency management & reproducibility problems in open-source hardware and show the validity of the approach, taking CVA6 as a running example. The end result - a fully reproducible collection of packaged tests, emulation, simulation and cycle-accurate models - shows a promising workflow that could (in future) scale to support larger RISC-V community with reusable software & hardware components for next-generation platforms.

Historically, several architectures have explored running ILP32 software on 64-bit ISAs - including ×86-X32, MIPS-N32, and Arm64-ILP32 - yet only Arm64-ILP32 reached commercial adoption, exclusively within Watch OS as a closed-source implementation.
We now present a new landmark: the first open-source commercial deployment of
RV64ILP32, realized on the Allwinner V881 Al Glasses SoC (Dual-Core XuanTie
(907).
1. Product-Level Demo (V881-based): An Al Glasses device running with
RV64ILP32 Linux kernel. Benchmarks against traditional RV32 Linux kernel demonstrate substantial gains - iperf loopback test throughput improves by 1.5×, while eBPF performance achieves up to 5.7× speedups across test cases
2. Community-Level Demo (QEMU-based): For the first time, LP64 applications execute on an RV64ILP32 Linux kernel, which provides ‡2 GB of separate address spaces, revealing new possibilities for mixed-ABI workloads on RISC-V (20% memory footprint saved v.s. traditional RV64 Linux kernel).

Together, these demonstrations mark a significant milestone: delivering 64-bit RISC-V performance advantages to resource-constrained embedded AI devices, while preserving ILP32 memory/cache efficiency - entirely on an open-source software stack.

Modern interrupt controllers combine hardware and software mechanisms to reduce interrupt latency, optimizing either worst-case latency, average-case latency, or both. The paper provides analysis of interrupt-latency optimization techniques and their trade-offs in the context of RISC‑V interrupt architectures. It draws on an end-to-end workflow that began with functional modeling and continued through simulation, OS porting, and RTL implementation. This provides practical insight into how these techniques behave both in isolation and in real-world systems. The paper shows that each technique admits multiple realizations, which redistribute cost across latency metrics, software and hardware implementation complexity, memory footprint, and other factors, and that the techniques are interdependent, so the benefits of enabling them are not directly additive.

As the RISC-V software ecosystem achieves maturity for high-performance computing, the demand for production-ready, competitive processor cores has reached a critical point. This presentation introduces the X200, our flagship RISC-V core, which has completed its entire development cycle and is now ready for deployment. We provide a comprehensive overview of the X200's journey, from its ambitious design goals to final GDS layout. The session details its advanced multi-stage pipeline, sophisticated memory subsystem, and scalable multi-core interconnect fabric. We present a transparent competitive analysis, share key benchmark results, and reveal detailed Power, Performance, and Area (PPA) data verified from the final layout. Attendees will gain a clear understanding of the X200's capabilities and its readiness to power next-generation SoCs.

In this paper we present STRiVe-VP, a hybrid RISC-V simulation framework that unifies functional and timing simulation by leveraging LLVM’s compiler infrastructure. Built on RISC-V VP++, it translates executed instructions into LLVM MCInst and LLVM MCA Instruction objects, which are injected into an extended LLVM MCA pipeline. Custom hardware units (cache, prefetch buffer, branch predictor) are modeled, allowing the combination of static scheduling information with dynamic effects from control flow and memory behavior. This direct integration enables timing-aware decisions using live architectural state and provides unified functional and timing debugging. Validation against an FPGA prototype of an in-order, single-issue rv32emc_zfinx core shows that STRiVe-VP matches FPGA cycle counts exactly for several benchmarks and across multiple optimization levels, demonstrating cycle-accurate performance estimation and a solid basis for extending to more complex RISC-V microarchitectures.

The RISC-V ecosystem is expanding rapidly, with many open hardware projects now developed collaboratively on platforms such as GitHub. Yet while software enjoys mature continuous integration and deployment (CI/CD) practices, hardware design lacks equivalent automated verification: formal tools such as logic equivalence checking (LEC) stay confined to proprietary EDA solutions whose per-run license costs make them impractical to run on every pull request. This gap is now acute, as AI-assisted agents that modify RTL are emerging without fast, open tools to verify their output, sharpening the need for automated formal verification inside the development loop.
We present kepler-formal, an open-source formal equivalence checking tool that runs efficiently in CI for RISC-V projects. Built on a high-performance C++ netlist engine with a Python interface, it checks equivalence between RTL transformations and synthesized netlists. It is evolving from combinational LEC toward Sequential Equivalence Checking (SEC): since RTL contains registers, pipelines, and state machines, SEC's cycle-by-cycle modeling is the sound method for proving equivalence at the RTL level.
On open RISC-V designs (CVA6, BlackParrot, MegaBoom, up to ~3.9M primitives), checks complete within typical pull request budgets, from under two to under ten minutes. Running license-free and fast enough for per-commit use, kepler-formal delivers both the inner-loop verification AI agents need and a practical first formal gate before commercial sign-off.

PRG32 is an open-source educational platform that teaches RISC-V programming by developing playable 32-bit game cartridges. Inspired by retro-gaming consoles, PRG32 allows students to write small games in RISC-V assembly or C, package them as .prg32 cartridges, and run them on a lightweight runtime targeting RISC-V hardware and emulated environments.

The demo presents the complete PRG32 workflow: writing a simple game, building the cartridge, loading it into the runtime, and executing it as an interactive program with graphics, input, and game logic. By turning low-level programming concepts into tangible, playable outcomes, PRG32 helps students understand registers, memory, control flow, graphics buffers, input handling, compilation, and system interfaces in a practical, engaging way.

The platform is designed for computer architecture, systems programming, and introductory embedded computing courses. It supports both assembly-first and C-based teaching paths, enabling instructors to connect abstract RISC-V concepts with hands-on experimentation. The demo will show how PRG32 can be used in the classroom to make RISC-V programming more accessible, motivating, and fun.

The PULP Platform team at ETH Zürich and the University of Bologna has delivered several “big” chips based on RISC-V cores that exceed the complexity of chips traditionally designed in academic/research settings. These designs are made possible through open-source principles that allow greater collaboration and innovation in critical parts of the design. RISC-V has been instrumental in the development of these designs, allowing the team to develop a sandbox of building blocks for creating designs that exceed one billion transistors.

Hardware Description Languages (HDLs) have evolved from traditional Register Transfer Level (RTL) modeling over High-level Synthesis (HLS) towards todays generative approaches. Although modern HDLs often assert technical advantages, directly comparable evaluations across HDL paradigms remain scarce.
This work introduces a year-long, community-driven tournament, designed to enable reproducible comparison of HDLs under uniform conditions. A RISC-V microarchitecture is independently implemented in multiple HDLs and evaluated within a standardized, GitHub-based framework. Since the framework provides identical conditions, differences can be related to how an HDL enables hardware realization. To ensure the quality of this tournament, all results are public, reproducible, and objectively evaluated, providing transparent evidence of HDL-specific strengths and trade-offs. Through contribution, participants can systematically demonstrate the capabilities of their preferred HDL. The collected implementations can further be used as common reference basis for research, education, and reproducible comparison of HDL approaches.

The surging demand for VM-based secure containers in the AI Agent era is driving rapid growth in the scale of vCPU deployments. However, the current RISC-V AIA specification co-locates inter-processor interrupts (IPIs) and device interrupts within the IMSIC, causing hardware resource overhead to scale multiplicatively with both the per-file size and the total count of S/VS-files — a structural coupling that fundamentally limits vCPU interrupt pass-through scalability.
To address this, we propose the Software-interrupt MSI Controller (SMSIC), an AIA extension that explicitly decouples IPI from the IMSIC external interrupt hierarchy and establishes a dedicated MSI delivery path for the software interrupts defined in the RISC-V privileged specification. By fully decoupling the IPI path from the device interrupt path, SMSIC reduces the per-VS-file IPI resource to a single interrupt entry, comprising only one enable bit and one pending bit, thereby supporting large-scale VS-file deployment at minimal hardware cost (for both the per-hart and SoC IPI merging & absorption components). Furthermore, with the IPI path isolated, IOMMU MRIF can scale the number of virtualization interrupt files to support larger-scale deployments of vCPU interrupt pass-through, effectively taking over the scalability role from native IMSIC VS-files.

The complexity of modern electronic systems has increased significantly over the past decades due to continuous technological advances. To cope with this growing complexity, data structures, algorithms, and the underlying hardware platforms used in Electronic Design Automation (EDA) must be continuously improved. Decision Diagrams (DDs) constitute a fundamental graph-based structure for formal verification, enabling efficient representation and algorithmic manipulation of switching functions. Owing to their practical relevance, numerous optimizations have been incorporated into existing DD software packages. However, these optimizations are typically designed in an architecture-agnostic manner and do not explicitly exploit characteristics of a specific target platform. As a consequence, architecture-specific optimization opportunities may remain untapped. In this work, a transaction-level analysis of a representative DD package is conducted using a RISC-V-based trace analysis tool to investigate this potential. The study reveals recurring instruction sequences with strong potential for hardware-level aggregation, enabling more efficient hardware designs. Furthermore, the derived insights provide guidance for higher-level software optimizations.

The EAI8800 is an automotive-grade high-performance dedicated chip for CMS electronic mirrors built on the RISC-V CPU developed by ESWIN Computing. Adopting a heterogeneous multi-core RISC-V CPU consisting of two large cores and one small core, ESWIN computing self-developed ISP and tightly-coupled video processing architecture. This single chip realizes the full-link workflow of collection, processing and display, addressing the pain points of traditional general-purpose chips such as high latency, high power consumption and high costs.
It boasts outstanding core performances: the camera-to-panel latency is no more than 16.6ms with power consumption below 500mw. It supports 1920×1080@60FPS as well as HDR and night vision enhancement, conforms to ASIL-B functional safety standards.

Functional verification dominates modern SoC development effort, yet migrating simulation testbenches to FPGA emulation typically requires proprietary tools, expensive licenses, and
significant manual RTL adaptation-particularly for designs using DPI-C calls, multi-cycle timing blocks, or system tasks like $display and $finish. We present Loom, a fully open-source
toolchain that automatically transforms unmodified simulation-grade SystemVerilog into FPGA-synthesizable RTL with complete host communication infrastructure. Built on Yosys, Loom
applies five composable compiler passes-memory shadowing, reset extraction, DPI-C bridge instrumentation, scan chain insertion, and AXI-Lite emulation wrapping-to close the semantic
gap between simulation and emulation. We validate Loom end-to-end on a Snitch RISC-V core running on a Xilinx Alveo U250 with no manual source modifications, demonstrating DPI argument
passing, scan-based state capture/restore, and host memory preloading via PCIe XDMA.

Early-stage performance estimation plays a critical role in HW/SW co-design. It enables SW development prior to silicon availability while guiding HW architectural exploration. These activities are inherently iterative and therefore require simulation environments that are sufficiently fast to evaluate SW optimizations and HW design alternatives efficiently.
Cycle-accurate simulators provide highly precise execution-time estimation but are often too slow for evaluating realistic workloads. Instruction Set Simulators (ISSs), in contrast, offer significantly higher simulation speed but lack accurate timing information. Abstract performance models represent a promising compromise; however, existing handcrafted approaches remain labor-intensive and difficult to generalize.
We present an automated methodology for generating Machine Learning (ML)-based performance models from cycle-accurate simulations and integrating them into fast ISS environments. The approach targets the 64-bit RISC-V core CVA6 and is implemented with the open-source emulator QEMU.

Most existing educational tools for RISC-V focus on either hardware or software development, rarely both. PicoNut is an open, synthesizable RISC-V processor and system platform designed for academic education and rapid prototyping. By using SystemC-RTL as the main hardware modeling language, modules can be arbitrarily replaced by C/C++ software implementations. This allows to build full RTL as well as software based simulators for highly efficient and cycle-accurate simulations of complete systems. Even emulations of external hardware are possible, for example, by implementing screen hardware with a Qt-based GUI. To any system simulator, GDB can be attached for software debugging.

To demonstrate the platforms capabilities, students implemented a retro game console featuring custom peripherals and several ports of classic games. Through hands-on engagement with real hardware and software challenges, PicoNut empowers students to develop a comprehensive understanding of digital design, computer architecture, hardware-software codesign, and embedded systems development.

This live demonstration showcases GAPses, an ultra-low-power smart-glasses platform based on an ultra-low power RISC-V multicore processor (GAP9), enabling always-on, real-time, energy-efficient edge processing of electrooculography (EOG) and electroencephalography. GAPses performs on-device signal processing and machine-learning inference, converting raw biosignals into events without cloud compute or continuous high-bandwidth streaming, enabling energy-scalable and privacy-preserving operation. In the demo, dry electrodes integrated into the glasses frame capture horizontal/vertical EOG, and an on-device lightweight CNN running on GAP9 classifies saccadic eye movements from these EOG signals in real time. The resulting eye-movement events are transmitted via BLE to a laptop running a visualization application, which displays the CNN outputs alongside filtered EOG traces. The classification stream drives multiple interactive scenarios, including grid control, a Tetris game, and live class-probability visualization. During the demo session, we will run the complete pipeline live: a team member will wear the glasses and perform a sequence of saccades to trigger on-device CNN inference. The GUI updates in real time with predicted classes and EOG traces, allowing attendees to observe latency, robustness, and privacy benefits of RISC-V-based embedded biosignal inference in a practical wearable form factor. Overall, the demo highlights GAPses as an open, fully wearable research platform and illustrates how parallel RISC-V compute enables always-on neural interfaces by executing sensing, inference, and event-level decisions locally without cloud dependence or continuous high-bandwidth streaming.

Non-Terrestrial Networks (NTN) require software-defined payloads to stretch the lifetime of space-components, while meeting strict real-time and power constraints. We evaluate the end-to-end 5G NTN up&downlink on a single rv64gc core. Measurements show that 273× speedup is needed to run the uplink in 1ms transmission time interval (TTI). We argue that programmable decoupled vector datapaths, implementing the RISC-V "V" extension are the key to bridge performance gaps, while preserving long term flexibility for space-grade systems.

The emergence of the open-source RISC-V Instruction Set Architecture has significantly democratized CPU and SoC design across a wide range of applications. By enabling companies to implement and customize their own processor architectures, rather than relying on proprietary solutions from a few vendors, RISC-V allows architectures to be tailored to specific application requirements. However, CPU and SoC development remains complex and demands substantial design and verification expertise. To address this challenge, several academic and industrial reference platforms have been introduced to accelerate RISC-V–based SoC development. This abstract presents ALPES, a versatile SoC platform built around cores from the OpenHW Foundation. ALPES includes an application-class chipset based on the CVA6 processor, as well as multiple secondary chipsets built around the CV32E40P core, targeting safe and secure real-time use cases. ALPES provides a robust, pre-verified foundation for ASIC projects, supporting several research projects focused on the RISC-V ecosystem.

We present a coverage-driven framework that optimizes RISC-V smoke regressions by decomposing VCS coverage into feature-specific subsets via tag-based pattern matching, ranking tests via greedy set cover, and flagging runtime outliers. Applied to a 978-test production suite drawn from a larger regression pool of 10,000 tests, the framework cut smoke tests by 40% and peak test runtime by 63%, while improving coverage on key architectural features-including +64% (SMRNMI), +53% (timer), and +25% (counters)-with modest regressions on a few features (median <3%), all within project thresholds.

Radiation-induced bit-flips in on-chip memories threaten the reliability of processor-based systems, particularly in aerospace applications. This work introduces ECC-based hardening for the HPDcache, an open-source L1 data cache compatible with RISC-V cores (e.g., CVA6). The design enables Single Error Correction and Double Error Detection (SECDED), thereby protecting SRAMs from transient faults. A scrubber further mitigates multi-bit errors by periodically refreshing cachelines. Implementation of an 8 KiB cache configuration in 45 nm technology shows a 2.1% core area overhead and an 8% clock frequency reduction. This is a first step towards a fully open-source RISC-V core with both safety features and a high-performance memory subsystem to address the increasing computing demand in aerospace applications.

The gem5 simulator is a widely used tool for microarchitectural research, but often incurs prohibitive execution times. gem5 mitigates this cost through checkpoint-based resumption, yet existing checkpoint-generation mechanisms remain slow, non-portable, or both---significantly limiting iterative hardware-software exploration.

We introduce QUICK (QEMU Internal Checkpointing for gem5), a framework that enables fast, automated, and deterministic generation of gem5-compatible checkpoints directly within QEMU.
QUICK integrates full-system checkpointing into QEMU’s TCG engine, capturing architectural, memory, and essential device state without external orchestration. QUICK substantially reduces checkpoint-generation overhead while preserving existing gem5 workflows, enabling scalable and systematic microarchitectural studies.

Initial validation demonstrates correct cross-simulator state transfer and consistent workload resumption.

FPGA fault injection (FFI) is a well-known technique for verification and robustness assessment of critical systems. However existing FFI tools for current generation FPGAs support only FPGA-specific fault models irrelevant for ASIC prototypes, and feature very coarse-grain analysis insufficient for localization of dependability bottlenecks in the design. To address these limitations we have developed a bit-accurate FFI tool (BAFFI), capable of emulating ASIC (RTL) faults at the level of individual netlist cells. This paper explains how BAFFI can be used to obtain robustness estimates for RTL designs and exemplifies this through a case study of an open-source RISC-V SoC.

Building on the long-standing use of programmable system-on-chips (SoCs) for edge computing in other domains, this work explores their early adoption in application-specific integrated circuit (ASIC) designs for high-energy physics (HEP) experiments, targeting optimization from design through in-field operation. From front-end detector readout in harsh radiation environments to infrastructure monitoring such as beam and radiation level surveillance, radiation-hardened ASIC SoCs could benefit a range of HEP applications. Current efforts focus on programmable SoCs for control tasks and local data processing such as chip calibration, with physics data processing remaining a longer-term prospect. Beyond HEP, such fault-tolerant techniques, including triple modular redundancy (TMR), hardened interconnects, and memory protection, are equally applicable to safety-critical embedded controllers in domains such as automotive and industrial control systems. In this context, SoCMake, part of the System-on-Chip Radiation-Tolerant Ecosystem (SOCRATES), is being actively developed and used to produce prototype chips. One such chip is TriglaV , a fully radiation-hardened prototype ASIC designed for reliable operation in the radiation environment typical of Large Hadron Collider (LHC) detector front-end electronics. This paper reports on the current status of SOCRATES/SoCMake and the test results of TriglaV, as well as the ongoing work and future directions for the platform.

Modern processors delegate power and thermal management to dedicated Power Control Systems (PCS), communicating through kernel-mediated interfaces such as SCMI or the emerging RPMI.
Prior work has shown that end-to-end control quality is dominated by the power-management policy rather than by interface latency, leaving room to choose communication paradigms based on flexibility rather than raw latency.
We integrate Micro XRCE-DDS on ControlPULP, a RISC-V–based PCS, connecting it to a user-space Agent on an ARM host via a custom shared-memory transport.
This design removes protocol logic from kernel drivers and naturally supports multi-controller coordination through a shared middleware layer. Experiments on a ZCU102 FPGA at 20 MHz show 490 μs of active processing per publication, 0.8 MB/s throughput, and a memory footprint under 11.2 KB for 32 topics. The resulting latency is comparable to SCMI [1] while enabling a more flexible communication model.

This work presents a co-simulation methodology for the evaluation of pixel detector architecture, combining two independently developed tools: PixESL, a virtual prototyping framework targeting the architectural exploration and performance assessment of pixel detector systems, and GVSoC, a full-platform simulator for RISC-V IoT SoCs.
In parallel with PixESL's development, studies on integrating RISC-V-based SoCs with pixel detector readout circuitry were carried out using GVSoC. Rather than relying on fixed ASIC readout architectures, this approach introduces a programmable processing layer alongside the pixel readout, enabling software-level control over data handling.
In the outlined co-simulation flow, PixESL generates data for a given readout architecture and set of stimuli, while GVSoC simulates the target application executing on the PULP RISC-V SoC platform. Additionally, in order to accurately capture the overhead of data movement within this chain, a virtual prototype of the DMA block responsible for transfers between pixel readout and SoC was developed. Together, these components provide a unified view of the full readout chain, from initial stimulus to processed data, opening possibilities for more informed hardware-software co-design in future detectors.

The exponential growth in RISC-V processor complexity challenges traditional functional verification. Both directed testing and constrained-random simulation are inefficient for modern architectural designs. While hardware fuzzing has emerged as a powerful alternative for uncovering deep microarchitectural bugs, existing software-based fuzzers are severely bottlenecked by slow RTL simulation speeds and suboptimal mutation strategies that lack adaptive guidance.We propose AdaMut-RV, a high-throughput, FPGA-accelerated fuzzing framework specifically optimized for RISC-V processor verification. Unlike software-bound solutions, AdaMut-RV offloads both the processor and the fuzzer onto FPGA hardware, enabling MHz-scale execution speeds. The core innovation of AdaMut-RV is an intelligent mutation-operator scheduler based on the Multi-Armed Bandit (MAB) reinforcement learning algorithm. By categorizing AFL-inspired mutation operators into nine distinct classes, our scheduler dynamically prioritizes those that yield the highest coverage gains based on real-time hardware feedback. This dynamic scheduling mechanism accelerates the exploration of processor design spaces and critical corner-case logic. Preliminary results demonstrate that AdaMut-RV significantly outperforms state-of-the-art software-based fuzzers. It achieves higher Control and Status Register Coverage while reaching the same coverage targets at a significantly faster rate.

As system complexity increases, so does the difficulty in demonstrating their overall correctness. The Monitor-Actuator design pattern is one the main approaches in the literature proposing ways to ensure that systems can work safely, even in the presence of undetected or unpatched system defects. This design pattern consists of coupling verification monitors to, at execution time, verify if a target system is executing as expected and intervene when needed. Therefore, maximizing the isolation between the target system and the monitoring unit becomes a fundamental factor to reduce mutual interference, both in functionality and in terms of computational overhead. This work presents a Monitor-Actuator proof of concept system developed for the PolarFire SoC Icicle Kit. The system consists of a target application executing on the PolarFire SoC’s processing system and a dedicated runtime verification monitor IP executing on the programmable logic unit. We detail how the monitor IP is generated from a formal specification that is used to, first synthesize it's equivalent CPP code, and later serve as input to the process of high-level synthesis of hardware description language. The description of the development process and setup is designed to serve as a reference for future applications requiring low interference hardware synthesized runtime monitors capable of detecting user-specified property violations in a platform’s hardcore and softcore RISC-V processors.

Domain-Specific architectures with accelerators for machine learning and signal processing require efficient bulk data movement and high-bandwidth access to large datasets. Such capabilities are often absent from minimal open-source microcontrollers (MCUs).
We present HyperCroc, an extension to the end-to-end open-source RISC-V Croc system-on-chip (SoC) integrating a silicon-proven HyperBus controller for off-chip DRAM and Flash memory access and a DMA engine, providing a practical MCU-class platform with streamlined plug-in support for domain-specific acceleration. HyperBus offers a low-pin-count PSDRAM interface at up to 400 MB/s, enabling bandwidth-scaled dataset access, while the DMA engine enables autonomous, high-throughput transfers without CPU intervention. HyperCroc preserves Croc’s open-source synthesis and physical implementation flow targeting IHP’s open 130 nm process design kit (PDK); the full chip can be implemented in under one hour on a consumer-grade workstation.
We further report first silicon measurements from MLEM, the first Croc tapeout, confirming that the silicon is fully functional at 72 MHz @ 1.2 V and validating the end-to-end flow.

This live demonstration showcases the integration of Carfield, a heterogeneous automotive RISC-V SoC for mixed-criticality edge intelligence applications, with SHIELD, a non-intrusive, multimodal smart steering wheel. SHIELD enables robust, redundant acquisition of physiological signals to monitor the driver’s state continuously. During the demo, dry electrodes embedded within the steering wheel synchronously measure electrocardiography (ECG), electrodermal activity (EDA), photoplethysmography (PPG), and body temperature from both hands. Raw signals are transmitted via the automotive CAN-FD protocol directly to the Carfield SoC, while simultaneously streaming to a PC GUI via Bluetooth Low Energy (BLE) or WiFi. The RISC-V core processes the incoming CAN-FD data stream in real time. It performs digital signal filtering and employs golden-standard algorithms, including the Pan-Tompkins algorithm for ECG and PPG peak detection, to analyze heart rate (HR) and heart rate variability (HRV) in both the time and frequency domains. In the live session,(see Figure 1), a team member will use the smart steering wheel during a dynamic driving simulation using BeamNG.tech. Attendees will observe the GUI updating in real time, displaying the physiological waveforms alongside the HR and HRV metrics computed by Carfield.
Overall, this demo illustrates how heterogeneous, open-source RISC-V architectures can efficiently handle vital sensor data acquisition and complex biosignal processing at the edge in a real-time automotive contest, paving the road for non-intrusive, real-time driver monitoring systems in next-generation vehicles.

Deploying high-performance AI inference on autonomous drones requires a precise balance between computational throughput and a strict 1W power envelope. This paper presents a vertical design space exploration (DSE) of the RISC-V Gemmini accelerator, scaling from 8x8 to 32x32 mesh configurations in the SkyWater 130nm process. Through an end-to-end evaluation using a YOLOv4-tiny model on the VisDrone dataset, we demonstrate a 74.75% reduction in model memory footprint via INT8 quantization and a speedup of up to 2352x compared to a RISC-V CPU baseline. Our results indicate that while the 32x32 mesh excels in peak throughput, the 16x16 mesh represents the optimal “sweet spot” for 1W-limited drone chiplets, combining high performance with manageable leakage and area.

Processor designs are increasingly complex, making verification a critical challenge in the chip development process. Traditional verification techniques, heavily reliant on software simulations and random test inputs, often fail to effectively identify complex corner cases, leading to slow convergence and high verification costs. To address these challenges, we propose a heterogeneous hardware-accelerated RISC-V verification framework that integrates FPGA acceleration with a domain-specific generative model. This framework generates semantically-aware RISC-V instruction sequences and executes them in parallel with a reference model, providing real-time coverage collection and differential checking. The system improves verification efficiency by generating high-quality test inputs and reducing the time required for coverage convergence. Experimental results show that our framework outperforms existing fuzzers in terms of both coverage and speed, achieving up to 1.27× higher coverage and accelerates verification by up to 107×(Cascade) to 3343×(DifuzzRTL) compared to state-of-the-art fuzzers, with consistently lower convergence difficulty.

This work presents a novel, highly integrated dual-core microcontroller architecture based on the RISC-V ISA, specifically designed for First Person View(FPV) Drone On-Screen Display (OSD) systems. Traditional solutions suffer from computational bottlenecks or multi-chip synchronization latency. By leveraging a specialized RISC-V asymmetric dual-core architecture, this design achieves sub-microsecond synchronization between complex flight control execution and high-framerate video rendering. Incorporating advanced ISA extensions and custom microarchitectural features, the proposed SoC successfully injects rendered OSD data during the video signal's blanking period with pixel-level precision, showcasing the potential of RISC-V in mission-critical vertical application domains.

FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale
multi-core systems increasingly exceed the hardware resource capacity of a single FPGA, limiting the feasibility of full-system emulation. To address this challenge, we introduce EMiX, a scalable multi-FPGA framework that enables distributed emulation of multi-core RISC-V architectures beyond single-FPGA resource limits. EMiX systematically partitions a monolithic multi-core design into multiple components and deploys them across multiple interconnected FPGAs, effectively exploiting inter-FPGA interconnects to balance scalability and performance without requiring fundamental RTL redesign. We prototype EMiX with a 64-core architecture across eight interconnected Alveo U55c FPGAs (scalable on core and FPGA counts), successfully demonstrating full-system execution including Linux boot. EMiX will be released as an open-source platform.

This paper presents a radiation-hardened, open-source RISC-V CVA6 core designed for space, aeronautics, and automotive applications, where Single Event Upsets (SEUs) threaten reliability or safety. The design integrates error detection and recovery in L1 caches and Dual-Core Lockstep (DCLS) with temporal diversity. For non-critical workloads, the system supports Asymmetric Multiprocessing (AMP), enabling independent core operation. Tested with Linux and Zephyr, this work is inspired by RISC-V International’s Functional Safety white paper and advances open-source, fault-tolerant computing for critical systems. It is being integrated in a new 18 nm SoC for AI.

In this paper, we present the results of the XXXXXXXX project, in which a fully open-source, parametrizable low-power floating-point unit (FPU) under HUB format has been designed and validated. This unit, implemented in SystemVerilog, supports addition, subtraction, multiplication, division, square root, and Fused Multiply-Add (FMA) operations under HUB format. This FPU has been exhaustively tested through simulation and FPGA implementations. Moreover, it has been integrated with some RISC-V cores and validated using several test benches. The development is complemented by a compiler environment that enables native FPHUB arithmetic for C and C++ programs. The proposed unit achieves a roughly 60\% reduction in area and power consumption compared with a classic IEEE FPU implementation.

Functional verification remains a critical bottleneck in modern IC development cycles. However, traditional methods, including constrained-random and formal verification, struggle to keep pace with the growing complexity of modern semiconductor designs.

While recent advances in Large Language Models (LLMs) have shown promise in code generation and task automation, significant challenges hinder the realization of end-to-end functional verification automation.
These challenges include (i) limited accuracy in generating Verilog/SystemVerilog verification code, (ii) the fragility of LLMs when executing complex, multi-step verification workflows, and (iii) the difficulty of maintaining verification consistency across specifications, coverage models, and test cases throughout the workflow.

To address these challenges, we propose UCAgent, an end-to-end agent that automates hardware block-level functional verification based on three core mechanisms.
First, we establish a pure Python verification environment using Picker and Toffee to avoid relying on LLM-generated SystemVerilog verification code.
Second, we introduce a configurable 31-stage fine-grained verification workflow to guide the LLM, where each stage is verified by an automated checker.
Furthermore, we propose a Verification Consistency Labeling Mechanism (VCLM) that assigns hierarchical labels to LLM-generated artifacts, improving the reliability and traceability of verification.

Experimental results show that UCAgent can complete end-to-end automated verification on multiple modules, including the UART, FPU, and integer divider modules, achieving up to 98.5\% code coverage and up to 100\% functional coverage. UCAgent also discovers previously unidentified design defects in realistic designs, demonstrating its practical potential.

RISC-V provides complex platform-level specifications, such as the RISC-V IOMMU, in addition to the core-level ISA to support a complete open computing platform. The RISC-V IOMMU delves into intricate hardware-software interactions, page table formats, command and fault queue handling, and multi-stage address translations that are as critical to system correctness but significantly harder to validate.
An essential part of verifying the IOMMU involves executing real-world scenarios as would be presented via Linux. However, setting up a full SoC-level environment to run Linux sequences is time-consuming and resource-intensive. As a result, critical IOMMU interactions are often validated too late or not at all.

We have developed a programmable device model that permits Linux testing of RISC-V IOMMU RTL without requiring PCIe or DMA-capable devices to be integrated into the design under test.
The device model has been pivotal in creating an emulation-friendly subsystem-level environment that integrates high-performance RISC-V cores (TT-Ascalon) with RISC-V IOMMU.
The subsystem runs Linux as the primary stimulus source, reusing the upstream kernel IOMMU driver to exercise the IOMMU implementation against the RISC-V specification with complex and realistic scenarios.

We will present the design and operation of this device model, the subsystem environment and related software, and shall share our findings, including how it enabled us to quickly uncover corner-case bugs in our IOMMU RTL and its software drivers, thereby complementing traditional IP-level validation approaches.

When the RISC-V matrix extensions effort was restructured into four complementary approaches at Summit Europe 2025 in Paris, it was a bold architectural bet — that the breadth of the RISC-V ecosystem demands not one rigid solution but a family of extensions spanning from lightweight vector-matrix primitives to fully independent matrix engines. One year later, that bet is paying off. This talk reports on the rapid progress across the matrix extension family as two of the four extensions — the Integrated Matrix Extensions (IME) and the Vector Matrix Extensions (VME) — converge on specification freeze. We trace the architectural decisions that brought IME and VME from concept to maturity: algebraic tile geometry that scales naturally with VLEN, the deliberate reuse of RVV state for seamless software integration, and the introduction of dedicated accumulator registers to unlock higher computational intensity where implementations demand it. Crucially, work is starting to unify IME and VME through a common LLVM-MLIR lowering path — giving compilers and AI/ML frameworks a single abstraction that targets both extensions, ensuring that the software ecosystem scales with the hardware rather than fragmenting across it. For Europe's semiconductor industry — from research institutions and startups to established design houses — standardized, open matrix extensions represent a strategic opportunity: competitive AI/ML and HPC capability on an open ISA, free from proprietary lock-in. RISC-V matrix support is no longer a roadmap item. It is arriving.

Europe has been a key contributor to the development of modern computing, inventing fundamental hardware and software technologies, and growing highly successful companies with worldwide reach. But in a new era of AI and Cloud computing, how can Europe redefine its approach and put itself at the forefront of computing innovation and success?

This panel will debate the European approach to computing and how RISC-V can be a powerful tool for delivering an innovative, successful, and uniquely European vision of the future of computing.

What is the vision of European computing sovereignty, and to what extent is this becoming reality?
What is the role of the policy makers on the European strategy and the relative influence of European organizations, national entities and venture capitals/investors?
What are the main differences between the US, Asia, and Europe in terms of sustainability of the industrial ecosystem?
How do the laws and rules of Europe influence our success?
What are the technologies and applications Europe needs to deliver?
Where are its strengths and high potential application spaces?
How can we close the gap regarding maximizing the technology transfer between research/academia to industry?
How can we train the highly skilled workers needed?
What is the balance between addressing domestic needs and an international market?

Moderator:
Florian Wolhrab - Open Hardware Foundation

Panelists:
Georgi Kuzmanov - Chips-JU
Sachiko Muto - Open Forum Europe
Enrico Sangiorgi - Chips-IT
Edward Wilford - OMDIA
Fabien Piuzzi - Scaleway

An end-to-end case study evaluating cloud-connected workloads on CVA6 platforms is presented.
System behaviour under increasing telemetry loads is analysed using CAN trace replay.
The results provide empirical insights into the suitability of open RISC-V platforms for industrial deployment and highlight further optimisation.

In RISC-V based systems, a key security mecha-
nism is the Input-Output Physical Memory Protection (IOPMP)
subsystem, which enables controlled access to shared memory
and peripherals by non-core initiators [1]. While the specification
defines functional behavior, the availability of a publicly available
cycle-accurate reference model will encourage early SoC-level
integration.
This paper presents an open-source cycle-accurate IOPMP
reference model consisting of a SystemVerilog wrapper integrated
with a C-based functional reference model. The SystemVer-
ilog wrapper models pipeline timing, transaction ordering, and
standard bus interfaces, while the C-based reference model
provides specification-compliant functional evaluation of address
matching, permission checking, and priority resolution. The
combined architecture enables both functional correctness and
timing-accurate system-level validation.
The model supports AMBA AXI4 for transaction enforcement
and AMBA AHB3-Lite for configuration, to enables seamless re-
placement with actual RTL. A reusable suite of architectural-level
bare-metal tests is provided, and the approach is demonstrated
through integration in an open-source CVA6-based SoC [4].
Index Terms—RISC-V, IOPMP, SoC Security, Reference
Model, Cycle-Accurate Modeling

This demo showcases complete end-to-end Transformer training locally on the GAP9 RISC-V MCU. On-device training is crucial for applications that operate in dynamically changing environments. One example is biosignal DNNs in wearable devices, where cross-subject transfer and long-term temporal drift degrade performance. RISC-V MCUs are already widely used for edge DNN deployment. However, most existing work focuses either on inference only, or on fine-tuning a small portion of the network.

We extended the Deeploy compiler to generate training code. Deeploy generates bare-metal C code from an ONNX graph and is tailored for efficient inference. To support training, we added critical kernels such as optimizers and in-place gradient accumulators. We also extended the ONNX runtime training API to generate graphs optimized for edge deployment. This extension is released at https://github.com/pulp-platform/ONNX4Deeploy. To reduce the memory footprint of batching required for stable training, we implement gradient accumulation. The demo video showcases the full workflow, from training graph optimization to code generation and on-board execution. The video is available at https://drive.google.com/file/d/16BMiHn0jyMvScFJD7AGTwHpA4Rc0aMnC/view?usp=drive_link and will be uploaded to the Pulp Platform YouTube channel.

The increasing demand for domain-specific architectures from various domains such as Artificial Intelligence (AI),High Performance Computing (HPC), and automotive systems is reshaping modern System on Chip (SoC) design,requiring faster iteration cycles and deeper hardware/software integration. While the open ISA RISC-V enablesunprecedented architectural flexibility, it also dramatically expands the design space across system, micro-architectural,and implementation levels. Efficiently navigating this complexity remains a key challenge for both academia and industry.The A-DECA framework is a design space exploration framework developed within the SoC Planner project to accelerateproductive SoC design. A-DECA enables a structured and modular exploration from high-level architectural configurationdown to synthesis-aware micro-architectural evaluation, effectively bridging the gap between system-level modeling andimplementation constraints.Our methodology leverage the open-source RISC-V design flow Chipyard to develop a hardware/software co-designsolution that supports automated configuration generation, parameter tuning, and quantitative performance, power, areatrade-off analysis. By reducing manual exploration effort and formalizing early-stage architectural planning, A-DECAsignificantly improves design productivity and accelerates pre-silicon decision-making. The framework reinforces theopen-source chip design ecosystem and lays the foundation for scalable, chiplet-oriented RISC-V architectures. Its plannedopen-source release aims to further enable reproducible research, industrial adoption, and collaborative innovation infull-flow RISC-V SoC development.

The growing demand for near-sensor processing exposes a gap: nonlinear activation functions still fall back on the host CPU, incurring energy and latency penalties. We present TOXOS, a RISC-V CORDIC coprocessor tightly integrated into X-HEEP via the Core-V eXtension Interface, achieving up to 27× speedup over a hardware FPU (CVFPU) with minimal area overhead.

Functional verification of RISC-V multi-core IPs is bottleneck by the sequential nature of convectional CPU-based event driven simulation, where coverage closure timelines scale linearly with core count and configuration complexity. This paper presents a GPU- accelerated parallel simulation framework that offloads stimulus generation, constraint solving, and concurrent coverage computation to GPU hardware while retaining UVM testbench orchestration on the CPU host. The framework employs a heterogeneous partitioning tasks including constrained-random transaction generation, functional coverage bin evaluation, and reference model computation are parallelized across GPU threads using CUDA kernels. The control, DUT RTL simulation, and sequential verification logic, ensuring complete compatibility with existing verification flows. Evaluated on RISC-V IP configurations ranging from 2 to 32 cores with AXI4 interconnect and MESI coherency protocol, the framework achieves up to 22x simulation speedup, reduces coverage closure time from 44 hours to 14 hours, and reaches 99 percent functional coverage versus 93 percent for CPU-only baselines within the same wall clock budget. The GPU acceleration advantage scales near -linearly with core count, making it particularly valuable for emerging many core RISC-V designs targeting automotive and data-center applications. The approach requires no modification to existing RTL or UVM testbench architectures, integrating via a lightweight GPU dispatch layer that operates on standard simulation interfaces.

Writing verification stimulus for RISC-V processors requires deep expertise across ISA specifications, microarchitectural implementation, and test framework APIs. We present an LLM-driven multi-agent framework that transforms a brief natural-language scenario description into a comprehensive, executable RISC-V test generator. Five specialized AI agents form a sequential enrichment
pipeline: an ISA expert expands intent into architecturally complete scenarios, an RTL analyst reads hardware source code to inject microarchitecture-targeted stress patterns, a framework specialist maps steps to concrete API calls, a builder synthesizes deployable code, and a validator ensures correctness through static checks and instruction-set-simulator execution. On the RISC-V Svadu extension, a 3-line scenario yields 490 lines of validated, simulation-passing code in under 13 minutes—a ∼40× speedup versus an estimated∼8 hours of manual effort.

The Raspberry Pi Pico2 is an ideal platform to showcase the state of RISC-V capabilities in the realm of embedded real-time systems. When switching from the ARM Cortex-M33 to the RISC-V Hazard3 CPU cores everything else stays the same: memory subsystem, clock tree, peripherals. This allows for an apples-to-apples comparison of the relative strengths and weaknesses of the two CPU implementations by compiling the same C code for both architectures. We present a detailed comparison of relative performance and assembly code differences as well as insight on how much effort using RISC-V instead of ARM on the RP2350 MCU powering the Pico2 really adds.

The growing demand for artificial intelligence, scientific computing, and large-scale data analytics has significantly increased the need for massively parallel computing architectures. Modern GPUs provide high computational throughput by executing thousands of concurrent threads, but most existing GPU architectures remain proprietary, limiting open architectural innovation and research. This paper presents Vishwa, a scalable RISC-V based General Purpose GPU (GPGPU) architecture designed to enable open and extensible parallel computing platforms. The architecture adopts a hierarchical compute model composed of Vishwa Compute Clusters (VCLs) containing multiple Vishwa Compute Cores (VCCs) that execute threads using a Single Instruction Multiple Thread (SIMT) execution model. Each compute core integrates specialised Vishwa Matrix Cores (VMCs) designed to accelerate matrix-intensive operations commonly used in machine learning workloads. Work distribution across the architecture is managed by a global Vishwa Work Distributor (VWD) that schedules workloads across available compute clusters. The architecture is supported by a complete software ecosystem through the CHAKRA compiler stack, which integrates with LLVM to provide kernel compilation and runtime execution support. The compute core architecture has been implemented and validated on an FPGA platform, demonstrating functional correctness of the execution pipeline and SIMT execution model.

The Cincoranch Test Chip 1 (TC1), manufactured in Intel3 technology, integrates three RISC-V processors
with a Vector Processing Unit (VPU) accelerator and an HPC-oriented cache hierarchy. This work presents the
electrical characterization of the silicon, the power-on bring-up procedure, and basic functionality verification
of the TC1 chips. Initial measurements focused on power consumption and temperature of each core under idle
conditions, providing insight into the chip’s behavior and readiness for further workload testing.

Verification remains a key bottleneck in the design of modern RISC-V processors, particularly for deep corner cases that are difficult to reach with conventional verification techniques. Coverage-guided hardware fuzzing provides fast exploration, but often relies on coarse-grained coverage feedback and blind mutation, leading to shallow exploration. Symbolic and concolic methods offer control path reasoning, but their practicality is limited by path explosion and high solver cost on realistic RTL processor designs.
We present a concolic execution guided hybrid whitebox fuzzing framework for RISC-V processors with FPGA acceleration. The framework combines RTL instrumentation, selective concolic execution, and hardware fuzzing to balance exploration of hard-to-trigger behaviors with fuzzing efficiency. It extracts the processor control-flow graph from RTL, instruments synthesizable control path monitoring, and prioritizes high-value unexplored paths. We further provide FPGA implementation to accelerate the hybrid whitebox fuzzing process through an end-to-end heterogeneous architecture.
We evaluate the approach on open-source RISC-V processors, including Ibex, CVA6, and PicoRV32. Results show that our approach can achieve 1.33x higher coverage than SOTA fuzzers and explore deep corner coverage points that are difficult to trigger with existing approaches.

In certain scenarios computer systems have to deal with both little-endian and big-endian data regardless their native endianness. A RISC-V extension that makes it possible to remove the overhead introduced when dealing with foreign-endian data is proposed. It can be implemented with little engineering effort and negligible impact on performance and hardware resources. Preliminary results show that the extension can remove a 62% or 37% of foreign-endian data processing overhead when compared to software solutions using the base Instruction Set Architecture (ISA) or the currently available bit manipulation extensions respectively. This performance boost can benefit both new and legacy software once compiler and library support is put in place.

We present Wolvrix, an open-source infrastructure that ingests Verilog-2005/SystemVerilog into GRH (Graph RTL Hierarchy), an SSA-based graph intermediate representation, and supports composable transformation passes with Verilog re-emission. Wolvrix models complex SystemVerilog semantics, including multi-event registers, multi-port memories, blackboxes, cross-module references, and DPI-C calls, within a uniform graph structure amenable to analysis and transformation. We describe GRH and Wolvrix's architecture, and present roundtrip re-emission on XiangShan and XuanTie C910 plus RepCut partitioning on XiangShan.

This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implements the rv64gch ISA and features advanced support for real-time execution, including TLB partitioning and locking for predictable address translation, a dynamically reconfigurable scratchpad mode in the L1 caches for deterministic memory access, and low-latency interrupt handling via an enhanced interrupt controller combined with hardware-assisted context stacking. With real-time features enabled, CVA6-RT achieves an interrupt latency of 12 cycles, comparable to that of simpler Arm Cortex-M microcontrollers, and 10x lower than the baseline CVA6 core.

Recent announcements have shown the viability of end-to-end open-source (OS) Linux-capable RISC-V systems on chip (SoCs). However, practical application and software development platforms require efficient non-volatile storage, which is not adequately served by common SPI-based interfaces due to their limited throughput. Secure Digital (SD) cards are the de facto standard storage medium for embedded Linux systems; efficient SD host controller (SDHC) integration is thus essential for open-source RISC-V platforms.
We present an OS SD host controller interface (SDHCI) peripheral integrated into the end-to-end OS Cheshire RISC-V SoC platform. The controller and its software stack are designed with full awareness of CVA6’s memory system and Linux driver behavior; during evaluation, we identify a significant performance bottleneck caused by the RISC-V memory model and CVA6’s implementation of the fence instruction, which flushes the pipeline and data cache on memory-mapped register accesses when cache management operations (CMOs) are unavailable. By customizing the driver’s register access paths and avoiding unnecessary fences, we substantially reduced this overhead. Our fully OS controller achieves up to 11.1 MB/s throughput, approaching the 12.5 MB/s limit of the SD interface and providing up to 6.5 times the throughput of SPI-based storage.

Symbolic Quick Error Detection (SQED) streamlines processor verification by checking a microarchitecture-agnostic self-consistency property using bounded model checking (BMC). While effective in detecting bugs without manual property specification, SQED suffers from severe scalability limitations due to state explosion in complex designs. This paper introduces RDM-SQED to mitigate this bottleneck by reducing the resource-intensive duplicate mode with a lightweight Processor-Level Abstraction (PLA). The PLA captures software-visible behaviors through a concise set of Elementary Instructions (EIs). To further constrain the verification logic, we propose a recursive refinement algorithm that generates a minimal EI set. Experimental evaluation on an out-of-order RISC-V processor demonstrates that RDM-SQED significantly outperforms existing variants in both scalability and bug
detection efficiency, successfully identifying bugs that cause timeouts in other methods.

This paper presents the riscv-test-platform, an enhanced set of environments built upon the riscv-test-env, designed to facilitate the execution of tests and benchmarks on RISC-V architectures atop bare-metal environments. Their balance between code complexity and features make them a flexible platform to execute software in both simulated and FPGA environments, bridging the gap between the two platforms, with the advantages that each provide. The result is a set of four environments that mimic the functionalities of the original riscv-test-env, with the addition of some benchmarking features, which exercise more parts of RTL designs and help verification teams spot mismatches in the early stages of development.

Verifying modern RISC-V cores requires qualifying every merge request (MR) against a large and evolving test space spanning ISA extensions, micro-architectural features, and system-level scenarios. Manually selecting appropriate tests for each MR is time-consuming and error-prone, and does not scale with the rate of RTL changes. This work presents an AI-driven testlist generator that automatically derives MR-specific regression lists for a production RISC-V core verification environment. The tool analyzes Git diffs for an MR, infers impacted features using a combination of static rules and large language models (LLMs), and synthesizes targeted regressions across multiple test generators. The resulting flow reduces MR-qualification effort, improves repeatability, and provides a concrete path toward coverage-driven, closed-loop test selection for RISC-V core verification.

Many computational problems require the processing of large sparse matrices, where the vast majority of entries are zero. The irregular distribution of the non-zero elements in these matrices stresses the memory system resulting in performance being bottlenecked by the memory bandwidth. On parallel architectures, workload imbalances also limit performance. Graphics Processing Units (GPUs) runnning sparse matrix kernels using state-of-the-art Basic Linear Algebra Subsystem (BLAS) libraries are central in modern HPC systems. Although RISC-V application processors are gaining in performance, RISC-V based GPUs are in an early stage of development. We benchmark sparse kernels both on modern HPC-grade GPUs and on Vortex, a RISC-V GPU that is gaining adoption. We analyse their performance under memory-bound workloads and report the gaps in software and hardware required to enable efficient sparse BLAS processing on RISC-V GPUs.

Interest in edge inference for biomedical applications has boomed in recent years, given its benefits in terms of data privacy, low latency, and reduced cloud costs. We present Embedded ECG Processing on RISC-V(EEP-V), an end-to-end platform for multi-lead embedded ECG processing on RISC-V processors. EEP-V combines a custom multi-lead acquisition board, real-time digital signal conditioning, and on-device neural network inference in a fully local processing pipeline without cloud offloading. The platform is designed as an open-source hardware/software stack to support reproducible research on embedded cardiac monitoring. Our implementation targets a heterogeneous RISC-V architecture based on GAP9 and supports concurrent processing of up to 12 ECG leads. We validate the complete acquisition-to-inference pipeline using a medical-grade patient simulator and a reference multi-class arrhythmia classification model from PhysioNet/CinC Challenge 2021. On the deployed system, inference completes in 150 ms using 488 kB of L2 memory and consumes less than 5.47 mJ per classification, while the full pipeline consumes about 7 mJ per inference cycle. These results show the feasibility of an end-to-end multi-lead ECG processing platform on RISC-V and provide an open foundation for future embedded cardiac-monitoring research.

As artificial intelligence reshapes embedded systems, MCUs are evolving from simple control devices into intelligent, distributed computing nodes. This talk explores how RISC-V architecture and scalable AI frameworks are enabling a pragmatic, incremental approach to system transformation—particularly critical in automotive applications where safety, reliability, and legacy integration remain paramount.

Energy saving is a top priority for STMicroelectronics products. For the STxP5 embedded CPU based on the RISC-V architecture, there is a particular focus on minimizing static power when the core is inactive. Additionally, it is important to optimize the CPU restart time, silicon area, implementation complexity, and software overhead. The Ultra Low Power Retention with Warm Restart Mode addresses these challenges by maximizing power savings and reducing drawbacks typically associated with resuming operation. This solution leverages the modular, scalable, customizable, and extensible nature of the RISC-V architecture by defining and implementing a custom RISC-V extension and tailored microarchitecture.

The stringent safety requirements of the automotive industry necessitate compliance with standards like ISO 26262. Processor cores, often pre-certified to ASIL-B or ASIL-D, face certification risks when modified. This work focuses on the development of custom instructions that are integrated through Codasip’s Bounded Customization (BC) without directly modifying the core’s verified RTL. The paper details a workflow for this process and presents performance results demonstrating the acceleration achieved for key automotive and DSP algorithms, including Field Oriented Control (FOC). All extensions were consolidated into a unified custom processor, termed as the Motor Control with DSP (MCXD) core, featuring a scheduling algorithm that coordinates FOC and filtering routines. Synthesis showed an area increase of ~31%, while runtime and instruction count measurements demonstrated performance improvement of up to ~21%. These results validate that domain-specific acceleration can be achieved within the boundaries of ISO 26262.

PELT (Per-Entity Load Tracking) is an exponential decay-based per-entity load tracking algorithm in the Linux kernel. It significantly enhances the scheduler’s load awareness accuracy, response latency, and energy efficiency. However, there are still drawbacks in load tracking: The load metrics that are used are not CPU-frequency invariant. The advent of CPU frequency scaling causes task physical runtime to fluctuate with frequency, which, if uncorrected, distorts util_avg and leads to scheduling misjudgments. To address this, the kernel employs hardware counters (e.g., Intel APERF/MPERF, ARMv8.4-AMU) to implement frequency invariance accounting, ensuring util_avg remains anchored to the CPU’s maximum capacity, thereby maintaining load statistics accuracy and scheduling optimality in dynamic frequency environments.
Targeting RISC-V architectures, this proposal introduces State sensitive Counters to fill the gap in PELT
frequency invariance support. Together, these counters enable the derivation of real-time operating frequency and normalized utilization without costly synchronous queries.

Lustre powers approximately 70% of TOP500 supercomputers and is essential infrastructure for high-performance computing (HPC). Our work enables RISC-V systems to access Lustre storage clusters, addressing a critical gap in the RISC-V HPC ecosystem. The port required only 8 minimal patches (19 lines changed across 9 files) to Lustre 2.17.0, demonstrating the maturity of both the RISC-V Linux ecosystem and Lustre’s portable codebase. We validated functionality through QEMU-based testing with multi-client mount operations, FIO, and IOR benchmarks. The patches are being submitted upstream to the Lustre project for inclusion in future releases.

Driven by the need for zonal control architectures in software-defined vehicles, open-source RISC-V cores are becoming a compelling solution for automotive microprocessor units (MPUs). We introduce a 64b cache-coherent, tightly coupled cluster built upon the industry-backed OpenHW CVA6S+ core and HPDCache, capable of executing SMP Linux and RTOS kernels. A design space exploration of the core branch predictor identifies an embedded tournament configuration that reduces its area by 11.6% with no loss in accuracy. Evaluated on the Splash-3 benchmark suite, the cluster achieves a geometric mean speedup of 1.75× over a single-core baseline, and a 1.21× speedup over a prior implementation based on the scalar CVA6 and legacy cache subsystem. Synthesized in GlobalFoundries' 12 nm FinFET, the dual-core cluster incurs less than 1% per-core area overhead, with the coherent unit in the interconnect contributing only 35 kGE (1.5%) to the total cluster footprint.

Ainekko’s Agentic SoC is an open, full-stack approach to AI-native silicon that treats hardware as a programmable, composable substrate for model execution rather than a fixed target. Built on a many-core RISC-V architecture with tile-based compute and memory, the platform enables automated model-to-hardware mapping, dynamic quantization, and workload-specific system composition at packaging time, eliminating the need for per-model tape-outs.

We invert the traditional stack: models define the hardware. Our approach sits between FPGA flexibility and etching models into ASIC-level efficiency, delivering high performance and practical economics while remaining fully programmable to adapt to rapidly evolving models and architectures.

Our programmable RISC-V fabric has been validated with a 1,088-core tape-out and is designed to scale to 4,000+ cores. On top of this foundation, we have built a set of open building blocks across RTL, compiler, and runtime, which we are open-sourcing through the OpenHW Foundation (CORE-ET project) and AIFoundry. This open ecosystem enables developers, researchers, and AI agents to co-design across the full stack and directly optimize execution on hardware. This openness is essential: supporting fast-moving models, heterogeneous edge workloads, and agent-driven development requires a system where new kernels, quantization strategies, and architectural innovations can be introduced and composed without vendor constraints.

Climate change and environmental degradation demand new approaches for large-scale, continuous, and intelligent sensing of natural ecosystems. The Internet of Trees proposes a distributed infrastructure where smart environmental probes deployed in forest environments become active nodes in a real-time environmental intelligence network—requiring computing platforms that are low-power, secure, adaptable, and affordable.

RISC-V offers a powerful foundation for next-generation environmental sensing systems. As an open-source ISA, it enables technological flexibility, design transparency, and long-term digital sovereignty, while allowing customized processors tailored to edge AI, wireless sensor networks, secure communication, and ultra-low-power operation. These features are especially critical for climate-oriented deployments in remote, resource-constrained environments.

This keynote presents the Internet of Trees as a case study for the strategic use of open-source microprocessor technology, discussing how RISC-V supports distributed sensing, local data processing, trusted operation, and scalable integration with cloud-based environmental platforms. Beyond technical efficiency, open microprocessor ecosystems can strengthen local innovation and sustainable semiconductor capacity—making RISC-V not merely a processor architecture, but an instrument for building resilient, sovereign infrastructures for planetary monitoring.

The Internet of Trees illustrates how open silicon can connect sustainability, intelligence, and environmental stewardship, a perspective particularly relevant for emerging economies seeking both climate action and technological autonomy. The convergence of open hardware and environmental intelligence may define a new class of digital infrastructure for the living world.

RISC-V can be one of its most important enabling technologies.

A small lunar rover named "LEV-1" made surface mobility exploration on the Moon in January 2024. This was the first lunar exploration robot in our country. LEV-1 was installed in the lunar lander "SLIM" and was deployed onto the Moon surface just before landing.

LEV-1 explored over the landing area fully autonomously after the deployment. The obained data inclusing images were directly transmitted to the Ground with no relay by the lander.

The onboard computer of the rover used a RISC-V soft-core CPU implemented within the FPGA. The system is one of the world's first onboard computers using a RISC-V processor being operated on the Moon.

This paper describes the configuration of the RISC-V controller installed on LEV-1 rover as well as the technical background for using RISC-V in space applications.

We present Bianbu LXQt, a user-oriented desktop environment for RISC-V platforms built on a deeply adapted LXQt software stack, optimized for real hardware such as SpacemiT’s K1 and K3 SoCs. Unlike straightforward ports that assume x86-like hardware standardization, this work addresses common RISC-V Linux challenges, including fragmented peripheral support and the absence of a unified hardware abstraction layer. SpacemiT's CPUs integrate AI-oriented instruction extensions such as IME, enabling CPU-based inference without discrete GPUs or NPUs, requiring coordinated adaptation across the OS and AI frameworks.
Preserving LXQt’s lightweight design, we redesigned the UI and interaction logic to improve responsiveness and visual consistency on resource-constrained RISC-V systems. Development was accelerated using AI-assisted tooling, while continuous feedback from educators and early adopters guided iterative fixes for lag, crashes, and complex configuration—letting users focus on creation, learning, and development rather than system tuning.
The full software stack is open source with reproducible builds and modular components. We proved educational AI examples covering image recognition, speech processing, video analysis, and large language model inference, all with intuitive GUIs. Frameworks including ONNX Runtime, llama.cpp, and Ollama run reliably, demonstrating the feasibility of RISC-V systems for AI deployment and local AI development.
Through practical system integration, community-driven iteration, and accessible AI tooling, this work shows RISC-V can deliver a polished, daily-driver desktop environment—moving beyond a demo into a trusted open platform for developers, educators, and innovators.

Cryptographic hash algorithms for zero-knowledge proof systems often rely on prime-field S-box kernels such as x⁷ mod p over 31-bit fields. We accelerate this class of S-box primitives on a 4×4 coarse-grained reconfigurable array (CGRA) integrated within a RISC-V SoC. As a case study, we use the BabyBear instantiation adopted by the state-of-the-art Poseidon2 hash function, employing Barrett reduction to avoid software division on the host core. Our mapping decomposes operands into 8-bit limbs across CGRA processing elements and exploits the toroidal mesh for carry propagation in 4 hops. Compared to a hand-optimized baseline, we achieve 1.26× speedup and 25.7% energy reduction; versus an automatic compiler, we improve by 6.6× speedup and save 82% energy. Cycle-accurate RTL simulation of a full Poseidon2 integration shows ~3.3× fewer cycles than the RISC-V host for the full 141-invocation workload at 100 MHz (even a ~1.3× reduction at 250 MHz).

The semiconductor industry increasingly requires engineers skilled in both hardware design and software execution. This contribution presents a RISC-V-centric educational pipeline developed at our institute, bridging foundational bachelor's coursework and specialized master's programs. We outline three core courses that integrate practical hardware design, custom ISA extensions, and full-stack security. First, a computer organization course teaches students hardware design in SystemVerilog with the goal of modifying and extending a full RISC-V CPU. Second, a hardware security course tasks students with both the implementation of security-related hardware primitives for open-source RISC-V cores, and the development of software to interact with the extended hardware. Finally, a secure system architectures course addresses memory safety through full system prototyping, requiring students to modify the RISC-V Spike simulator and write custom LLVM compiler passes. This hands-on approach provides the ecosystem with engineers equipped to tackle modern microarchitectural and security challenges.

To enhance processor performance on HPC and AI workloads, the RISC-V Vector Extension (RVV) was ratified by RISC-V International in 2021. Vector processing enables data parallelism by operating on vectors rather than scalars, which studies have shown can improve performance on vectorized workloads by up to eight times or more on some workloads, significantly increasing memory bandwidth requirements compared with scalar processors. The proposed RISC-V Matrix Extensions further multiply the challenges, placing even greater demands on the memory subsystem. This increased data throughput requires architects to re-evaluate their long-held assumptions about SoC architecture. While many studies focus on the software implications of vector and matrix extensions, this paper explores the challenges and evaluates possible solutions for performant and power-efficient, optimal SoC hardware architectures.

This demo introduces Reptiles - Repeated Tiles of Sargantana, an open-source RISC-V multicore architecture designed to support research in HPC systems. Reptiles builds upon the OpenPiton manycore framework by integrating multiple Sargantana RISC-V cores and enhancing the memory hierarchy and interconnection network to improve scalability and performance. The goal is to provide an accessible and flexible platform for researchers to develop, experiment with, and optimize HPC workloads using open hardware.

Reptiles replicates Sargantana tiles within OpenPiton’s architecture and introduces several architectural improvements. These include a configurable network-on-chip width (from 64 up to 704 bits), flexible cache block sizes, adjustable numbers of miss status holding registers (MSHRs), improved cache sizes and associativities, parallel SRAM access in the L2 and the last-level cache, and configurable number of memory controllers. The system also integrates the High-Performance Data Cache (HPDcache) as an L1 data cache and enhances the Sargantana core with broader support for RISC-V extensions, particularly the RISC-V Vector Extension (RVV 1.0). Additional improvements include debugging support, performance counter access in Linux, and enhanced RTL simulation features such as checkpointing.

In this demo we show a fully functional FPGA prototype of Reptiles with four Sargantana cores booting Linux and running OpenMP benchmarks such as the NAS Parallel Benchmarks, interactive UART console games, and graphical applications by performing X11 forwarding over SSH. Overall, Reptiles demonstrates that open-source RISC-V multicore systems can effectively support scalable HPC research and experimentation.

The RISC-V Vector Extension (RVV) adopts a vector-length agnostic (VLA) model for exploiting data-level parallelism. We argue that this abstraction imposes significant costs in real silicon: control logic complexity, implicit state tracking in out-of-order pipelines, and runtime overhead that erode VLA’s theoretical portability benefits. Drawing on production experience with the ET-SoC-1, a 1088-core
RISC-V processor, we present ET-SIMD, a fixed-width 256-bit packed SIMD extension that overlays the standard F extension register file. In Flynn’s Taxonomy [2], ET-SIMD is a classical SIMD design: scalar and packed instructions share the same register file, a pattern well understood by GCC and LLVM autovectorizers and proven on competing ISAs, yet absent from RISC-V. We describe the extension’s architectural rationale, its relationship to contemporary packed SIMD practice, and its availability through the AI Foundry initiative.

As High-Performance Computing (HPC) advances towards the Exascale era, energy efficiency has become the primary design constraint. In HPC systems, the Floating-Point Unit (FPU) is instantiated in massive numbers to support parallel workloads, that require huge number of floating point computations. Consequently, the FPU becomes a dominant consumer of dynamic power within the chip. This work presents an energy-optimized FPU for RISC-V Vector Processing Units. To address the inefficiencies of standard unified FMA datapath, we propose a Split-Path FMA micro- architecture tailored for the RISC-V Vector specification. Our design integrates the physical separation of the arithmetic pipelines with vector-aware clock gating and operand isolation. Evaluated in a commercial 4nm technology at 2 GHz, the optimized design demonstrates up to a 29% increase in energy efficiency for mixed-arithmetic workloads and a 7.8% performance speedup in vector reduction-heavy kernels.

Conservative/qualification-sensitive RISC-V ecosystems tend to view large architectural changes as costly due to hardware overhead, integration effort, software/toolchain adaptation, and assurance scope. This is especially relevant for platforms intended for harsh environments and long lifetimes such as space-oriented and radiation-tolerant platforms (e.g., NOEL-V). At the same time, there is growing interest in on-board processing to support time-critical decisions close to the sensor and reduce reliance on transmitting raw sensor data, increasing the demand for compute-intensive Edge-AI inference. In such settings, full vector architectures can deliver high throughput, but they tend to introduce additional architectural state and increase integration complexity across the hardware and software stack. Therefore, to introduce data-parallel acceleration with minimal disruption, we evaluate packed-SIMD as a small-change alternative based on packed subword parallelism that remains close to the existing register and memory model.
We consider two packed-SIMD options: SWAR and SPARROW. On a NOEL-V softcore, we implement SWAR operator kernels for the most computationally expensive layers and integrate them into the math backend of a space prequalified inference engine, running on a space prequalified RTOS (RTEMS6 SMP). Using a hardware SWAR unit for packed subword operations, we report full-model results with and without SWAR acceleration, showing improved inference performance without requiring a full vector architecture. Finally, we outline future work extending the same backend methodology to SPARROW to compare performance across packed-SIMD options.

RISC-V deployment in embedded systems, IoT, and edge AI has outpaced developer education: most tutorials target C/C++ and cover only basic microcontroller tasks, leaving a gap for building ML systems with modern toolchains. RISCVML addresses this with a Rust curriculum spanning 172 chapters across seven modules, from beginner hardware to on-device ML inference.

The curriculum uses Espressif RISC-V SoCs: the ESP32-C3 (BLE 5.0, ~€3) and ESP32-C6 (Wi-Fi 6, Thread/Matter, ~€4) introduce Rust fundamentals — GPIO, sensors, power management, and wireless protocols. The ESP32-P4 (dual core 400 MHz, AI extensions, 128 bit vector ISA, ~€25) anchors an advanced module: ISP camera pipeline, hardware accelerated 2D rendering, H.264 encoding, DMA orchestration, and vector accelerated ML inference.

These converge in a capstone: a bird detection pipeline capturing MIPI-CSI frames, running quantized detection through esp-dl, driving pan/tilt servos, and recording H.264 video — all in async Rust with ESP-IDF drivers via FFI.

By pairing Rust memory safety with production toolchains (esp-hal, esp-idf-hal) on affordable hardware, and using a mascot to make complex terminology approachable for younger learners, RISCVML lowers the barrier for the next generation of RISC-V developers — supporting Europe's push for sovereign silicon literacy.

This work presents the design of a tightly coupled near-memory computing unit compatible with a preliminary RISC-V Attached Matrix Extension. The proposed unit is designed to be integrated with a processor core through the Core-V eXtension Interface (CV-X-IF), enabling matrix operations to be decoded and executed directly in a processing unit attached to a system's main memory. Instead of moving data into registers prior to computation, load instructions specify operand locations in main memory. Memory access and near-memory computation are deferred until the execution unit requires the operands. To evaluate the feasibility of the proposed architecture, a model of the unit is designed, implemented, and validated in the gem5 architectural simulator. This model serves as a first step to prove the concept and enables design-space exploration of the architecture. As a preliminary evaluation, a quantized convolutional neural network workload is executed on the simulator to assess the potential performance benefits of the approach, achieving a 47x speed-up with respect to a simulated processor baseline.

The development of our tightly coupled SIMD/Vector accelerator for matrix operations requires extending the RISC-V instruction set. Special compiler support is required for this extension. Our methodology starts from a Sail description of the ISA extension and generates the compiler target description data. The instructions are described in Sail and are tested in the generated simulator. The compiler is generated from the description model and is tested with the accelerator implemented in hardware. The experimental results suggest that for matrix multiplication we obtained speed-ups up to 1413x compared to an ARM A72 core.

With the proliferation of data-hungry accelerators and co-processors in embedded system design, co-design of processors and memory systems is becoming more important. Current simulation techniques for processors rely on oversimplified and inflexible memory models, while techniques for memory system simulation tend to only utilize simple processor models. In this work, we integrate a cycle-accurate Verilator processor and vector co-processor model with the Gem5 memory simulator in order to evaluate the full impact of a data-hungry co-processor on the memory system and main core performance, and to provide a framework for future co-design of both processor and memory systems.

Sparse tensor operations are critical for scientific computing but their irregular memory access patterns challenge traditional architectures. While domain-specific architectures offer efficiency, integration into mature SoCs often requires ISA modifications or complex driver development. This work addresses these challenges via a decoupled SpMV access unit integrated through Cohort, a coherent shared-memory queue interface communicating with a CVA6 RISC-V core. To mitigate the inter-tile communication overhead, we introduce a hybrid tiling approach that co-locates the access unit and the core in the same tile, enabling direct data delivery into the private cache. This hybrid architecture achieves significant performance gains, yielding geometric mean speedups of 1.33× and 1.50× for COO and CSR formats, respectively, over traditional multi-tile configurations. These results demonstrate that offloading memory traversal to a programmable data-flow engine, combined with optimized placement in the memory hierarchy, efficiently accelerates irregular workloads with minimal intrusion.

This work presents X-HEEP, an open-source RISC-V System-on-Chip (SoC) platform designed to lower the barrier to chip design for research and education, providing a configurable and extensible infrastructure that enables rapid development of custom RISC-V-based SoCs and hardware accelerators. The platform demonstrates how open ecosystems can accelerate silicon innovation and enable new academic chip design activities. In addition, X-HEEP illustrates how open hardware fosters collaboration between universities and industry, strengthens education in VLSI design, and contributes to broader European initiatives to advance semiconductor capabilities and technological sovereignty.

The Fast Fourier Transform (FFT) is a fundamental algorithm in embedded and edge signal processing applications, including audio and speech processing, radar systems, and biomedical sensing, where real-time performance must be achieved under strict area and power constraints. Conventional approaches typically rely on dedicated standalone accelerators, but these often impose significant area and power overheads that are impractical for resource-constrained embedded and edge platforms. To address this, tightly-coupled acceleration within the CPU pipeline offers a more efficient alternative by delivering substantial performance gains without requiring an independent hardware block. This paper presents APEX, a tightly-coupled coprocessor integrated with the CV32A6 32-bit RISC-V processor, designed to provide high-performance FFT acceleration for embedded RISC-V systems. For a fixed-point FFT of size N=512, APEX achieves an 83.5% reduction in execution cycles and an 87.9% reduction in instruction count compared to the software FFT implementation on the baseline CV32A6, while preserving the baseline operating frequency and full RV32IM_Zicsr software compatibility with only minimal area overhead. These results demonstrate that APEX is an efficient and practical solution for accelerating FFT-intensive workloads in embedded and edge deployments built on open RISC-V architectures.

Our contribution demonstrates how developers can easily run neural networks on RISC-V processors using our custom hardware accelerator TetraEdge.
We present a complete solution combining three components.

First, we introduce TetraEdge, a custom hardware SIMD accelerator.
TetraEdge contains a four-stage pipeline design to accelerate 8-bit quantized CNNs inference on 32-bit RISC-V processors.
In comparison to other hardware accelerators, TetraEdge features an innovative automatic data reordering and min/max accumulation.

Second, we extend the NeoRV32 open-source RISC-V processor,
by two custom instructions to control TetraEdge without blocking the main processor.
The CPU continues other tasks while the accelerator handles neural network operations.
By directly interfacing with the CPU core's register file, TetraEdge minimizes area
and control complexity, enabling seamless integration into existing toolchains.

Finally, we combine both aforementioned contributions to the open-source framework AIfES (Artificial Intelligence for Embedded Systems).
AIfES is specifically designed to train and run neural networks directly on resource-constrained devices.
Its modular software architecture enables the integration of user-specific hardware accelerators, such as TetraEdge.
AIfES reduces software overhead significantly with up to 54\% less memory usage and faster execution for CNNs.

This poster introduces the Bicameral+, an enhanced version of the Bicameral Cache; a vector-aware memory hierarchy that separates vector and scalar accesses into two cache partitions tailored to the needs of each kind of access, improving spatial locality for vectors and eliminating scalar interference. The new design aims to reduce implementation complexity and improve energy efficiency, while retaining the performance improvements of the original proposal, by introducing a set associative design and an alternative opportunistic dirty block management scheme. Experimental results on thirteen benchmarks across various configurations show a 7x area reduction and 18x energy savings, while retaining an average 1.59x speedup w.r.t a conventional cache.

The development of RISC-V technology faces challenges such as the existence of low-quality online courses, fragmented content, a lack of hierarchical and systematic course series, insufficient online experimental practice environments, and limited channels for learning Q&A. The paper sets out to develop a standardized model for assessing the quality of RISC-V courses. In addition, it puts forward a reconstruction method based on course classification tags, organized the individual video into a structured course series. The solution integrates a online RISC-V lab with offline community activities, thereby establishing an integrated online-offline practical teaching environment. This project has produced over 1,000 original RISC-V lecture videos, with total views exceeding 1.3 million. The experimental results demonstrate that the systematically organized course collections generated by this method significantly improve viewership and user engagement, providing a systematic solution for the development of the RISC-V education ecosystem.

The increasing computational demands characteristic of contemporary deep learning models, particularly those associated with computer vision tasks employing Vision Transformers, present considerable constraints for energy-limited smart devices and edge computing platforms. To address this challenge, we demonstrate a RISC-V SoC that incorporates ARCANE, a 512KiB compute-capable Last-Level Cache, which enables In-Cache Computing (ICC). This capability is crucial for substantially mitigating the energy and latency overheads linked to data movement between the central processing unit (CPU) and main memory—a primary architectural bottleneck. To validate the system's operational maturity, we deploy models such as the 22-million parameter DINOv2-S and the lightweight MobileNetV2 utilizing the TVM framework. This deployment serves to demonstrate the platform's capacity to efficiently execute both state-of-the-art, computationally intensive computer vision workloads and standard image classification tasks within a unified environment. The system, instantiated on a ZCU104 FPGA featuring 1GiB of DDR4 memory, operates at a clock frequency of 80MHz and furnishes a Linux operating environment complete with a dedicated suite of user applications. These applications provide quantitative evidence of the significant performance advantages conferred by ARCANE's near-memory computing paradigm when compared against CPU-only execution. By integrating a custom tensor ISA that remains transparent and lock-less to the application programmer, ARCANE establishes itself as a valuable and pioneering contribution to the RISC-V ecosystem, representing one of the first In-Cache Computing IP cores integrated into a Linux operating environment.

The “One Student One Chip” (OSOC) initiative was launched by the University of Chinese Academy of Sciences in 2019. The initiative guides students through designing a RISC-V processor chip from scratch, including tape-out, developing a simple operating system, running it on the chip, running the real game Legend of Sword and Fairy, and completing the physical design process using open-source EDA tools. This enables students to understand the entire processor chip design process. As of February 2026, OSOC enrollments have surpassed 17,000, representing participants from more than 1,200 universities worldwide. This report introduces the implementation of the “One Student One Chip” initiative and the outcomes of open-source chip talent cultivation.

Matrix workloads, essential in generative AI, increasingly rely on ISA-level (i.e. AMX, SME). The attached matrix extension (AME) is one of the three (IME, AME, VME) ISA extensions under standardization in RISC-V. In common, all these matrix-ISA assumes extensions of the processor datapath with dedicated matrix acceleration hardware. However, executing matrix kernels requires moving large tiles between memory and processor registers, making performance limited by memory bandwidth.
We investigate whether High Bandwidth Memory with Processing-in-Memory (HBM--PIM) can serve as alternative implementation of AME instructions. We propose a PIM Execution Primitive (PEP) computational model mapping AME ISA onto Samsung Aquabolt-XL HBM-PIM microkernels, using an outer-product dataflow to enable in-memory accumulation, as well as remapping AME tile registers into memory regions—making possible to chain AME instructions without leaving the memory.
Our experiments show AME tile multiplication reaching 14.9 GFLOP/s (59.4 FLOP/cycle) on a HBM--PIM pseudo-channel, demonstrating that HBM--PIM can serve as an implementation of RISC-V matrix extensions.

The RISC-V ecosystem is moving toward increasingly heterogeneous SoCs that combine multicore processors, hardware accelerators, and software programmability. In this work, we integrate the application-class CORE-V CVA6 processor into the open-source ESP framework, enabling ISA extensions within a coherent multicore platform.
The integration preserves cache coherence, SMP correctness, and Linux-class software support, while providing a practical path to deploying custom instructions in ESP-based systems. To demonstrate the benefits of heterogeneity at the core level, we implement an FFT butterfly extension using a CV-X-IF-based flow with three custom instructions. Across FFT sizes from 16 to 1024 points, the proposed design achieves speedups of 1.37× to 1.45×.
These improvements are obtained with low hardware overhead, namely +0.23% at the platform level and +5% at the core level. Results show that ISA-level extensions can complement multi-accelerator architectures by providing efficient fine-grained acceleration for recurring DSP kernels.

This paper presents a standards-aligned microarchitectural extension that leverages architecturally reserved RISC-V HINT encodings to enable lightweight Very Long Instruction Word (VLIW) execution while preserving full backward binary compatibility. Unlike conventional superscalar designs that rely on dynamic scheduling, speculative issue, and complex hazard detection, our approach encodes static scheduling decisions in HINT instructions that execute as NOPs on unmodified cores. Modified implementations interpret these hints to form statically scheduled issue bundles, achieving higher Instruction-Level Parallelism (ILP) without increasing ISA surface area or compromising compliance.

We validate the proposal through a full-stack methodology spanning ISA modeling, RTL implementation, and FPGA deployment. ISA semantics were prototyped using Google’s MPACT simulator to evaluate bundle formation and decode behavior. We then extended the OpenHW Group CVW (Wally) core to support 4-wide integer VLIW execution via a widened multi-ported register file and parallel datapaths. The design was verified in Questa and Verilator and synthesized for FPGA-based cycle-accurate measurement.

Evaluation on representative DSP kernels (FFT, FIR, IIR, and dot product) demonstrates substantial IPC and cycle-count improvements relative to scalar RV32I execution, while maintaining binary compatibility and toolchain transparency. The proposed mechanism provides a path for energy-efficient ILP extraction in embedded and domain-specific systems, illustrating how reserved ISA space can be systematically exploited to deliver microarchitectural innovation without ecosystem fragmentation.

Language models are becoming increasingly common, and their number of parameters is continuously increasing, imposing huge memory capacities. One of the most common techniques to reduce their memory footprint is weight quantization. Ternary models are one of the most extreme cases of quantization. So far, most hardware proposals focus on FPGA-based accelerators to optimize inference in quantized models, while current general-purpose processors have limited support (up to 8-bit integers). In this work we attempt a preliminary analysis of the potential benefits of moving the quantization hardware support directly to the processor. To do so, we make use of a state-of-the-art inference framework for CPUs and Small Language Models, evaluating what the competitive advantages of having dedicated SIMD hardware for quantized operations. The results show a speedup x2 (tokens/s) on a 350MB Small Language Model with a tendency to increase the speedup with the model size, using a minimal increase of the hardware resources (1.25% in LUTs).

The transputer is a famous High Performance Computing (HPC) architecture from the late 1980s/early 1990s, with Inmos being arguably the most famous example. Embodying a communication-centric, distributed-memory MIMD architecture designed explicitly for scalable parallel process networks, there are numerous potential efficiency advantages to this approach. In a world where scientific programmers are ever demanding more performance, but having to balance this with energy efficiency, this approach is worth another look. The Esperanto ET-SoC-1 was a 1,088-core RISC-V manycore accelerator organised around a mesh network-on-chip (NoC) with hierarchical cache and scratchpad memory structures. Purchased and released by the AI foundry who are focussed on open source, they are emphasising the transputer credentials of the architecture. In this abstract and associated poster we provide and independent exploration around how parallel code written for a T800 transputer array may be systematically mirrored onto the ET-SoC-1 compute fabric. We identify architectural similarities and highlight key divergences.

The European AI Factory initiative aims to distribute sovereign compute capacity across Europe, but participation from Western Balkans accession countries has remained largely aspirational. Albania is charting a different course.
Albania's ICT sector employs tens of thousands of skilled engineers, but almost entirely in software outsourcing—writing code for other countries' products on other countries' architectures. This model creates employment but not ownership, capability but not sovereignty. The age of AI demands transformation: from consuming compute to shaping it.
This talk presents a strategy to establish one of Europe's first RISC-V-native AI compute facilities. The initiative is designed not only to serve Albania's public-sector AI needs but to act as a regional compute hub for the Western Balkans and a gateway for Middle Eastern partners seeking EU-aligned AI infrastructure.
Critically, the strategy begins in the classroom. By embedding RISC-V into Albanian computer science and engineering education, the initiative connects that talent pipeline directly to a sovereign AI compute facility, transforming a generation of outsourcing engineers into architects of AI infrastructure.
Kushtrim Shala draws on Albania's track record in digital innovation to show how small, agile countries can move faster than larger member states in adopting open ISA infrastructure. The talk addresses what it takes to bootstrap a semiconductor culture and makes the case that RISC-V is not merely a technical choice but a strategic instrument of digital sovereignty—one that smaller nations can leverage to build resilient, independent AI capacity.

RISC-V's Zvvm matrix extension stores all tile state in the standard V register file and derives tile geometry algebraically from VLEN, SEW, and a new aspect-ratio field λ. This yields arithmetic intensity that scales with VLEN: a binary compiled at VLEN=256 delivers higher throughput at VLEN=65536 with no recompilation. The same partial-VL mechanism that enables one-column-at-a-time embedded streaming also drives full HPC bulk tiling, while microscaling is integrated via vm-bit opcode aliasing with no new architectural state.

Tile dimensions are not programmer-specified constants — they are consequences of existing parameters. The tile is always square: M = N = VLEN/(SEW×λ), with inner dimension K_eff = λ×W×LMUL. Arithmetic intensity (M/2) grows proportionally with VLEN, and the ratio of intensity to cache-to-VRF bandwidth remains constant — a provable algebraic identity with no equivalent in Arm SME or Intel AMX.

Zvvm's geometry knobs form an intent vocabulary expressed from both sides: software selects LMUL and VL to control K_eff depth and streaming granularity; hardware determines λ and VLEN to shape the tile for its datapath. Setting VL = K_eff with LMUL = 1 gives portable streaming; increasing LMUL or computing multiple C panels trades register pressure for compute intensity — all via the same opcode.

Microscaling (MX) support is integrated by aliasing the vm bit in FP multiply-accumulate opcodes, introducing no new encoding space, registers, or modes.

Modern data-centric workloads increasingly expose the limitations of traditional von Neumann architectures, where excessive data movement limits throughput and energy efficiency.
While hardware accelerators improve performance, they often lack flexibility and still require costly memory transfers.
Existing compute in- and near-memory solutions reduce the memory bottleneck but introduce usability challenges related to constraints on data placement.
ARCANE is a cache architecture that doubles as a tightly-coupled near-memory coprocessor.
The embedded RISC-V cache controller executes custom instructions offloaded by the host CPU relying on near-memory vector processing units within the cache memory subsystem. This architecture hides memory synchronization and data mapping from application software, while offering software-based Instruction Set Architecture extensibility.
Evaluations demonstrate up to an 84x speedup on 8-bit convolution layers over a traditional system-on-chip, incurring only a 41.3\% area overhead.

We implemented an N-body astrophysical simulation code and offloaded its most computationally intensive kernel to Tenstorrent RISC-V–based accelerators using the TT-Metalium programming interface. Performance was assessed on the Wormhole n300 card in terms of execution time and energy consumption, and compared with both an optimized CPU implementation and a CUDA version. The TT-Metalium implementation achieves a speedup of 2× over the CPU baseline, although its performance still slightly lags behind the CUDA implementation. Finally, we investigated strategies for scaling the application across multiple Tenstorrent accelerators, evaluating configurations with up to four devices.

The emergence of RISC-V as an open and extensible instruction set architecture has enabled the development of domain-specific accelerators and General-Purpose Graphics Processing Units (GPGPUs). While the RISC-V ISA provides support for scalar instructions and the RISC-V Vector Extension (RVV) enables data-parallel vector execution, these models do not directly support the Single-Instruction Multiple-Thread (SIMT) execution paradigm required by modern GPU architectures. Consequently, efficient software enablement for RISC-V–based GPUs requires compiler support capable of generating SIMT-oriented instruction sequences and managing massively parallel execution. This proposal talks about CHAKRA-GP, a hardware-optimized compiler framework for a custom RISC-V–based GPGPU architecture. Built upon LLVM and MLIR infrastructures, CHAKRA-GP provides a scalable compilation pipeline enabling efficient kernel generation, memory optimization, and parallel execution mapping for massively parallel workloads. The compiler targets a custom RISC-V GPGPU platform and enables efficient execution of HPC, scientific computing, and AI workloads. The work demonstrates how an extensible compiler infrastructure can bridge the gap between the RISC-V ISA and SIMT-based GPU execution models, enabling efficient compilation for a custom RISC-V GPGPU architecture.

Combining signal processing and artificial intelligence applications is actually a demanding task as these areas require different hardware support during program execution. Specifically, if the demands on rea-time as well as fast execution are high, any feasible solution will use different processing platforms, e.g. DSPs for signal processing and GPU for AI. This results in higher costs, less reliability and high demands on memory transfer rates not to talk about different development tool chains, This paper introduces the UB410 architecture based on RISC-V with enhancements to support different application classes like digital signal processing and artificial intelligence.

The development of our tightly coupled SIMD/Vector accelerator for matrix operations requires extending the RISC-V instruction set. Special compiler support is required for this extension. Our methodology starts from a Sail description of the ISA extension and generates the compiler target description data.

The accelerator main features are: 32 software defined 2D registers, dedicated hardware for matrix operations and a dedicated memory interface. The accelerator employs the CoreV-eXtension-Interface (CV-X-IF) and could be connected to multiple RISC–V cores that feature this interface.

The custom instructions extend the RISC–V ISA and follow their encoding. The custom instructions are of three types: to define matrix registers, matrix operations and memory operations.

The instructions are described in Sail and are tested in the generated simulator. adl_tool transforms the Sail architecture description into compiler model artifacts needed to build a functional prototype compiler for the given specification. Additionally, provides automatically generated tests to validate the correctness of the instruction encodings.

The compiler was generated from the description model and tested with the accelerator implemented in hardware. The experimental results suggest that for matrix multiplication we obtained speed-ups up to 1413x compared to an ARM A72 core.

Data integrity and fault tolerance are prerequisites for RISC-V adoption in enterprise server environments, relying heavily on Cyclic Redundancy Check (CRC) and Erasure Coding (EC) for storage reliability and network transmission. Currently, the RISC-V ISA lacks the dedicated hardware acceleration found in mature architectures such as x86, leading to significant overhead in implementations. We propose novel ISA extensions to bridge this gap: a fused carry-less multiply-add instruction for CRC folding achieving up to 4x - 8x speedup, and a specialized GF(2^8) multiply-accumulate instruction for EC delivering 4x throughput gains over vectorized baselines. Evaluation confirms that these extensions significantly enhance data path efficiency, positioning RISC-V as a competitive architecture for reliable, high-performance storage and networking systems.

The RISC-V ecosystem is evolving toward AI-oriented computing, with matrix-oriented proposal directions such as AME, VME, and IME attracting increasing attention. In LLM inference, matrix multiplication constitutes one of the dominant computation patterns, and quantized matrix multiplication is widely adopted by many accelerators to improve efficiency. In this setting, the practical value of matrix-oriented proposals depends not only on the instruction capabilities they provide, but also on how effectively representative operators can be mapped onto realistic execution flows. This work presents an operator-level profiling study of a currently discussed AME proposal for RISC-V AI. We first design representative matrix operators for quantized LLM-style workloads, then develop a gem5-based platform with support for the AME proposal, and profile matrix multiplication on this platform. Based on these observations, we further analyze scaled matrix multiplication as an extended operator flow and discuss a possible scaled matrix multiplication instruction strategy as a future optimization direction.

UnifiedDB is a machine‑readable encoding of the RISC‑V specification that enables automated generation of documentation, simulators, toolchain support, and certification tooling. We summarize recent accomplishments, including adoption within RISC‑V certification workflows, its role as the authoritative store for architectural parameters, and its maturation into stable, shared specification infrastructure backed by robust continuous integration and validation capabilities. In addition to summarizing technical stabilization and growing community use, the talk outlines a forward‑looking roadmap centered on lowering contribution barriers through new interaction models, including AI‑assisted specification development, while preserving architectural rigor.

The increasing computational demands of modern AI workloads necessitate a holistic architectural approach to AI acceleration on RISC-V processors. This talk presents the XuanTie Tensor Processing Engine (TPE), a RISC-V-based Attached Matrix Extension (AME) engine designed to address AI acceleration across three dimensions: ISA, microarchitecture, and software ecosystem.
At the ISA level, the TPE adopts the in-progress RISC-V AME specification, featuring dedicated tensor registers and a comprehensive instruction set encompassing matrix multiply-accumulate, element-wise, special function, reduction, and load/store operations with broad data type support including INT4, FP8, FP16, and micro-scaling formats.
At the microarchitecture level, the design incorporates a matrix engine achieving 2 TOPS/GHz at INT8/FP8, a concurrent vector engine with hardware-accelerated non-linear functions, and a layered memory subsystem featuring a coherent tensor cache and data prefetch engine.
A full-stack software ecosystem spanning LLVM toolchain to graph execution runtime completes the solution.
Experimental results on the XuanTie C930 cluster demonstrate 99% FP16 GEMM utilization. We discuss key design trade-offs and implications for the evolving RISC-V AME standard.

The RISC-V Unified Database (UDB) serves as a machine-readable “source of truth” for written RISC-V specifications. To improve the ease of creating these specifications, Qualcomm collaborated with a team of Harvey Mudd College students to develop an Integrated Development Environment (IDE) toolkit that can support architects for RISC-V specifications. The team has worked to develop many of the features one would consider standard for developing in a programming language in a modern IDE, including syntax highlighting, autocompletion, and cross-referencing. The groundwork for this IDE also lays the foundation for other tool developers for the RISC-V ecosystem to use information contained in the UDB more efficiently.

The Discrete Cosine Transform (DCT) is a key component in image and video compression systems due to its high energy compaction and efficient implementation. This paper presents a hardware accelerator for the 2-D DCT integrated into RISC-V–based FPGA systems. The design relies on an optimized 8-point 1-D DCT algorithm requiring only 11 multiplications and 29 additions, extended to 2-D using row–column decomposition. The accelerator employs a three-stage pipeline performing row-wise transform, column-wise transform, and quantization. It was integrated with both MicroBlaze V and CVA6 RISC-V cores and implemented on AMD VCU128 and KCU116 FPGA development boards. Experimental results for multiple image resolutions show significant performance improvements compared with the software implementation, achieving speedups of up to 44.56× and a throughput of 2 Mpixel/s at 100 MHz. The accelerator uses modest FPGA resources, enabling multiple instances and demonstrating its suitability for accelerating image and video compression pipelines in RISC-V–based systems.

As RISC-V "Vector" (RVV 1.0) architectures scale, the Vector Register File (VRF) becomes a primary bottleneck in area and power. This work characterizes data residency and redundancy patterns in a distributed, long-vector VRF using the gem5 simulator. We identify two primary inefficiencies: resource fragmentation and an entropy-capacity mismatch in active data. Our evaluation of lightweight compression schemes reveals that a 2-entry dictionary-based approach consistently yields a 2.5x compression ratio of the computed vector elements. These results demonstrate that hardware-level data compaction is an interesting path for optimizing the area of future long-vector RISC-V accelerators

This paper tells the incremental journey of taking Tenstorrent’s Ascalon RISC‑V CPU IP from RTL and emulation to a playable DOOM demo on a Synopsys’s prototyping platform. Along the way we describe the problems we overcame, and how we optimized our flows and the design. We close with a set of lessons and recommendations for teams who want to use emulation and prototyping and realistic workloads like DOOM to de‑risk RISC‑V IP adoption and accelerate hardware/software co‑design.

We show how a processor with native extended floating point precision could be incorporated in algebraic subroutines in convex optimisation, namely in indirect matrix inversion methods like Conjugate Gradient, which are used in Interior Point Methods in the case of very large problem sizes. Also, an estimate is provided of the expected acceleration of the time to solution for a hardware running natively on extended precision. Specifically, when using indirect matrix inversion methods like Conjugate Gradient, which have lower complexity than direct methods and are therefore used in very large problems, we see that increasing the internal working precision reduces the time to solution by a factor that increases with the system size.

This work proposes an open-source framework that leverages both the Zfh (scalar float16) and the Zvfh (vector float16) extensions to enable complete on-device training on resource-constrained RISC-V single-core. On top of reducing the memory footprint by about 50% as compared to using float32, our approach facilitates transfer learning and fine-tuning scenarios by incorporating layer-freezing capabilities. Our work builds onto AIfES an open-source, modular and generic DNN training and inference framework for embedded systems that can be extended with custom hardware-specific functions.

Communication baseband workloads such as covariance estimation, synchronization and reduction operations exhibit substantial data-level parallelism. The RISC-V Vector Extension (RVV) introduces vector-length agnostic (VLA) execution, enabling scalable vector implementations independent of a fixed hardware width. In this work, we explore architectural scalability trade-offs of a configurable RVV-based vector processor across VLEN, lane count, and lane width. Using representative communication kernels and synthesis with the predictive ASAP7 PDK, we analyze architectural scaling behavior and the interaction between cycle reduction and frequency degradation. While increasing VLEN reduces cycle counts, critical-path growth and bandwidth imbalance introduce a parallelism–frequency trade-off that yields kernel-dependent optimal configurations. We further demonstrate how a lightweight custom vector complex multiplication instruction improves efficiency for covariance-based workloads. The results highlight the importance of balanced compute–memory design for practical and physically realizable RVV implementations.

This paper presents a compact FPGA-based controller for Reconfigurable Intelligent Surfaces (RIS) that integrates an embedded RISC-V processor and dedicated hardware control within a single device. The proposed architecture targets a 15×15 mechanical RIS prototype driven by stepper motor actuators. The embedded RISC-V processor accesses the RIS controller through a lightweight memory-mapped interface, enabling software-programmable RIS reconfiguration while fully abstracting low-level actuation details. By integrating processing and control within the same FPGA, the proposed platform eliminates the need for external computing units and reduces communication latency.

The RISC-V Unified Database (UDB) serves as a machine-readable “source of truth” for written RISC-V specifications. To improve the ease of creating these specifications, Qualcomm collaborated with a team of Harvey Mudd College students to develop an Integrated Development Environment (IDE) toolkit that can support architects for RISC-V specifications. The team has worked to develop many of the features one would consider standard for developing in a programming language in a modern IDE, including syntax highlighting, autocompletion, and cross-referencing. The groundwork for this IDE also lays the foundation for other tool developers for the RISC-V ecosystem to use information contained in the UDB more efficiently.

This work enables optimized, end-to-end inference of the object detection models on RISC-V vector CPU. It includes the implementation of optimized pre- and post-processing pipelines as well as the enablement of efficient execution of the models at FP32, FP16, and INT8 precisions. IREE, an MLIR-based compiler, is used to compile and optimize the model. Model inference on the Banana Pi BPI-F3 is profiled to identify top hotspot ops and their compilation is optimized in the IREE compilation pipeline either by improving vectorization or by implementing ukernels. For accuracy validation, the mean Average Precision (mAP) is computed using the COCO validation dataset. This project is supported by the RISC-V Software Ecosystem (RISE), and all the developed artifacts are open-source.

We present an end-to-end framework for the automatic generation of custom RISC-V instruction-subset processors (RISSPs) tailored to machine learning (ML) inference. Building on the RISSP methodology, our fully automated flow accepts model hyperparameters and a target dataset, performs offline training, and generates the complete inference implementation together with all deployment artifacts for the target device. The resulting inference code then drives the RISSP generation, synthesising a custom processor that implements only the RISC-V instructions used by the application. By co-optimizing software and hardware within a tightly integrated co-design toolchain, the combined flow reduces ISA footprint and design complexity, enabling smaller and more energy-efficient processors for ML workloads at the edge.

Spiking Neural Networks (SNNs) offer significant energy efficiency for Edge AI, yet their event-driven nature leads to unpredictable, variable-length output data. In traditional heterogeneous SoCs, this unpredictability causes high CPU overhead and bus inefficiency. This paper presents a specialized Event-Adaptive DMA (EA-DMA) integrated into a RISC-V based SoC. Unlike standard DMAs, the proposed engine performs buffer-triggered, variable-length transfers with maximum-size clamping and hardware backpressure for irregular SNN spike traffic. This work provides a scalable solution for integrating neuromorphic accelerators into the RISC-V ecosystem.

Modern processors implement complex features that require unique verification strategies to exhaustively verify the feature and achieve coverage goals faster. The memory management unit (MMU) within the CVA6, with multiple level of table, page tables, lookaside buffers (TLBs), and physical memory protection (PMP) capabilities, is one such feature. It is highly configurable and complex, making an exhaustive verification a real challenge. It requires smart management of different page table entries (PTEs) and PMP entries, to simulate different types of exceptions, page faults and PMP access errors. This work is done using an Universal Verification Method (UVM) framework provinding an efficient means creating PMPs and PTEs, thus simplifying the verification of MMU.

Hearing loss is among the most prevalent sensory impairments worldwide. Hearing aids that incorporate adaptable, personalized signal processing have the potential to improve communication outcomes and social participation for affected individuals. The development and rigorous evaluation of novel hearing-aid algorithms requires high-level programmable, low-power, and portable behind-the-ear (BTE) research platforms that enable studies in real-world environments. The RISC-V open source instruction set architecture (ISA) presents a flexible and configurable baseline for the development of signal processing architectures.
This paper presents a lightweight single instruction multiple data (SIMD) architecture featuring a complex number extension targeted at embedded applications with a specific focus on the energy efficiency by reusing existing multiplier hardware. Performance data is gathered from a reference Fast Fourier Transform (FFT) implementation, with FFT sizes taken from the field of typical hearing aid applications. Power values are obtained by synthesizing the baseline processor and the extension in a 22 nm FD-SOI technology, followed by a gate-level simulation to obtain accurate switching activity values. The implemented extension achieves a speedup of up to 26 %. A comparison of the energy values through gate-level simulation reveals that the energy consumption of the modified design decreases by 27 % on average.

This work presents a co-optimized architecture for edge-based Transformers, focusing on a specialized RISC-V CPU designed to manage a parallel AI co-processor. While the BumBleBee (BBB) unit handles core Flash Attention Method (FAM) computations, the system relies on an adaptable RISC-V core for critical data orchestration and pre-processing. To overcome the bottlenecks of a memory-bound system, the CPU's ISA is enhanced with custom fused instructions—convcat, lwincr, and swincr—which consolidate complex macro-operations into single-cycle actions. Notably, the convcat instruction reduces 13 F-extension instructions to one, cutting latency by over 50%. Furthermore, the CPU incorporates M and F extensions with data-gating in the ALU to minimize power consumption during scaling and normalization tasks. By prioritizing CPU-level adaptability and instruction fusion, the architecture significantly reduces the energy bill and latency required for high-performance LLM inference in power-constrained environments.

FPGA lifecycle management remains tied to proprietary toolchains and host architectures, leaving RISC-V without a vendor-neutral model for scalable bitstream deployment.
A host-agnostic control-plane architecture is presented that shifts lifecycle management to the operating-system layer by leveraging standard Linux capabilities, thereby decoupling deployment from specific ISAs and vendor stacks. This enables Linux-capable RISC-V processors to serve as control hosts in heterogeneous FPGA systems.
Prototyped on a Zynq-7000 SoC and generalizable to RISC-V platforms, the architecture provides a portable foundation for fleet-scale FPGA management.

Integrating AI onboard satellites to reduce dependence on ground stations and facilitate quick orbital maneuvers demands a new class of onboard computers with enhanced processing power, real-time control capabilities, and robustness against the harsh space environment.
Astral is a fully open-source, highly parametric platform for RISC-V-based heterogeneous SoCs targeting reliable onboard control and AI acceleration for next-generation space computers.

In this work, we present a dedicated IP core optimized for energy-efficient convolution over highly sparse and unstructured input arrays, characteristic of event-based convolutional neural networks. The accelerator was integrated into a RISC-V-enabled system on chip (SoC) and taped out in 65nm TSMC technology to enable full post silicon characterization and to evaluate alternative sparse computation algorithm variants.

This video documents the unboxing and functional verification process of the StarrySky development board by participants of the “One Student One Chip (OSOC)” Program IV, following the successful tape-out and chip delivery. Featuring a fully customized RISC-V processor core independently developed by the trainees, this self-designed board demonstrates remarkable technical achievements through successful execution of classic games like Mario and rendering of the university's emblem. This helped students strengthen capabilities in hardware–software co-design of computer systems, and cultivated their abilities to understand, build, debug, and optimize complex systems. The student in this video, who is called Tao Zhou, is currently a core technical contributor in the XiangShan frontend team, responsible for the development and performance optimization of the ICache and BPU.

The transition toward centralized automotive computing platforms demands scalable, high-performance, and energy-efficient AI acceleration tightly integrated with open instruction set architectures. Within the European Chips Joint Undertaking framework, the [PROJECT NAME] project develops a next-generation automotive hardware platform based on RISC-V technology.
This paper explores three hardware acceleration paradigms applicable to RISC-V-based automotive systems: (i) memory-mapped monolithic accelerators, (ii) custom ISA extensions tightly coupled to the processor pipeline, and (iii) Near-Memory Computing (NMC) architectures. We present an ongoing comparative study evaluating their applicability to representative automotive AI kernels, including conventional neural networks (CNNs, MLPs), data-driven battery models, and emerging Spiking Neural Networks (SNNs).
While all paradigms provide workload-dependent performance benefits, preliminary architectural analysis suggests that Near-Memory Computing offers superior scalability and energy efficiency for memory-bound AI workloads. Complementing the hardware effort, we develop a software ecosystem leveraging MLIR-based compilation flows to efficiently map both conventional and neuromorphic models onto heterogeneous RISC-V accelerators.

AI and HPC workloads demand scalable, efficient accelerator architectures. We present MAGIA-V, an open mesh-of-tiles accelerator template integrating a RISC-V Zve32d Spatz vector processor with a RedMulE tensor engine, enabling concurrent vector and matrix operations.

RISC‑V has emerged as one of the most important new architectures in decades, achieving widespread adoption in embedded systems and shipping at massive scale. But as the industry looks beyond embedded into application processors, a new set of challenges—and opportunities—comes into focus.

This talk explores where RISC‑V stands today, what makes its next phase of growth fundamentally different, and why its future is likely to unfold unevenly across markets. It highlights key inflection points that will shape adoption and outlines where RISC‑V is poised to gain traction next.

The global nature of RISC-V is one of its greatest strengths. The RISC-V Instruction Set Architecture (ISA) is constantly developed and evolved by member organizations worldwide, with contributors working together on new features and capabilities across geographies and time zones. In turn, the RISC-V ISA provides the basis for the future of global computing innovation, addressing the diverse needs of countries, companies, educators and individuals.

In this session we bring together representatives of the RISC-V community from different continents to discuss the nature of a worldwide ecosystem. We will discuss the realities of RISC-V in different geographies:
How the ISA drives innovation and solves specific local problems
How RISC-V unlocks the potential of a global marketplace.
The importance of digital sovereignty, and different approaches to research, education and training a new generation of engineers.
Explore the tension between collaboration and competition.
How are RISC-V members working together and supporting each other? Where does their location give them a competitive edge?
Opportunities and challenges in cross-continent collaboration. Lessons learnt.

Join us to learn the global lessons of RISC-V deployment!

Moderator:
Florian Wolhrab - Open Hardware Foundation

Panelists:
P. Hari - C-DAC
Teresa Cervero - Barcelona Supercomputing Center
Marcelo Zuffo - University of Sao Paulo
Jing Yang - Damo Academy

Addressing ever-larger amounts of memory is a fact of (computerized) life. The authors of the RISC-V unpriviledge specification did recognize that and coined on less than one and a half page what could be a natural extension to 128-bit of the 32- and 64-bit RISC-V ISA. Given this RV128I draft, we (a) defined an ELF128 extension for binaries, (b) made gnu-based a cross-compilation environment able to use RV128I instructions and generate ELF128 binaries, (c) added support for this extension and ELF128 in QEMU, (d) added the necessary instructions and resources in the CVA6 processor.

Computational Fluid Dynamics (CFD) relies heavily on the efficiency of linear solvers based on sparse linear algebra kernels. Widely used frameworks like OpenFOAM exploit parallelism primarily at the domain decomposi-tion level via MPI. Support for vector/SIMD architectures is limited to compiler auto-vectorization. Furthermore, support for such architectures is limited by OpenFOAM’s internal matrix data format, which is intrinsically ill-suited for the contiguous memory accesses required for efficient execution on vector processors. In this work, we focused on two very different RISC-V architectures: the prototype long-vector EPAC accelerator and the commercial short-vector CPU Sophon SG2044. On these platforms, we optimized the Sparse Matrix-Vector multiplication (SpMV) using RISC-V vector intrinsics and integrated it into a custom smoother, performing a runtime conversion of internal data into a vector-friendly format. Experimental results on the EPAC test chip show a 6× speedup for the smoother; benchmarks on Monte Cimone (MCv2) cluster with the Sophon SG2044 processor achieve a 1.5× smoother speedup, proving that legacy CFD codes can be effectively accelerated on both research and commercial emerging hardware.

Llama.cpp is a widely used open-source platform for running Large Language Models (LLMs) on CPUs, but its support for RISC-V remains limited compared to x86 and ARM. Many floating-point and quantized kernels lack RISC-V Vector (RVV) implementations, restricting the performance of existing hardware. This work improves the upstream RISC-V performance by vectorizing core floating-point kernels and extending support across multiple quantization types, enabling first-class support for RVV in Llama.cpp. VLEN-aware data repacking is introduced to accelerate GEMM and GEMV kernels for both floating point and quantization types. The optimized kernels are validated across VLENs up to 1024-bit, with benchmarking on Banana Pi BPI-F3 (256-bit VLEN) demonstrating considerable performance gains over upstream Llama.cpp. This work is supported by the RISC-V Software Ecosystem (RISE), with the vectorized kernels being upstreamed to Llama.cpp along with the test infrastructure.

To address the lack of hardware sovereignty in proprietary console ecosystems, this paper presents a fully open-source RISC-V gaming platform utilizing a VexRiscv core and Lattice ECP5 FPGA. We implemented a custom SoC featuring dedicated 2D GPU and APU accelerators, supported by a complete LLVM-based toolchain and a high-level Game Development Framework API. Validation through a 48-hour game jam demonstrated the platform’s utility, achieving a stable 640 × 480 at 60 FPS output and high power efficiency for independent development.

Some highlights about the current event and closing remarks.