Digital Design Engineer with 3+ years of industry experience in RTL design and verification, specialising in RISC-V CPU architecture, ISA extensions, and hardware accelerators for FPGA and ASIC targets. Passionate about open-source CPU design, computer architecture, and hardware/software co-design. Active contributor to the RISC-V ecosystem, including CVA6, SERV, and RISC-V Architecture Compatibility Test Suites (ACTs).

Abinaya Senthil is a Design Verification Engineer at NXP Semiconductors, Austin, Texas specializing in UVM-based IP verification, System Verilog, CDC verification, and memory injection methodologies for complex IP designs. She is a founder of SiliconDV , a technical education platform for semiconductor verification engineers. She is a member on the IEEE WIE MRP award review committee and has presented CSTIC 2026 ( IEEE Xplore indexed). Her research focus on AI-driven verification optimization and GPU accelerated simulation for RISC-V architectures.

I am a compiler engineer at 10xEngineers, working on enabling the compilation of LLMs and vision models for custom hardware/accelerators using IREE, an MLIR-based AI compiler. I have experience in writing optimized kernels for RISC-V Vector (RVV) and custom hardware, LLVM middle-end and backend development.

Adnan is the President and CTO of Breker and the inventor of its core technology.

He has over 30 years of experience in functional verification automation. Prior to Breker, he managed AMD’s System Logic Division, and also led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor. In addition, Adnan spent several years at Cadence Design Systems and served as the subject matter expert in system-level verification, developing solutions for Texas Instruments, Siemens/Infineon, Motorola/Freescale, and General Motors.

Adnan holds more than 20 patents in test case generation and synthesis. He received BS degrees in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.

Afonso Oliveira is a computer engineer focused on the RISC-V ecosystem, currently working across the SW/HW stack at AiNekko. Previously, he worked at Synopsys on the ARC-V software team. His open-source work involves several upstream Zephyr contributions and the RISC-V Unified Database, where he worked as core developer who helped the project grow from 0 to 1.

Akif has done in BS in Computer Engineering from ITU Lahore, Pakistan. He has 3+ years of experience in the semiconductor industry, specializing in RISC-V software. His work spans multiple OSes, RTOSes, and microkernel RISC-V enablement. Currently working as Systems/Firmware Engineer at 10xEngineers. He recently joined the Eclipse Foundation as a ThreadX RTOS committer. He is also a core member and developer of Cloud-V platform.

Ph.D. researcher in Electrical/Electronic Engineering with strong organizational skills and high motivation. Experienced in hardware/software co-design for embedded systems, including RISC-V SoC integration, custom accelerator interfaces, RTL development (SystemVerilog), FPGA prototyping, and embedded C. Solid background in Post-Quantum Cryptography implementations and optimization, with a performance-driven mindset and enthusiasm for new technical challenges.

Alessandro Nadalini received the B.Sc. and M.Sc. degrees in electronic engineering from the University of Bologna in 2018 and 2021, respectively. He is currently pursuing the Ph.D. degree with the Department of Electrical, Electronic and Information Technologies Engineering (DEI), University of Bologna. His research regards the hardware-software co-design of multi-processors heterogeneous systems on chip. He received the Mukherjee Best Paper Award of the 2023 IEEE Computer Society Annual Symposium on VLSI.

Alexandre de Limas Santana has been working on high-performance code generation at the Barcelona Supercomputing Center for the past five years. During this time, he participated in the European Pilot project as a research engineer, where he focused on accelerating dense linear algebra operations for deep neural networks on long-vector processors. Alexandre’s research interests now also include performance portability, motivated by the hardware diversity of emerging RISC-V vector architectures.

Alexandros Ntyrkai holds a BSc in Computer Science from the Department of Informatics and Telecommunications at the National and Kapodistrian University of Athens. He is currently a research assistant at the Computer Architecture Lab. His research focuses on the security evaluation of RISC-V CPU designs.

Álvaro Moreno is a computer architecture researcher at the Barcelona Supercomputing Center (BSC), where he has been part of the Simulation Infrastructure and Methodologies (SIM) group since 2022. Currently pursuing a PhD in computer architecture at the Universitat Politècnica de Catalunya (UPC), his work focuses on advancing computer architecture simulation and designing efficient, new RISC-V accelerators.

Andrea Gallo is CEO of RISC-V International. Before joining RISC-V as VP of Technology, Gallo worked in leadership roles at Linaro for over a decade as Vice President of Business Development, driving the company’s membership acquisition strategy and previously managing the Linaro Datacenter and Cloud, Home, Mobile, Networking, IoT, and Embedded Segment Groups and underlying open source collaborative projects within the Arm ecosystem. Before Linaro, Gallo was a fellow at STMicroelectronics, where he led the optimization of hardware-software architectures for new smartphone and telecommunication ICs. He also served on the board of directors for CHAOSS, a Linux Foundation project focused on the health of open source communities.

Andrea Helga Bernardi received her master’s degree with honors in Electronic Engineering from the University of Bologna, Italy, in 2024. She is currently enrolled in a PhD program under the supervision of Prof. Simone Benatti at the Energy-Efficient Embedded Systems Laboratory (EEES Lab), DEI Department, University of Bologna. Her research focuses on biosignal processing and the development of real-time human-machine interfaces based on smart glasses.

Andreas Mauderer received the diploma degree in computer science from the University of Karlsruhe, Germany, in 2009. He received his PhD in computer science at the University of Tuebingen in 2014. He is working at Bosch since 2009 in the business unit Mobility Electronics in the field of Virtual Prototyping and on-chip processors for automotive ICs. Furthermore, he is active in various publicly funded projects regarding these topics.

ANDREI STAN (Member, IEEE) received the B.S. degree in computer engineering, the M.Sc. degree in advanced computer architecture, and the Ph.D. degree in computer engineering from the ‘‘Gheorghe Asachi’’ Technical University of Iaşi, Romania, in 2002, 2003, and 2012, respectively. He is currently a Faculty Member in the Department of Computer Engineering and actively contributes to both teaching and research in computer systems and embedded systems. His primary research interests include computer architecture and embedded systems. His work explores modern architectures for domain-specific computing, hardware-software co-design methodologies, and system-level modeling.

Andrew Dellow is a director in the technical standards group at Qualcomm and currently chair of the Security Horizontal Committee at RISC-V International. He is also a RISC-V Ambassador, and Chair of the SoC Infrastructure Horizontal Committee. With over 25 years' experience in system on chip architecture and security, starting with the original development of robust Set Top Box SoCs for Pay TV, he is a former Chief Security Architect at HiSilicon Technologies, Distinguished Engineer and Technical Director at Broadcom Corp., and Security Architect at STMicroelectronics. His passion is driving secure architectures and implementations, holding more than 30 patents around SoC security.

Hardware/Software co-design engineer at imec belgium

Anna Duque Antón received her Dipl.-Ing. degree in Electrical and Computer Engineering from the RPTU University Kaiserslautern-Landau in 2019. She is currently a Ph.D. candidate at the Electronic Design Automation group at the same university, working under supervision of Prof. Kunz and Prof. Stoffel. Her research interests include formal security verification, access control mechanisms and hardware trojan detection. For her work on SoC-wide security verification, she received the Intel Hardware Security Academic Award 2022.

Anne Merlande is a processor architect at STMicroelectronics in Grenoble, within the Computing and Compilers Center. As Senior Member of Technical Staff, her expertise field covers processor and system architecture, CPU microarchitecture and frontend design, low power and energy efficient subsystems, security and functional safety.
She graduated from Institut Supérieur d’Électronique de Paris in 1995 and joined STMicroelectronics in 1999, after four years as an ASIP designer at Matra. At STMicroelectronics, she has led the design of the ST200 processor families, acted as technical lead for ARM Cortex A subsystem frontend design, and led top level integration for automotive SoCs.
She currently works as Processor Architect on the STxP5 core family, with a particular focus on ultra low power operation, security, and functional safety.

Antonio del Vecchio received his PhD in Electronic Engineering from the University of Bologna, where he also obtained his BSc and MSc degrees. His research focuses on power and thermal management for modern computing systems, with particular emphasis on high-performance computing, edge platforms, and RISC-V-based control architectures. During his PhD, he worked on open and scalable power-management subsystems, hardware/software communication interfaces, and thermal-power modeling techniques for many-core and chiplet-based processors. His work combines embedded systems, FPGA-based prototyping, firmware development, and system-level evaluation. His current interests include open RISC-V power controllers and flexible communication substrates for distributed, energy-efficient runtime management.

Antti Nurmi received the B.Sc. degree in electronics and the M.Sc. degree in embedded systems from Tampere University, Tampere, Finland, in 2019 and 2022, respectively, where he is currently working toward the Ph.D. degree in computer engineering at the SoC Hub Research Centre. His research interests include predictable computer architecture, embedded real-time systems, RISC-V, and SoC design.

Arda Öztürk is a Computer Engineering graduate from Marmara University and a contributor to the EU Chips JU RIGOLETTO project. His work focuses on RISC-V systems, runtime telemetry, and performance monitoring for accelerator-aware workloads. At RISC-V Summit Europe 2026, he contributes to a poster on window-level telemetry monitoring for RISC-V systems.

Ashley Stevens is Director of Product Management and Marketing at Arteris responsible for coherent NoCs and die-2-die interconnects. He has over 35 years of industry experience and previously held roles at Arm, SiFive and Acorn Computers. He holds 11 granted patents and has a degree in Computer Engineering from Queen Mary, University of London.

PhD student in machine learning security at CEA-Leti.

I received my Ph.D. from the Embedded Systems Laboratory (ESL) at EPFL, Switzerland, where my research focused on low-power computer architectures for biomedical wearable applications. I am currently a research fellow at CERN, working on integrated circuit designs for the HL-LHC and FCC. My research interests include low-power RISC-V SoC architectures, open-source hardware and EDA tools, and chip design.

Founder & Chairman of Nuclei System Technology.
RISC-V pioneer in China; author of best-selling RISC-V Chinese book. Ex-Marvell/Synopsys CPU design expert (15+ years). Founded Nuclei (at 2018) to deliver full-spectrum RISC-V IP and automated SoC design solutions, empowering global designers with revolutionary technology.

Harvey Mudd College class of 2026 (B.S. in Computer Science)

Dr. Caaliph Andriamisaina is a research engineer at CEA-LIST, in the field of HW design and EDA. He received a Ph.D. degree in computer science and electronic engineering from the University of South Brittany in Lorient, France, in 2008. At CEA-LIST, he has been involved in several R&D projects on HW design, simulation, and AI-assisted power/performance modeling. His current research interests focus on AI-driven methodologies for modeling functional and extra-functional properties to support HW/SW co-design.

Rafael Tordoya is a Research Associate at the Zurich University of Applied Sciences (ZHAW) in the fields of Artificial Intelligence (AI) and Embedded Systems. His research focuses on leveraging AI in resource-constrained environments, with particular emphasis on optimized AI inference, mathematical backends, and leveraging available hardware capabilities to enhance inference performance in embedded systems.

Carsten is Professor for Computer Architecture and Operating Systems at TU Munich's Heilbronn campus.

Carsten is also deputy spokesman of Gesellschaft für Informatik (GI)'s special interest group on "Ethics in Informatics", GI liaison lecturer at TU Munich, and member of the Zuse Society's board of directors.

From 2013 to 2019 he was elected member of GI's board of directors.

His research interests comprise high performance computer architectures, microprocessor architectures, multi- and many-core architectures as well as the adaptation of numerical simulation codes to these architectures, with a focus on RISC-V.

Catalin Ciobanu has a MSc and PhD from Delft University of Technology, The Netherlands. He is currently Associate Professor at Transilvania University of Brasov, Romania and Senior Researcher at the National Institute for Research and Development in Microtechnologies - IMT Bucharest, Romania. His research interests include RISC-V processors, embedded systems, high performance computing, SIMD architectures, digital signal processing and reconfigurable hardware.

He is a researcher at Inria in the TIMA laboratory of the University Grenoble Alpes since November 2024, where he is member of the MADMAX team. He spent previously 9 years at CEA. He’s got his computer sciences and electronics PhD from Université Paris 6 in 2015.
He co-chairs the Interconnect Task Group in the OpenHW Foundation and is a committer of the CVA6 project, where he is the designer and leading maintainer of the HPDcache (L1 Data Cache).
He works on multi-core heterogeneous architectures, cache hierarchy and cache coherence.

Charlie has been a contributor to the Linux kernel for the last 3 years, focusing on bringing RISC-V support to be on-par with x86 and ARM.

Teaching assistant for "One Student One Chip", with main research directions in RISC-V processors and SoC design.

Sr. Staff Performance Engineer, Infrastructure - Tenstorrent

Chloe Jian Ma is a strategic technology executive with more than 20 years of experience in AI, semiconductors, and cloud infrastructure. As Chief Business Officer at Epic Semi, she leads global growth, commercialization, and ecosystem initiatives that enable chipmakers and system innovators through agile semiconductor solutions. Prior to Epic Semi, Chloe led Edge AI and Robotics go-to-market strategy at Arm, driving strong revenue growth and expanding AI adoption across sectors including smart vision, robotics, and industrial IoT. She has also held leadership positions at SiFive, Intel, Mellanox, Juniper Networks, and Cisco Systems, where she helped build high-growth product businesses and strategic partnerships with leading cloud and AI providers. Chloe holds an MBA from the Wharton School and an MSEE from the University of Southern California. She is widely recognized for her industry leadership and commitment to advancing innovation across the global AI and semiconductor ecosystem.

Christian Siemers has studied Physics and Mathematics and has received his PhD from Kiel University in 1984. After some years at Kiel University and in Industry, he received his appointment as professor first at University of Applied Sciences Stralsund, later in Heide/Holstein and Nordhausen. Since 2006 he was with the Clausthal University of Technology, first part-time since 2016 full-time. His regions of interest are programmable architectures amd their programming interface. He has over 200 publications and holds more than 20 patents.

Christian Wenzel-Benner completed a dual engineering degree at the former DaimlerChrysler AG / University of Cooperative Education in Stuttgart. After several years of ECU development at Bosch, he took on tasks as project manager and later as a specialist for embedded systems & security at ITK Engineering.
During this time, he earned a Master of Science at Brunel University West London and led an embedded systems benchmarking team for the international NIST SHA-3 standardization competition.
Since the end of 2015, he has been responsible for customer-specific solutions and training at GLIWA and works as a part time university lecturer.

With 20 years of experience in Electronic Design Automation (EDA), I began my journey with a PhD in microelectronics from Sorbonne University. In 2009, I co-founded Flexras Technologies, a startup specializing in FPGA prototyping tools, which was acquired by Mentor Graphics (now Siemens EDA) in 2015. There, I served as Chief Software Architect, leading global R&D teams and helping evolve our technology into a widely adopted product.In 2022, I co-founded a new venture: keplertech.io, an EDA startup built on the belief that Open Source can unlock innovation in one of the most closed and complex industries: integrated circuits and the tools used to design them. In a space dominated by a handful of major players, we aim to create meaningful opportunities for smaller, agile actors to thrive. I’m passionate about building complex systems from scratch and bringing ideas to life in the real world.

Christoph Hazott received his M.Sc. degree in Embedded Systems Design from the University of Applied Sciences Hagenberg, Austria, in 2012. After completing his master’s studies, he joined Infineon Technologies AG, where he worked in the Test Engineering Department. In 2021, he became a PhD student at the Institute for Complex Systems, Johannes Kepler University Linz, Austria, and received his PhD in Computer Science in 2025. He has published several papers in international conferences and journals, including ASP-DAC, ETS, DDECS, FDL, and Integration, the VLSI Journal. Since October 2025, he has been with MINRES Technologies. His current research interests include RISC-V, SystemC/TLM-based virtual prototyping, and the testing and analysis of embedded HW/SW systems.

Cosmin-Andrei Popovici received his B.S. degree in Computer Engineering and Information Technology in 2020 and his M. Sc. degree in Embedded Computers in 2022, both from the Faculty of Automatic Control and Computer Engineering of the "Gheorghe Asachi" Technical University of Iași, România. He is currently pursuing a Ph.D. degree in Computer Engineering from the same university. His research interest focuses on Digital Design, Computer Architecture, especially hardware accelerators and extensions for RISC-V cores, and Embedded Systems. As a graduate teaching assistant and faculty member in the Department of Computer Engineering, he teaches laboratory sessions for the courses of Introduction in Programming (C Language), Data Structures, Computer Architecture, Computer Networks, Systems with Microprocessors and Multiprocessor Systems.

Prof. Dr.-Ing. Daniel Klünder is a Professor of Electrical Engineering at the Baden-Wuerttemberg Cooperative State University (DHBW) Stuttgart. Before joining academia, he gathered extensive industry and leadership experience in the automotive and software sectors, focusing on embedded software and vehicle electronics in senior roles at ETAS, FEV, and Daimler. He holds a PhD in embedded software design from RWTH Aachen University.

His current work operates at the intersection of hardware architecture and strategic system design, with a strong focus on Next-Gen Edge-AI for autonomous systems in defense and critical infrastructure. He specializes in overcoming strict SWaP-C (Size, Weight, Power, and Cost) constraints through energy-efficient "Zero-Overhead" architectures.

Embedded systems engineer specializing in embedded AI deployment and optimization. My work focuses on adapting machine learning models to resource-constrained hardware and improving performance through efficient compilation and system-level optimization

Dave Cremins is a Principal Cloud Software Engineer at OPENCHIP, where he specializes in designing and building advanced cloud‑native systems at scale. With deep expertise in distributed architectures, automation, and infrastructure engineering, Dave plays a key role in shaping technical strategy and delivering high‑impact engineering solutions across the organization.

David Aledo is an Assistant Professor at Universidad de Cantabria, Spain. He has a PhD on Electrical and Electronic Engineering, and was a PostDoc Researcher at the TU Deflt, Netherlands. His research lines are around hardware accelerators for machine learning, HLS (High-Level Synthesis), FPGAs, and system-level simulations.

David is a software engineer and system architect working in correctness - and latency-critical systems. His background spans academic research in parallel computing, low-level programming in RISC-V and MIPS assembly and embedded C and Rust, and active involvement in both the Rust and RISC-V communities as a speaker and mentor. He is a member of the Safety Critical Rust Consortium.

David Guerrero Martos received his Bsc degree and the PhD degree in Computer Engineering from the University of Seville, Spain, in 2000 and 2012, respectively. Since 2002, he has been working as a lecturer in the Department of Electronics Technology of said university. His research interests include digital circuit synchronization, hardware implementation of numerical methods and computer architecture. He has published several papers in journals and conferences.

Diego Gigena Ivanovich is a Scientist at Silicon Austria Labs (SAL), where he conducts research on microelectronics for embedded artificial intelligence. His work focuses on the design and optimization of hardware accelerators for AI applications in embedded systems. He holds a Ph.D. in Electrical Engineering from the National University of the South (Argentina).

Dr. Erich Focht is a system architect and physicist currently working as a Senior Fellow at Openchip, where he leads the Accelerator-AI architecture group and focuses on the development of Artificial Intelligence (AI) and High-Performance Computing (HPC) accelerators. He holds a Ph.D. in theoretical physics from RWTH Aachen and has a professional background that spans computational physics, numeric algorithms, distributed systems software, parallel file systems and hardware-software co-design.
Before his current role at Openchip, Erich spent over 25 years at NEC HPC Europe where he contributed to the system design of dozens of supercomputers, most of them present in the TOP500 list.
Within the RISC-V open-source ecosystem, Dr. Focht contributes to the standardization of matrix operations as an active member of the IME TG, focusing on RISC-V matrix implementations. He also represents Openchip in the RVI Technical Steering Committee.

Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL GmbH, providing strategic R&D for semiconductor companies. He chairs the RISC-V Applications & Tools Committee, serves on the RISC-V Board of Directors, and is Vice-Chair of the Technical Steering Committee, where he champions software ecosystem growth and standards alignment, including efforts to publish RISC-V under ISO.

He instigated the standards-development matrix operations and AI/ML, serving as principal editor of the Integrated Matrix Extension and as the Vice-chair of the Attached Matrix TG.

Edward is the Senior Research Director, Automotive, having previously covered automotive AI and semiconductors as Senior Principal Analyst, IoT, at Omdia. He has written extensively on embedded applications processors and GPUs, edge AI, advanced connectivity, and novel semiconductor architectures such as RISC-V.

He started in the industry in 2016 when he joined Arm as a market intelligence analyst, leading market research and forecasting in the automotive and IoT division. He has also worked in financial services and media roles in London. He has a BA from Durham University and an MPhil in Linguistics from the University of Cambridge.

Elisabetta Boella received her M.Sc. degree in Energy and Nuclear Engineering in 2009 from Politecnico di Torino (Turin, Italy) and her Ph.D. in Computational Plasma Physics in 2014 from the same institution. She currently works as HPC product specialist at E4 Computer Engineering (Scandiano, Italy), where she leads the company effort in several European projects, including MaX, SPACE and EoCoE. Her research interests include numerical modelling, parallel programming, and co-design practices. She has a long-time experience in the development and optimisation of parallel codes using the Message Passing Interface protocol. She is one of the main developers of the massively parallel plasma code ECsim. She also has extensive experience in Graphical Processing Unit (GPU) programming and off-loading of legacy codes to GPU.

Received his B.Sc. in Informatics Engineering in 2025 from Universitat Politècnica de Catalunya (UPC) and is pursuing a M.Sc. in Research and Innovation in Informatics, with a focus on HPC systems, from the same university. He joined the Design Verification team at the Barcelona Supercomputing Center (BSC) in 2024. His research interests include high performance computer architecture, functional verification, and memory subsystem verification.

Emanuele Valea received the master’s degree in electronic engineering from the Politecnico di
Torino, Turin, Italy, in 2016, and the Ph.D. degree in microelectronics from the University of Montpellier,
Montpellier, France, in 2020. He is currently a Researcher at CEA LIST, Grenoble, France. His research interests include hardware security and trust, cryptographic primitives for microelectronics, and security-related aspects of VLSI testing and reliability.

I am a PhD student at the ECS Lab at University of Bologna, where I also earned my MSc in Electronics Engineering. My research focuses on digital architectures, with particular interest in RISC-V vector and matrix extensions and processing-in-memory (PIM) systems. I work on the Monte Cimone project, contributing to the enablement and characterization of the second-generation RISC-V cluster while evaluating the third iteration. I also contributed to AME-PIM, a novel approach that exposes PIM capabilities through the semantics of a matrix extension. In parallel, I work within the DARE project, where I contribute to the delivery of ControlPULP as the power-management controller for the GPP subsystem.

Professor Eugenio Villar obtained his PhD in Electronics many years ago. Since 2002, he has been a Professor in the TEISA Department at the University of Cantabria, where he is responsible for the Embedded Systems Design (HW/SW) area within the Microelectronics Engineering Group. His research has always focused on the specification and design of electronic systems. He is currently working on the use of Artificial Intelligence in the co-design and simulation of model-driven systems. Professor Villar has authored over 100 papers published in national and international conferences and journals. He has participated in electronic systems design projects under European (FP and Horizon Europe) and transnational programs, such as Medea-Catrene, Artemis, ECSEL, KDT, and Chips JU. He is the University of Cantabria's representative in Chips JU and the Director of the Cantabria Chip Chair.

I possess 14 years of expertise in high-performance CPU design, specializing in high-performance core development and inter-core interconnect buses. Throughout my career, I have led the development of multiple processor cores across different instruction sets, taking them from design to successful tape-out and final deployment in sectors including finance, consumer electronics, industrial control, and the Internet of Things (IoT). I have also participated in several national "Core and High-Base" initiatives and hold over 15 granted invention patents

Perf & ASM nerd, practical troublemaker
Care about clean specs, clean mandates, HPC, IEEE754 & the BLAS.

As a senior Engineer in the Firmware Team at Alibaba Damo Academy, Esther specializes in system and power management software standards, with a focus on architecting and developing power management frameworks across diverse operating systems (OS) and firmware technologies. Her work drives innovation in energy-efficient computing and system optimization, aligning with industry-leading specifications to enhance hardware-software synergy.

Flavia Guella is a Ph.D. student in Electronics and Communications Engineering at Politecnico di Torino, under the supervision of Prof. Maurizio Martina. Her research interests include RISC-V based in-cache computing, and co-design methodologies for the efficient deployment of neural networks on low-power systems.

Gianmarco Fortunelli is an Electronic Engineering student at Politecnico di Torino and EURECOM, focusing on embedded systems, hardware security, and computer architecture. His work spans RISC-V security research and digital design, with a strong interest in efficient and secure computing.

Francisco J. Romero received the B.Eng. in Telecommunications Engineering from the University of Granada (UGR, Spain) in 2016 and the M.Eng. in Telecommunications Engineering from the same university in 2018, both with Extraordinary Awards. In 2015, he joined the Department of Electronics and Computer Technology at UGR as an undergraduate researcher, where he began working on embedded systems and wearable devices, later expanding his research to emerging technologies for IoT applications. In 2021, he obtained his PhD with honors in collaboration with the Institute for Nanoelectronics at the Technical University of Munich (TUM, Germany). He also completed several industrial research stays at Infineon Technologies AG and eesy-innovation GmbH, contributing to multiple technology-transfer projects. He is currently an Associate Professor at UGR, where his research focuses on embedded systems, hardware-based security, and memristive and emerging electronic technologies.

Frédéric Desbiens manages the Embedded and IoT programs at the Eclipse Foundation, Europe's largest open-source organisation. In this role, he helps the community drive innovation at the intersection of devices, software, and open collaboration. A passionate advocate for open source, Frédéric works with developers, companies, and researchers to advance the Internet of Things and edge computing. He is also the project lead for Eclipse ThreadX, the first open source real-time operating system (RTOS) certified for safety-critical applications.

Before joining the Eclipse Foundation, he held various technical and leadership roles at Pivotal, Cisco, and Oracle. Frédéric holds an MBA in Electronic Commerce, a BASc in Computer Science, and a BEd from Université Laval in Québec City, Canada.

He is the author of Building Enterprise IoT Solutions using Eclipse IoT Technologies: An Open-Source Approach to Edge Computing (Apress, 2022).

Frédéric Pétrot got a Ph.D. in Computer Science in 1994, and the Habilitation in 2003, both at LIP6 lab, Université Pierre et Marie Curie, Paris, France. Since 2004, he is Professor at Grenoble INP - UGA/Ensimag, teaching mainly architecture and operating system classes. He joined the TIMA Lab, to work on various topics related to multiprocessor systems on chip. He is currently heading the joint UGA, Inria, CNRS team MADMAX.

Frederik Haxel is a researcher at the FZI Research Center for Information Technology. His research interests include developing tools and methods to accelerate the design of safe and efficient RISC-V systems.

Gabriele Ceccolini received his Master's degree in Computer Engineering from the University of Bologna in March 2026. He previously obtained his Bachelor's degree from the same institution in 2023. Since May 2025, Gabriele has been collaborating with CINECA, focusing on the optimization of CFD algorithms on RISC-V platforms.

Germano Brunacci earned his degree in Electronic Engineering from the University of Ferrara, Italy, in 2000. He began his career as a firmware developer, contributing to projects across the automotive, medical, and telecommunications sectors from 2000 to 2010.

In 2010 he joined FIAMM, and later MIDAC, where he served as Firmware Lead Engineer, focusing on Battery Management Systems (BMS) for advanced battery technologies. From 2018 to 2023, he was BMS Component Responsible for 800 V Battery Electric Vehicles (BEVs) at MASERATI, playing a key role in high-voltage system development.

Since 2023, Germano has been part of GLIWA, where he is involved in development of customer specific solutions, as well as training and coaching activities in the field of real-time embedded systems.

Giacomo Valente received the M.S. degree in Electronic Engineering in 2014 and the Ph.D. degree in Information and Communication Technology in 2018 from the University of L'Aquila.
His primary research activities are in electronic design automation, reconfigurable computer architectures, and real-time systems.
Since 2022, he has been an Assistant Professor in Computer Architecture at the Department of Information Engineering, Computer Science, and Mathematics of the University of L’Aquila.
He is the author or co-author of more than 40 research articles in peer-reviewed journals and international conference proceedings. He has been also a reviewer and member of several TPCs related to his research topics

Driven by complex problem-solving, I am a researcher at VORTEX-CoLab specialising in the safety, cybersecurity, and formal verification of real-time embedded systems. My work focuses on bridging the gap between hardware and software to build dependable, high-performance architectures. With an academic and professional background spanning Brazil, the Netherlands, and Portugal, I have contributed to top-tier research in cyber-physical systems, with publications in premier venues like RTSS and DSN. Beyond research, I also have experience teaching undergraduate and master’s level courses in Assembly, C, and NuSMV model checking. I am currently focusing on identifying industry-ready applications for applied research and cross-border collaboration.

Giordano Mancini joined E4 Computer Engineering in 2023, first as R&D Manager and then as CTO from December of the same year. He leads the Tech Factory team, focusing on HPC technology scouting and the development of cluster deployment and management solutions. His background spans research in molecular physics and the management of HPC infrastructures, including a previous role as COO of the HPC Center at Scuola Normale Superiore in Pisa.

Research Engineer at CEA-List, I hold a Master’s degree in Cybersecurity Engineering from Politecnico di Torino. I am passionate about hardware and software security, with a strong focus on fault injection and microarchitectural security.

Giorgio Marletta received his M.S. degree in Computer Engineering from the University of Catania in 2020. He subsequently joined STMicroelectronics as a Compiler Engineer, where he actively works on LLVM for RISC-V and proprietary ISAs.

Giovanni Di Guardo graduated at the University of Catania, Faculty of Ingegneria Informatica in 2000. After graduation he worked for three years as a contractor for the University of Catania. He then joined STMicroelectronics in October 2003 where he focused on MCU development and specifically on architecture, functional and performance modeling and toolchain development. He contributed to the development of proprietary and RISC-V based microcontroller class cores used on several STMicroelectronics products. He leads the toolchain development team and is a staff member of the Application Specific CPU team, contributing to the roadmap of embedded application specific processing

Gundolf Kiefer is a professor for Computer Engineering at the Technical University of Applied Sciences Augsburg. With a PhD from the University of Siegen (2001) and experience at Philips Research, he leads the Efficient Embedded Systems group. His research focuses on RISC-V and customizable hardware for embedded vision and embedded AI.

Guodong Xu is a RISC-V International Advocate and Director of Software Engineering at RISCstar Solutions, with over 20 years of Linux kernel development experience. Previously at Motorola (mobile phone low-level software) and Linaro (Sr. Tech Lead, 10+ years), he now works on RISC-V upstream kernel enablement — including SpacemiT K1/K3 SoC support and RVA23 profile extensions.

A Linux kernel developer focuses on the CPU subsystem, including virtualization, IOMMU, PCIe, Heterogeneous Programming, and RV64ILP32.

Staff Engineer, Alibaba Damo Academy

Haotian Yang is a senior undergraduate student at Shenzhen Technology University and a core teaching assistant of the One Student One Chip program. He is also the founding leader of the One Student One Chip Studio at Shenzhen Technology University.

His research focuses on low-power embedded RISC-V processor design, with interests in microarchitecture optimization, low-power design techniques, and SoC system integration. In addition to technical research and development, he is actively involved in the organization and operation of the One Student One Chip Shenzhen training base, university studios, and student learning communities related to open-source chip education and RISC-V talent cultivation.

Haoyuan Liu, a Digital Design Engineer at the Beijing Institute of Open Source Chip (BOSC), specializes in RISC-V security areas such as MPT, CFI, and PMP. He actively contributes to the XiangShan open-source RISC-V CPU.

Harry has worked in software for 15+ years, with experience in real-time audio processing and open-source projects like OpenAV productions, to datacenter networking SIMD optimizations for DPDK, and now works with Openchip to advance the software ecosystem of Risc-V Vector instructions. As a data-driven technologies he's passionate about tooling to help achieve success, and has presented at many conferences on the topic. He holds 4 patents in the datacenter domain, and many open source contributions.

In his spare time Harry can be found playing badminton or sim-racing, with 24 hour races being the favorite!

Henrik Gustafsson is a Principal Engineer at Qualcomm Technologies, where he contributes to the RISC‑V Research and Standards Team. He has been actively involved with RISC‑V and RISC‑V International since 2018, supporting the advancement of open processor architectures and industry collaboration.
With 29 years of experience spanning telecommunications and radio systems, smart‑grid technologies, and the semiconductor industry, Henrik brings deep technical expertise and a proven track record in system design and innovation.
He holds a Bachelor of Science in Electrical Engineering from the Royal Institute of Technology in Stockholm, Sweden.

Dr Henri-Pierre Charles is scientific advisor to the management of the CEA since 2025, he was research director at CEA-LIST since September 2010. He was previously assistant professor in Versailles University during 17 years, HDR since 2008.

His research interests are in dynamic compilation, Low level code optimization and new methods for code generation for high performances and multimedia applications. He has developed the concept of "compilettes" that can be defined as tiny code generators embedded into applications, able to generate optimal code depending on the data characteristics. This notion is used in heterogeneous architecture context, where code should be generated for CPU and/or accelerators and/or special devices such as in memory computing architecture or heterogeneous architecture / ISA.

He has created many compilation tools allowing to generate binary code at run time with multiple objective like execution speed, code size, energy and heterogeneous computing.

Holger Blasum is research engineer at SYSGO GmbH, with interests in architecture, design, implementation and verification (including formal methods) of safe and secure systems.

Hongbin Zhang is a postdoctoral researcher at the Institute of Software, Chinese Academy of Sciences (ISCAS). He received his Ph.D. degree from the University of Chinese Academy of Sciences. His research focuses on AI system software and compiler technology. He leads the RuyiAI system software team at ISCAS. He launched the Buddy Compiler community and has served as a community mentor for the LFX RISC-V Mentorship and OSPP open-source programs. He is a member of the Technical Steering Committee (TSC) of RISC-V International and serves on the Governing Board of CHIPS Alliance.

Co-founder & CTO of Terapines Technology. More than 15 years compiler design and development experience in Andes, S3 Graphics, Imagination and Terapines. Specialized in CPU, GPU, GPGPU, AI compilers based on MLIR, LLVM and GCC.

Iacopo Colonnelli is an Assistant Professor in the Department of Computer Science at the University
of Turin. He serves on the Technical Committee of the Common Workflow Language (CWL), and is a founding coordinator of the CWL4HPC working group. He has co-authored over 40 peer-reviewed publications in national and international journals and conferences, and has contributed to more than 10 funded research projects. He is currently the local Principal Investigator for the DARE European project (total budget: e240M). His research interests include workflow modeling and management in heterogeneous distributed architectures, high-performance computing and I/O, distributed confidential computing, and large-scale data science.

Ihsane Tahir received a M.S. degree in embedded systems from Grenoble INP - Esisar, Valence, France, in 2020. She subsequently joined CEA LIST as a research engineer. She then joined the OpenHW Foundation in 2026 as a hardware verification engineer. Her works include functional verification, FPGA prototyping and digital design.

Ilya Tuzov received the Ph.D. degree in computer science from the Universitat Politècnica de València (UPV), Valencia, Spain, in 2020. He is currently working at UPV as a researcher. His current research interest include fault-tolerant embedded systems, reconfigurable computing, automated verification and dependability benchmarking.

Ivan Sarno received the B.Sc. degree in Computer Science and the M.Sc. degree in Cybersecurity from the University of Pisa, Italy. He is currently pursuing the Ph.D. degree at the University of Grenoble Alpes, conducting his research at CEA List and TIMA Laboratory, Grenoble, France. His research focuses on secure hardware/software implementation of post-quantum cryptography on RISC-V platforms, including custom ISA extensions for cryptographic acceleration.

Jan Zielasko is a PhD student at the University of Bremen and a researcher at the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). His research focuses on Virtual Prototype-driven tracing, analysis, verification and hardware optimization.

Jeremy Bennett is Chief Executive of Embecosm, an international open source consultancy specializing in compiler tool chains and AI tooling. He is a former academic and author of the standard text book "Introduction to Compiling Techniques: A first course using ANSI C, Lex and YACC" (McGraw-Hill 1990, 1995, 2003). Dr Bennett holds an MA and PhD from Cambridge University. He is aFellow of the British Computer Society, Fellow of the Royal Society of Arts, Member of the IET and a Chartered Engineer.

Jeremy Dahan is an Automotive Compute Sr Tech GTM Specialist at Amazon Web Services. He’s helping customers / partners to tackle the most challenging problems related to automotive software leveraging cloud capabilities. He has over a decade of experience in the automotive industry specifically in embedded software and more recently in the cloud. When not building things on AWS, he’s tinkering with car/IoT sensors.

Jérôme Quévremont graduated in telecommunications and electronics in 1995 (Télécom Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology cortAIx Labs as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security.

CEO of Nuclei System Technology
Ph.D. in Microelectronics, Zhejiang University; 20‑year CPU design & management veteran (ex‑Synopsys/Marvell). Co‑founded Nuclei (at 2018) to lead China’s RISC‑V IP innovation, delivering full‑spectrum cores and ASIL‑D certified automotive solutions. Key community leader driving RISC‑V ecosystem development and domestic semiconductor advancement.

Wang Jingwei is an engineer at the Institute of Software, Chinese Academy of Sciences and a member of the openEuler Technical Committee. He is a RISC-V advocate focused on building the RISC-V software ecosystem based on openEuler and related Linux distributions.

Currently pursuing a PhD in Microelectronics with a focus on digital circuits for edge AI. I work on digital hardware for edge implementations of Transformer models (aka LLMs), with a particular emphasis on attention mechanisms—especially dot-product attention—and on the design of ASICs that implement this computation with optimized power and performance. A goal-oriented and curious engineer, committed to continuous learning and collaboration.

Johannes Hofmann is a graduate student pursuing a Master of Science (MSc) in Applied Research in Engineering Sciences at the Technical University of Applied Sciences Augsburg. His research interests include embedded systems and debugging methodologies, RISC-V hardware development, and embedded AI.

Received the Bachelor of Science in Computer Science from the Julius-Maximilians-Universität, Gemany, 2025. Since 2025, he is a research assistant at the Computer Engineering group under Prof. Dr.-Ing. Matthias Jung. Amateur radio operator.

Jonathan Woodruff is a Associate Research Professor with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.

Jon has 25 years of experience in the semiconductor and software industries and has been involved with RISC-V since 2019. He is currently product manager for RISC-V at Canonical driving product development to strengthen the RISC-V ecosystem.

Jose Sanchez-Yun received his B.S. degree in Computer Engineering from the University of Cordoba in 2022, and his M.S. degree in Software Engineering and Artificial Intelligence from the University of Malaga in 2024. He is currently pursuing a Ph.D. degree at the University of Malaga. His research interests include the development of RISC-V ISA extensions for neural network optimization and the vectorization of time series analysis algorithms.

I am a current PhD student at TUWien. Interested in embedded system design and vector processing.

Research Assistant at FZI Forschungszentrum Informatik

Incoming M.S. Electrical and Computer Engineering candidate at Georgia Tech specializing in VLSI Systems and Digital Design.

Earned Bachelor's of Science in Electrical and Computer Engineering degree at Rice University, graduating with summa cum laude honors.

Before working in the automotive microcontroller area Kajetan Nürnberger has worked in the domain of safety critical aerospace software in an industrial and university environment. He is familiar with various CPU architectures and focused on the HW SW interface. Within Infineon he has contributed to the definition of different automotive controllers with respect to compute architecture SW and tooling.

Konstantinos is a Senior ASIC Design Engineer at Pragmatic Semiconductor, where he works on pioneering projects that push the limits of flexible IC technology. Previously, he was a Research Associate at The University of Manchester. Konstantinos holds an MEng in Electrical and Computer Engineering from the Technical University of Crete and a PhD in Computer Science from The University of Manchester.

Krste Asanović is Professor Emeritus and a Professor of the Graduate School in the EECS Department at UC Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998, then joined the faculty at MIT, receiving tenure in 2005. He returned to Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory, led the ASPIRE Lab, and co-led the ADEPT Lab and Berkeley SLICE Lab. His main research areas are computer architecture, VLSI design, parallel programming, and operating system design.
He has led the RISC-V open ISA project at Berkeley from its inception in 2010 and co-founded the RISC-V Foundation in 2015, which has now become RISC-V International, where he serves as Chief Architect. He also co-founded SiFive in 2015 to commercialize RISC-V processors, serving as Chief Architect there. He is an ACM Fellow and an IEEE Fellow.

Kushtrim Shala is an Albanian technology entrepreneur, innovation strategist, and ecosystem builder with over 15 years of experience in ICT, digital transformation, and startup development. He holds a degree in Computing Sciences from the University of Tirana and an MBA from the University of New York Tirana.
As Co-founder and Executive Director of ALBICT (Albanian ICT Association) and Co-founder of Digital Valley Albania (DiVA), an official European Digital Innovation Hub, Kushtrim has built bridges between technology, policy, and entrepreneurship across the Western Balkans. Under his leadership, ALBICT has supported more than 100 startups through eight accelerator cohorts.
He is also co-founder of the Uplift Startup Accelerator, ICTSlab, and the Albanian ICT Awards. Recognized with the Golden Bee Award by the Prime Minister's Office of Albania, he currently focuses on open hardware ecosystems, RISC-V, AI infrastructure, and digital sovereignty strategies for emerging European economies.

BS/MS Student from Rice University. Background in computer architecture and hardware infrastructure.

Dr. Leonidas Kosmidis is the Group Leader of the Hardware Dependability for Embedded Systems (HADES) group at the Barcelona Supercomputing Center (BSC) and Faculty member at the Universitat Politècnica de Catalunya (UPC). His research interests include hardware and software design for high performance safe and secure embedded systems, and particularly GPUs. He was the recipient of the RISC-V Educator of the Year Award in 2019 and he is involved in several standardisation efforts around RISC-V, hardware design and GPUs for safety critical systems.

Accelerating the Future Computing with RISC-V

I am a PhD Student at the Institute of Information Security at Graz University of Technology.
My research focuses on system security, from the perspective of both hardware/software co-design, as well as improving the security for complex software systems.
I am strongly involved in teaching and have, among other things, helped create a new system security course from scratch.

Electronic Engineer with a BSc (2023) and MSc (2026) in Electronic Engineering from the University of Bologna. Currently a Researcher at Fondazione Chips-IT, focused on the design and development of RISC-V-based processors, accelerators, and SoCs.

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Università di Bologna. He received a PhD from Stanford University. He is a Fellow of the IEEE, of the ACM, a member of the Academia Europaea and a funding member of the Italian Academy of Engineering and Technology. He is the recipient of various awards, including the 2023 IEEE CS E.J. McCluskey Award, and the 2024 IEEE CS Open Source Hardware contribution Award.

Ludovic works at the intersection of open-source software and emerging hardware. He is a key contributor to the RISC-V ecosystem, focusing on the performance and stability of the AI stack. His recent work involves optimizing native dependencies like OpenBLAS and oneDNN and establishing the infrastructure for native PyTorch testing. Through his leadership at RISE, Ludovic is dedicated to making RISC-V a competitive, first-class platform for the next generation of AI development.

Ph.D. researcher in Electrical/Electronic Engineering. Experienced in reconfigurable computing for AI and ML workloads, including FPGA-based accelerator design, hardware/software co-design for embedded systems, RISC-V SoC integration, and custom accelerator interfaces. Proficient in RTL development (SystemVerilog) and embedded C, with a focus on optimizing dataflow and compute efficiency for neural network and machine learning inference/training pipelines.

Luis Waucquez received his BSc and MSc degrees in Electronic Engineering from Universidad Politécnica de Madrid (UPM).
He is currently pursuing a Ph.D. degree at the Center of Industrial Electronics. His current research interest are open computer architectures and fault-tolerant systems

Lukas Füreder is a researcher and PhD student at the Fraunhofer Institute for Applied and Integrated Security (AISEC). The primary focus of his research is memory safety solutions for real-time and embedded applications on resource-constrained platforms.

Lukas Glantschnig is a Master’s student in Information and Computer Engineering at Graz University of Technology (TU Graz), where he also received his Bachelor’s degree. He works part-time at Infineon Technologies, focusing on mixed-signal verification.

Manfred Schlägl is a PhD student at the Institute for Complex Systems, JKU Linz, under Prof. Daniel Große. For 15 years, he worked in industry, focusing mainly on low-level firmware and operating systems for industrial embedded systems. In 2021, he left the industry to resume his studies, completed his Master's degree in Computer Science in 2023, and started his PhD immediately afterward. His main research interests are hardware/software co-simulation using virtual prototypes and hardware verification. He is also deeply interested in operating systems, hardware platforms, and computer architectures, especially RISC-V.

Dr. Manolis Marazakis (Ph.D. in Computer Science, University of Crete, Greece - 2000) is a Principal Staff Research Scientist at the Institute of Computer science, FORTH. His research interests are in architectures and efficient systems software, mainly resource management and storage I/O middleware, for high-performance servers in data center environments. He has contributed to the design, implementation and performance analysis of several system prototypes for HPC, data analytics, multi-tenant workloads, and the convergence of HPC and Cloud infrastructures. He has been FORTH’s technical lead for system software and performance evaluation for European digital sovereignty-focused research and innovation projects, for both HPC and Cloud infrastructure technologies. He is a Senior Member of ACM (since 2018) and IEEE (since 2021), and a Member of the USENIX Technical Society.

MANUEL RODRÍGUEZ earned his M.Sc. degree in Electronic and Computer Engineering at the University of Minho, Portugal, with a focus on Embedded Systems and Micro/Nanotechnologies. He is currently pursuing a Ph.D. in Electronics and Computer Engineering at the same institution, focusing on the development of novel RISC-V ISA primitives for secure virtualization in mixed-criticality systems. Throughout his career, he has contributed to the RISC-V ecosystem providing PoC artifacts for ongoing specifications, mostly in the hardware area. His research interests encompass computer architecture, RISC-V, hardware design, embedded virtualization, and safety-critical and mixed-criticality systems.

In 2024, Marcel Ziswiler joined Codethink as a software engineer. Before, he worked
for more than 13 years at Toradex, spearheading their Embedded Linux adoption. His
introduction of an upstream first policy led to being a top 10 U-Boot as well as Linux
kernel Arm SoC contributor. He has broad experience in designing real-time and
mobile applications for industrial systems. He holds a Certificate in Embedded Systems
Technologies from the UCI and a CS Master from the ETHZ. He spoke at several
international conferences including all ELCs starting 2019 and FOSDEMs starting 2025.

Marco Bertuletti received the B.Sc. and M.Sc. degree in Electrical Engineering in Politecnico di Milano, Milano, Italy. He is currently pursuing his Ph.D. at ETH, Zurich, Switzerland, in the Integrated Systems Laboratory (IIS). His main interests are in the design of multi and many-core clusters of RISC-V processors for next-generation telecommunications.

Marco Edoardo Santimaria is a Ph.D. student in Modeling and Data Science at the University of Turin, where I focus on developing methods and tools to optimize the performance of file-based scientific workflows. His research centers on the CAPIO methodology (born out of a collaboration between the University of Turin and the University of Pisa), which consists of two main components: the CAPIO middleware, a scientific tool designed to enhance I/O performance by enabling transparent streaming capabilities and providing a distributed, in-memory file system without requiring modifications to the workflow’s source code—and CAPIO-CL, a coordination language developed to express file dependencies and annotate streaming semantics across workflow steps.

After completing his Master’s degree in Electronic Engineering at the University of Bologna in 2019, Marco Fariselli began his career at GreenWaves Technologies, a fabless semiconductor company developing RISC‑V multicore processors to enable AI on ultra‑low‑power platforms. His work focused on bridging algorithm design and hardware execution, enabling neural networks and signal‑processing workloads to run efficiently on battery‑powered devices.
He is currently with Luxottica, where he advances embedded machine learning deployment and contributes to the co‑design of next‑generation AI accelerators. His interests lie at the intersection of software optimization, hardware‑aware machine learning, and scalable edge intelligence on emerging architectures such as RISC‑V.

Margherita Rossi received her M.Sc. degree in Electronic Engineering from the University of Bologna, Italy, in 2025. She is currently pursuing her Ph.D. in Electronics, Telecommunications, and Information Technologies Engineering at the University of Bologna, under the supervision of Prof. Simone Benatti. Her work focuses on the design and deployment of energy-efficient embedded systems for wearable biomedical applications, with particular interest in on-device machine learning and real-time human-machine interaction.

He received the Diploma and PhD degree in electrical engineering from the Technische Universität Kaiserslautern, Germany, in 2011 and 2017, respectively. From 2011 to 2017 he was a researcher at the Microelectronic Systems Design Research Group of RPTU Kaiserslautern. Since 2017 he is with the Fraunhofer Institute for Experimental Software Engineering in Kaiserslautern as Expert Engineer for virtual hardware engineering. In 2018, he received the EDAA Outstanding Dissertation Award for this work. At Fraunhofer IESE in Kaiserslautern, he has been leading many research and industrial projects in the area of embedded systems since 2017 and has published more than 100 papers in relevant journals and conference proceedings. Since 2023, he is professor at the University of Würzburg. Matthias Jung's scientific focus is on embedded and autonomous systems, especially with a focus on memory architectures, functional safety, and virtual product development of embedded systems through virtual platforms and simulations.

Mattia Orlandi received his M.Sc. degree in Artificial Intelligence from the University of Bologna, Italy, in 2022. He is currently pursuing his Ph.D. in Data Science and Computation under the supervision of Prof. S. Benatti at the Energy-Efficient Embedded Systems Laboratory (EEES Lab), DEI Department, University of Bologna. His research activities involve bio-signal processing with machine learning on low-power computing platforms. He is investigating how to develop advanced human-machine interfaces based on EMG.

Mattia Paladino is a Project Manager at E4 Computer Engineering. He is currently involved in several European projects within the HPC sector, focusing on areas such as co-design for optimizing ML applications, green computing, and RISC-V. He holds a master's degree in Nuclear and Subnuclear Physics from the University of Bologna.

RISC-V Engineer, mainly focus on Go compiler/toolchains developement

Michael Rogenmoser received his BSc and MSc degrees from ETH Zurich in 2020 and 2021, respectively. In 2021, he joined the Integrated Systems Laboratory of ETH Zurich as a PhD candidate under the supervision of Prof. Dr. Luca Benini. His research interests include fault-tolerant architectures for space, multicore processors, and reliability in systems-on-chip (SoCs).

Mihailo Obradovic is an electronics engineer at CERN. His current work focuses on co-simulation methodologies for hardware modelling, with a specific interest in evaluating RISC-V SoC integration into detector readout systems and investigating how open-standard processor architectures can satisfy the performance and reliability constraints typical of high-energy physics applications. Mihailo holds a Bachelor's degree in electronics engineering from the University of Belgrade.

Mike Eftimakis brings three decades of experience in the semiconductor and electronics industry, having held senior technical and business leadership roles throughout his career. He has contributed to innovation and growth at companies such as VLSI Technology, NewLogic, Arm, and Codasip, and has also founded and led his own company. His expertise ranges from chip design engineering and system architecture to product and company management, marketing and strategy, making him a key contributor to the growth and success of microelectronics organisations.
He is a Founding Director of the CHERI Alliance, a non-profit industry association dedicated to accelerating the adoption of CHERI technology. This technology addresses the root causes of most current cyberattacks, contributing to a safer and more trustworthy digital world.

I'm a doctoral researcher at Tampere University. My research focus is hardware security and specifically, researching CPU side-channel attacks and defenses. Previously, I worked on hardware design, verification and physical implementation for 2 System-on-Chips at Tampere University, and now I'm starting my doctoral research.

Moritz Waser is a PhD student in the Secure Systems (SESYS) group at ISEC, Graz University of Technology.
His research interests include memory safety, confidential computing, capability systems and hardware security.

Nathan Egge is a Staff Software Engineer at Google working on the native tools and libraries used to build AOSP and Android applications, including the C/C++ and Rust toolchains. He serves as co-chair of the Technical Steering Committee in RISE and previously as the chair of the System Libraries WG. Nathan received the RISC-V Board of Directors Software Leadership award in 2024 for contributions to RISC-V industry adoption.

Niccolò Lentini is a PhD student in Computer and Cybersecurity Engineering at Politecnico di Torino, Italy. His research focuses on hardware and system security, with particular emphasis on fault injection attacks, the resilience of RISC-V systems. He received his MSc in Cybersecurity Engineering from Politecnico di Torino, where his Master’s thesis focused on securing avionic embedded systems using hardware-assisted security mechanisms. His current research investigates methodologies and tools for evaluating the security of computing platforms against physical attacks.

Sr. Engineer at Tenstorrent.

Previously open sourced Riescue, a direct test framework and compliance test generator. I'm using this experience and leveraging AI to create RISC-V stimulus

Tenstorrent systems software developer

Recently graduated from Harvey Mudd with a CS degree. I spent the last year building a VS Code extension for the RISC-V Unified Database as part of our Clinic program—think grammar design, validators, and making architectural specs actually usable for developers. Interested in the intersection of tooling, specification, and how good IDE support can make a real difference.

Noam Cohen is the Co-Founder and CTO of keplertech.io. Throughout his
corporate career, he led R&D teams at SNPS and Siemens, dedicated to compiler
development for hardware prototyping and emulation, with a focus on optimizing
solutions to NP-hard problems such as partitioning, placement, and routing, and
with an emphasis on high performance computing. After 10 years with the EDA
industry leaders, he co-founded keplertech.io with the aim of introducing innovation
in both technology and user experience to hardware design software tools.

Pasquale Davide Schiavone (Davide) is a Scientist at the Swiss Federal Institute of Technology Lausanne (EPFL) and Director of Engineering of the OpenHW Group. He was previously working in the ESL lab at EPFL as a PostDoc from 2022 to 2025. He obtained the Ph.D. title at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group in 2020 and the BSc. and MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016, respectively. His main activities are the RISC-V CPU design and low-power energy-efficient heterogeneous computer architectures for smart embedded systems and edge-computing devices.
Since the Ph.D., he delivers training workshops to companies and universities.

A list of his publications is available at https://scholar.google.ch/citations?user=mfZQ9zUAAAAJ&hl=en

My GitHub: https://github.com/davideschiavone

Dr. Ku works for Andes Technology Corporation and is enthusiastic about processor and platform security. He currently serves the IOPMP TG as the chair (Jul.2022 - now) and the TEE TG as the vice-chair (Apr.2021 - Mar.2022), and has presented several times in RISC-V Summits.
With 20+ years of experience in the semiconductor industry, he has participated in over a dozen ASIC projects, particularly in SoC design, optimization, and security.
He majored in Computer Engineering, was granted a Ph.D., and became an adjunct associate professor at National Tseng Hua University, focusing on processor security, parallel algorithms, and algorithm analysis.

Having started personal journey in Uzbekistan, and professional career in Delft, Peter delved into SW engineering (at TU/d) towards streaming and multimedia systems for CE (architecture & infrastructure group at Philips Research, NatLab). He developed a passion for fun PLs such as Icon, Scheme and Julia, which he applied in projects such a simulation modeling, virtual prototype environments and a joint project on SDR with Nokia. Dataflow compiler & middleware project got him further into the DSP algorithms and radio & radar transceivers - focus of the work at NXP Semiconductors for more than 10 years, resulting in IPs for, e.g., SAF85xx made with Julia and RoadLink SAF5400 made with SystemC and HLS. At IMEC since 2022, he focuses on SW/HW interfaces, simulation infra and on micro-arch modeling for RISC-V and CMOS2.0. Since 2019 he consults in efficient networking stack simulation, automation and nano-kernels such as Zephyr.

Ms. Prachi Pandey is a Senior Compiler Engineer at C-DAC, where she works on MLIR/LLVM-based compiler development for indigenous processors, GPUs, and AI accelerators. She has nearly two decades of experience in HPC, parallel programming, compilers, and runtime systems. Her research interests include compiler optimization techniques, automatic parallelizing compilers, performance portability for heterogeneous architectures, and parallelization strategies for HPC and AI workloads.

I am a PhD student in Chamers University of Technology and currently in Barcelona Supercomputing Center. My research is about optimizating performance of memory system for CPU and GPU workloads. I am familiar with CPU/GPU archiecture and also gem5 and accel-sim simulators.

Qiu Jing is a CPU design engineer at Alibaba DAMO Academy, where he has been involved in the design of multiple XuanTie RISC-V processors. He served as the Acting Chair during the inception phase of the RISC-V AME (Attached Matrix Extension) Task Group, and has been actively contributing to the TG's discussions since its establishment. His work focuses on bridging the gap between AI workload requirements and RISC-V ISA design, with particular emphasis on vector/matrix extension architecture and its hardware implementation.

About Me

Study and work

I am currently an embedded systems engineering student at ESISAR engineering school and a work-study research engineer at the CEA in Grenoble. I work on compiler research while assisting Henri-Pierre Charles (https://blog.hpch.net/), focusing on low-level optimization and embedded computing systems.

Passion

I am passionate about embedded systems, firmware development, hardware architecture, and the interaction between software and hardware.

My Specialities

• Embedded systems engineering
• Low-level programming
• Compiler research
• Dynamic runtime compilation
• Firmware and system optimization
• Hardware/software co-design

Why RISC-V Interests Me

RISC-V interests me because of its open and flexible philosophy, enabling experimentation and innovation in embedded computing. I find it especially exciting as it allows deeper exploration of the relationship between compilers, architectures, and runtime performance.

I believe open architectures like RISC-V will play a key role in future embedded systems.

Radim Krčmář is an engineer at Qualcomm whose work spans the lower levels of the RISC-V stack, from ISA specifications to operating system design, with a current focus on security and virtualization.

Rae Parnmukh is Director of IP Product Operations at Tenstorrent, where she focuses on enabling high-performance compute through RISC-V and AI IP and close hardware–software co-development.

Raffaele Montella is an Associate Professor with tenure in Computer Science
at the Department of Science and Technologies (DiST), University of Naples
“Parthenope” (UNP), Italy.

Ramon Canal (PhD ,2004) is a Professor at the Universitat Politècnica de Catalunya (UPC), in Barcelona, Catalonia, EU. He worked at Sun Microsystems in 2000, and he was a Fulbright visiting scholar at Harvard University in 2006/2007 and a visiting professor at the University of Cyprus in 2019/2020. His research focuses on power and thermal aware architectures, as well as reliability and security. He has been programme committee member in several editions of HPCA, ISCA, MICRO, DATE, HiPC, IPDPS, ICCD, ICPADS, CF. He has been co-general chair of DFTS 2025, HPCA 2016 and IOLTS 2012. He has been track co-chair for DATE 2019 and 2020. He is currently an associate editor of the IEEE Transactions on Computers, ACM Transactions on Architecture and Code Optimization (TACO) and the Journal of Parallel and Distributed Computing (JPDC). He is a member of the IEEE.

Rebeca Rasco Flores holds a BSc in Health Engineering from the University of Seville and an MSc in Mechatronics Engineering from the University of Málaga. She is currently a Research Fellow in the Department of Computer Architecture at the University of Málaga, where she is pursuing a PhD in Mechatronics Engineering. Her research focuses on the optimization and acceleration of quantum simulators on high-performance architectures, with a particular interest in RISC-V vector extensions and multi-core parallelism. Her work aims to bridge the gap between advanced classical computing and the efficient simulation of quantum circuits.

Riccardo Tedeschi received his Master's Degree in Electronic Engineering from the University of Bologna in 2023. He is now pursuing a Ph.D. in Digital Systems Design within the Department of Electrical and Information Engineering (DEI) at the same university and is currently a visiting researcher at ETH Zürich. His research centers on RISC-V architectures tailored for embedded platforms, particularly in the areas of performance optimization and reliability.

Having successfully completed an MSc in High Performance Computing at EPCC, I decided to continue on to PhD research focusing on the opportunities that RISC-V technology brings to HPC.

The central hypothesis of this research is that emerging RISC-V Integrated Matrix Extension (IME) can provide a scalable, efficient and performant foundation for HPC workloads. New compiler and programming-model abstractions developed to expose and optimise matrix-centric execution in a portable and reproducible manner would provide a platform to evaluate these benefits.

Representatives from Qualcomm, Synopsys, and an Independent Researcher who are actively contributing the the RISC-V High-Assurance Cryptography task group.

Roberto Giorgi is an Associate Professor in the Department of Information Engineering at the University of Siena, Italy (qualified for Full Professorship). He received his PhD in Computer Engineering and his Master’s in Electronics Engineering, both summa cum laude, from the University of Pisa. He coordinated the 4-year TERAFLUX (Future and Emerging Technologies) and 3-year AXIOM (H2020) projects, was a Work Package leader in Embedded Reconfigurable Architecture, and contributed to HiPEAC and SARC. He participated in ChARM, developing software for ARM-based embedded system performance evaluation. Selected as an ICT/HPC expert by the European Commission, he has authored over 160 scientific papers. His research focuses on Computer Architecture, including Embedded Systems, Multiprocessors, Memory Performance, Workload Characterization, and Reconfigurable Computing. He is a Lifetime Member of ACM and a Senior Member of IEEE and the IEEE Computer Society.

Rodrigo Olmos is a researcher in heterogeneous RISC-V SoC design and hardware acceleration at Universidad Politécnica de Madrid (UPM). His work focuses on hardware/software co-design, multicore integration, custom ISA extensions, and FPGA-based prototyping for embedded and high-performance systems.

Roman is a co-founder of Ainekko: a 100% open-source company on a mission to democratize how “the machine learning community collaborates on models, datasets, and applications” and helping “the AI community building the future”. He is a serial entrepreneur, technologist and a co-founder and former CTO of ZEDEDA Inc. who is also deeply involved in the world of Open Source as both VP of Legal Affairs at the ASF and a former VP of Technology at The LF.

Rubén Padial-Allué received the B.Sc. degree in industrial electronics engineering from the University of Granada, Spain, in 2016, and the M.Sc. degree in microelectronics from the University of Sevilla, Spain, in 2020. In February 2023, he joined the Department of Electronics and Computer Technology at the University of Granada as part of a research project, and is currently finishing his PhD on the implementation and optimization of artificial neural networks for hardware acceleration on FPGA devices. His current research interests include embedded systems, FPGAs, and their applications in the field of artificial intelligence.

Sadia Shamas is a PhD student in the National PhD. Program in Cybersecurity at IMT Lucca and Politecnico di Torino, Italy. Her research focuses on hardware and system security, with particular emphasis on cache side-channel attacks on RISC-V. She received her master's degree in Computer Science from Lahore University of Management Sciences, Lahore, Pakistan, where her master’s thesis focused on developing an energy estimation framework for embedded processors using a hybrid instruction and functional-level power/energy analysis approach. Her current research investigates the potential for side-channel attacks in RISC-V cryptographic implementations using a simulation environment.

Sai Rajat is an Engineer working on building high performance RISC-V CPU Cores and System IP at Tenstorrent. His work is deeply rooted in computer architecture, with a specific technical focus on IOMMU and cache coherency. He holds a degree in Electrical and Electronics Engineering from BITS Pilani. Driven by a belief in RISC-V ISA and a strong interest in advancing hardware systems, he joined Tenstorrent in 2024 after stints at Google Hardware and Samsung India.

Samuel (Sam) Grove is the Head of Software and Tools at MIPS. He has over 20 years of experience in defining products, designing embedded software, operating systems, and leading community-driven open-source software initiatives. In his current role, Sam is responsible for defining product strategy, roadmap execution, and go-to-market activities for MIPS software solutions.

Prior to joining MIPS, Sam was Director of Product Management for Software at SiFive, where he led key initiatives across compiler toolchains, development tools, and software stacks supporting high-performance RISC-V IP platforms. His work led to the realization of SiFive’s next-generation development boards that have played a pivotal role in growing the RISC-V software ecosystem across embedded RTOS projects, Linux Distributions, and optimized software libraries commonly used in AI/ML runtimes.

Scottie von Bruchhausen is the founder of RISCVML, an educational platform teaching Rust-based embedded systems development on RISC-V hardware. Originally from Biloxi, Mississippi, he has called Germany home since 1994 and is based in the Bad Schwalbach/Wiesbaden area. A fully remote DevOps engineer and CCNP-certified network specialist, Scottie works across Rust, Go, and Python with deep expertise in Cisco datacenter routing and switching, VXLAN fabrics, vulnerability assessment, and Checkpoint security (CCSA). His experience with AI/ML and LLMs, combined with years of network automation and strategic infrastructure insight, sparked the vision for RISCVML — bridging the gap between RISC-V hardware availability and developer education. When not pushing the limits of network automation or crushing Cisco bugs, Scottie is an avid outdoorsman and licensed skipper, sailing the Danish coast — occasionally with a Cisco ISE instance authenticating IoT devices aboard his 28-foot sailboat.

Sebastian Frey received his M.Sc. degree in Electrical Engineering and Information Technology from
ETH Zürich, Switzerland, in 2022. He is currently working toward his Ph.D. in Information Technology and Electrical Engineering under the supervision of Prof. L. Benini at the Integrated Systems Laboratory, D-ITET, ETH Zurich, Switzerland. His research interests focus on the design of intelligent, head-centric wearables and on applying machine learning for biosignal processing on low-power devices, aiming to advance smart wearable technologies for real-time health monitoring and human-computer interaction.

Simon Wegener completed his Master’s degree in computer science at the University of Saarland. He joined AbsInt in 2011, specializing in static analysis of binary code. Since then, he has contributed to a multitude of German and European research projects and authored or co-authored a number of peer-reviewed publications on timing analysis for safety-critical embedded systems. As part of TRISTAN, and together with five project partners, he worked on a tracing ecosystem for RISC-V.

Spandan Das is a Ph.D. student at the Group of Computer Architecture in University of Bremen, under the supervision of Professor Dr. Christoph Lüth and Prof. Dr. Rolf Drechsler. He received his B.Sc. and M.Sc. degrees in Mathematics from Indian Institute of Science Education and Research Kolkata, India, and M.Tech. in Computer Science from Indian Statistical Institute Kolkata, India. His Ph.D. work concerns designing hardware-based security and related benchmarks for resource-constrained IoT devices.

Stefano Di Carlo is a full professor of computer engineering at Politecnico di Torino, Department of Control and Computer Engineering, Italy. He received his Ph.D. and M.S. degrees in Computer Engineering from Politecnico di Torino in 1999 and 2003, respectively.

He has authored over 300 publications in major journals and conference proceedings on a wide range of topics. Major topics include dependable computing, artificial intelligence systems, and computational biology. His current research interests include emerging computing paradigms for reliable, energy-efficient computing; computer architectures; neuromorphic computing; systems; and computational biology.

Stefano Di Matteo received his M.Sc. (2019) and Ph.D. (2023) respectively in Electronic Engineering and Information Engineering from the University of Pisa. He is currently a tenure-track researcher in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction Set Extensions for PQC

Sven Schönewald received his B.Sc and M.Sc
in 2017 and 2020, respectively, from the Leib-
niz University of Hannover. He is currently a
research associate and Ph.D. candidate at the
Institute of Microelectronics Systems (IMS) from
the Leibniz University of Hannover. His research
focuses on exploring new and efficient archi-
tectures for digital signal-processing tasks. His
main research interest is in the field of RISC-V
based processors.

Tanya is a co-founder of Ainekko: a 100% open-source company on a mission to democratize inference and fine-tuning of all popular open-weight models with a hardware/software product.
Tanya also has started AIFoundry open source ecosystem of AI projects and engineers working on different building blocks of these stacks while maintaining the common goals and compatibility.

Before that Tanya has been involved in the tech world and open source in many different roles. She is an ex-VC @Almaz Capital with OSS and RISC-V portfolio, ex-OSS policy maker, working to integrate developing countries into the global scene while building local independent infrastructure, founder of project helping tech companies affected by the wars to leverage OSS for freedom of tech from politics.

He is a professor at the Institute of Space and Astronautical Science (ISAS) of the Japan Aerospace Exploration Agency (JAXA). He is engaged in solar system exploration, particularly research on planetary exploration rovers for celestial surfaces. As principal investigator, he developed the MINERVA and MINERVA-II rovers for the asteroid sample return missions of the Hayabusa and Hayabusa2 spacecraft. He has also been involved in multiple lunar exploration missions, including the OMOTENASHI CubeSat and the SLIM landing mission. He served as principal investigator for the LEV-1 rover for the SLIM mission.

Dr. Tianhai Liu is a postdoctoral researcher at KIT and a project lead at aicas GmbH. His work focuses on formal methods, consistency analysis, and verification for cyber-physical systems, with applications in automotive software, IoT architectures, and FPGA-cloud integration.

Associate professor
Institute of Computing Technology, Chinese Academy of Sciences
Research interests: computer architecture, memory system, memory security

Master’s student in Computer Science at the University of Würzburg.

I'm an Assistant Professor of Reconfigurable Computer Architectures in the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology and a RISC-V Advocate. I completed my PhD under Prof. Marcel Baunach, earning the Doctor of Engineering Sciences (Dr. techn.) degree sub auspiciis Praesidentis. My research focuses on sustainable, flexible, and runtime-reconfigurable microcontroller architectures for embedded systems – especially FPGA-based RISC-V – at the hardware-software interface, including processor logic and embedded operating systems. I teach CPU architecture and implementation, embedded programming, and scientific writing. I have authored peer-reviewed publications in international journals and conference proceedings and am active in several RISC-V SIGs, Euromicro, the ACM, and the German Informatics Society (GI).

Tor Jeremiassen is a senior staff software engineer at Google LLC working on tools supporting architectural exploration, in particular, instruction level simulation frameworks. He brings with him 30 years of experience in writing simulators and frameworks for a variety of processors and application specific accelerators, particularly in the embedded space.

Tor earned a Ph.D. in Computer Science from the University of Washington, specializing in compile time optimizations to improve cache performance on shared memory multiprocessors. Tor also holds an M.S. in Computer Science from the University of Washington, and a B.S in Computer Science from the University of Texas at Austin.

Trevor is an embedded systems developer at BayLibre, where he works on everything from the Yocto Project, to automation with CI and kernel development.

Troy Jones is the RISC-V CPU IP Product Manager at Tenstorrent focused on accelerated compute and RISC-V IP. With 26+ years in embedded systems and semiconductor IP, he has led product strategy, adoption, and go-to-market efforts at Tenstorrent, Codasip, AMD, and Xilinx. He is known for translating technical depth into clear product direction, aligning roadmaps with market needs, and partnering across engineering, sales, and ecosystem teams. His experience spans RISC-V IP adoption, space-grade IP development, and Linux product leadership. A frequent industry speaker, Troy represents Tenstorrent at events such as RISC-V Summit and DAC, helping drive awareness, partnerships, and business growth.

Tsung-Li Chen is a master’s student in the Department of Computer Science and Information Engineering at National Taiwan University of Science and Technology (NTUST). His research interests focus on computer architecture, microarchitectural performance modeling, and RISC-V processor design. His current work explores lightweight performance simulation frameworks for modern out-of-order processors by integrating timing models with functional simulators. Tsung-Li has been actively involved in RISC-V related research and previously presented work at the RISC-V Summit North America.

A working student at PlanV, currently pursuing a Master's in Embedded Computing Systems at RPTU-Kaiserslautern, Germany.

My name is Utku Budak, and I am a Research Assistant and PhD Candidate at the Chair of Security in Information Technology at the Technical University of Munich (TUM). In close collaboration with Siemens, my research focuses on enhancing the cyber resilience of embedded systems.

Valeria Piscopo received the B.Sc. and M.Sc. degrees in Electronic Engineering from Politecnico di Torino, in 2021 and 2024 respectively. Since November 2024, she is a Ph.D student in Electrical, Electronic and Communications Engineering at Politecnico di Torino. Her research activity is centered on the design of secure hardware accelerators for Post-Quantum Cryptography and their integration in RISC-V ecosystems.

Vasileios Karakostas is an Assistant Professor at the Department of Informatics and Telecommunications of the National and Kapodistrian University of Athens, and member of the Computer Architecture Lab. His research interests lie in the areas of computer architecture, memory systems, hardware/OS interaction, operating systems, resource management, and parallel systems.

Victor Jean-Baptiste Jung received his Bachelor’s Degree in Computer Science and Engineering Physics from Juniata College, and his Master’s Degree in Computer Science from the Institut Supérieur de l’Electronique et du Numérique of Lille (ISEN Lille) in 2022. After 3 months as a research intern with KU Leuven’s MICAS Research group, supervised by Prof. Marian Verhelst, he's currently pursuing his Ph.D. at the Integrated Systems Laboratory with Prof. Dr. Luca Benini. His current research interests include Efficient deployment of ML models on Microcontrollers, Tiny Transformers, Scheduling, and Quantization.

Scientist at Centre for Development of Advanced Computing (C-DAC), Bangalore, India

PhD student at the LEAT laboratory (Laboratoire d'Électronique, Antennes et Télécommunications), Université Côte d'Azur, France. Research focuses on neuromorphic computing, specifically the design and optimization of energy-efficient hardware accelerators for Spiking Neural Networks (SNNs).

Wenhao Wang is an Associate Professor at the Institute of Information Engineering, Chinese Academy of Sciences. His research focuses on confidential computing, side-channel attacks, hardware-assisted security, and trustworthy systems. He has published extensively in top-tier venues such as USENIX Security, IEEE S&P, ACM CCS, NDSS, and ASPLOS. The confidential computing architectures proposed by his team have been deployed at scale in commercial systems by companies including Ant Group, Alibaba Cloud, and Huawei.

A member of the openKylin Technical Committee, where he leads the RISC-V and RISC-V AI SIGs. An active contributor to the global RISC-V community, he is dedicated to advancing the RISC-V software ecosystem and hardware-software co-design within openKylin. His research interests focus on next-generation operating systems and high-performance RISC-V implementations for AI workloads.

PhD research engineer in Computer Architecture at Universitat Politècnica de Catalunya (UPC) and the Barcelona Supercomputing Center (BSC), focused on domain-specific hardware acceleration for Post-Quantum Cryptography (PQC) on RISC-V systems. Over 6 years of hands-on experience in hardware design (Jan 2020 – Present), with core expertise in RTL development and contributions spanning verification, physical design, and silicon bring-up. Participated in four silicon test-chip tapeouts (TSMC 65 nm, GlobalFoundries 22 nm, Intel 3). Experienced in custom RISC-V ISA extensions, hardware/software co-design, and FPGA-based High-Level Synthesis (HLS) prototyping as part of a full-stack research workflow for efficient and scalable computing systems.

Senior Software Engineer at SpacemiT, specializing in system application development and customer support.

I'm a Research Engineer at Barcelona Supercomputing Center (BSC-CNS). I received a B.Sc. degree in Electronic and Telecommunications Engineering from the Universitat Politècnica de Catalunya in 2022. I joined BSC-CNS in 2024 within the High-Performance Domain-Specific Architectures group, later earning a M.Sc. degree in Electronic Engineering in 2025. My work focuses on RTL design for decoupled access-execution architectures, targeting sparse workloads.

A master's student at Tsinghua University

Chief Engineer of Institute of Software, Chinese Academy of Sciences

Received the Bachelor of Science in Games Engineering from the Julius-Maximilians-Universität, Gemany, 2025. Since 2025, he is a research assistant at the Computer Engineering group under Prof. Dr.-Ing. Matthias Jung.

Yenkai Wang is a senior software engineer at Google working on RISC-V architectural validation and system simulation. His professional experience is in the areas of HW/SW co-design, system verification, FPGA validation, and performance modeling. Yenkai earned a Master of Computer Science from the University of California, Irvine. He also holds an M.S. in Computer Engineering from National Yang Ming Chiao Tung University.

Yichao Zhang received his M.Sc. degree from Nanyang Technological University, Singapore, in 2017. He served as a Physical Design Engineer at MediaTek and as the Lead Application Engineer at Cadence Design Systems in Singapore until 2021.
In 2021, he joined the Integrated Systems Laboratory at ETH Zurich to pursue a Ph.D. under the supervision of Prof. Dr. Luca Benini. As a developer of the Parallel Ultra-Low Power (PULP) platform, his research focuses on physically feasible, ultra-large-scale many-core shared-memory architectures with both scalar and vector processing, leveraging scalable, high-bandwidth, low-latency Network-on-Chip. On the application side, he focuses on software-defined B5G/6G Open Radio Access Networks for programmable baseband Physical Uplink Shared Channel processing.

Yiftach Gilad is the Senior Director of RISC-V CPU at NextSilicon, where he leads the development of advanced processor architectures designed for the next generation of AI and high-performance computing systems. With deep expertise in CPU microarchitecture, system design, and silicon development, Yiftach plays a central role in shaping the company’s RISC-V strategy and the evolution of the Arbel processor.

Yiftach has over 20 years of experience in engineering, having worked at Intel for 18 years, until 2021, when he joined NextSilicon. There, he has been instrumental in transforming ambitious architectural ideas into real, production-ready silicon.

Yinan Xu is an Assistant Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He received his B.Eng. degree from the University of Chinese Academy of Sciences in 2019 and his Ph.D. degree from ICT, CAS in 2025. He is a core developer of the XiangShan open-source high-performance RISC-V processor, where he has pioneered several agile design and verification techniques that have been successfully integrated into the project. His work has been recognized with the CAS President’s Special Award, the ICT Director’s Special Award (Xia Peisu Award), and the National Scholarship. His research contributions have been published in leading venues such as MICRO, HPCA, DAC, and JCST. Notably, XiangShan and its agile design methodology were selected as one of 2022 IEEE Micro Top Picks, recognizing it as one of the year’s most influential conference papers to computer architecture.

Yong Yang received his Ph.D. in Engineering and holds the title of vice Professor. He is the Vice General Manager and Board Member of WCH (Nanjing Qinheng Microelectronics), and Chairman of the Nanjing RISC-V Microcontroller Research Institute. He was the inaugural Vice-Chair of the RISC-V International Certification Steering Committee (CSC). He also serves as an off-campus supervisor at Southeast University and an Industry Professor of Jiangsu Province. With over a decade of R&D experience in embedded systems and IoT integrated circuits, he has spearheaded the design and mass production of proprietary RISC-V MCUs, Bluetooth Low Energy (BLE) SoCs, and USB 3.0 SuperSpeed chips. His technical expertise spans RISC-V ISA, processor microarchitecture, RISC-V Domain-Specific Architectures (DSA), interrupt controllers, and RF transceivers and Antenna design.

Dr. Yueh-Feng Lee received his Ph.D. degree in computer science from National Chiao Tung University. He previously worked at Mediatek and Industrial Technology Research Institute. His areas of focus include AI compiler and runtime, hypervisor technology, and embedded systems.

I am currently an Assistant Research Fellow at the Center for Advanced Computer Systems, Institute of Computing Technology, Chinese Academy of Sciences. My research interests include formal methods, hardware-software model checking, and deep integration of hardware and software. I completed my Ph.D. in Software Engineering at the Institute of Software, Chinese Academy of Sciences in 2024, and received my Bachelor's degree in Statistics from Northeast Normal University in 2017.

Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao co-founded Beijing Institute of Open Source Chip (BOSC). His research interests include computer architecture and computer systems. He is leading the XiangShan project, which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019. His work was published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, MICRO etc. and was selected to IEEE Micro Top Picks. He was the winner of RISC-V International Technical Leadership Award, CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

Email: luoyunxiang@iscas.ac.cn
Intelligent Software Research Center (ISRC), Institute of Software, Chinese Academy of Sciences (ISCAS)

Yvan Tortorella received the Ph.D. degree from the University of Bologna, Italy, in 2025, with a dissertation on RISC-V-based heterogeneous computing platforms for reliable space computing. He is currently with Fondazione Chips-IT, where he is a postdoctoral researcher and digital IC designer working on mixed-criticality space processors and AI accelerators.

Zdenek received the PhD degree from the Brno University of Technology, Czechia, where he played a significant role in the research related to processor development automation. It enabled the creation of the processor development tools, Codasip Studio, that he has been driving ever since at Codasip. Zdenek has continued working as the chief architect of Codasip Studio for more than 12 years. He has also been the architect of diverse processor cores, including but not limited to 16/32-bit architectures for IoT, 32/64bit DSP-oriented architectures, or Linux capable architectures. All of these architectures were developed using Codasip Studio, and many of them were based on the RISC-V ISA. Zdenek has been also involved in embedded systems design (software and hardware) and driving R&D activities for many years.

I am Huazhong Zheng, a Master’s student at the Institute of Computing Technology, Chinese Academy of Sciences. My research focuses on RISC-V processor fuzzing. Currently, I am working on adaptive mutation operator scheduling algorithms, enabling fuzzers to dynamically select more effective mutation strategies to improve coverage and vulnerability detection efficiency.