Digital Design Engineer with 3+ years of industry experience in RTL design and verification, specialising in RISC-V CPU architecture, ISA extensions, and hardware accelerators for FPGA and ASIC targets. Passionate about open-source CPU design, computer architecture, and hardware/software co-design. Active contributor to the RISC-V ecosystem, including CVA6, SERV, and RISC-V Architecture Compatibility Test Suites (ACTs).
- APEX: Accelerating FFT on CVA6 with a Tightly Coupled CV-X-IF Co-processor
- AI-Driven Testlist Generation for RISC-V Core Verification
- Coverage-Directed Smoke Regression Optimization via Greedy Set Cover for RISC-V Verification
Abinaya Senthil is a Design Verification Engineer at NXP Semiconductors, Austin, Texas specializing in UVM-based IP verification, System Verilog, CDC verification, and memory injection methodologies for complex IP designs. She is a founder of SiliconDV , a technical education platform for semiconductor verification engineers. She is a member on the IEEE WIE MRP award review committee and has presented CSTIC 2026 ( IEEE Xplore indexed). Her research focus on AI-driven verification optimization and GPU accelerated simulation for RISC-V architectures.
- GPU-Accelerated Parallel Simulation for RISC-V Multi-Core IP Verification
I am a compiler engineer at 10xEngineers, working on enabling the compilation of LLMs and vision models for custom hardware/accelerators using IREE, an MLIR-based AI compiler. I have experience in writing optimized kernels for RISC-V Vector (RVV) and custom hardware, LLVM middle-end and backend development.
- Optimizing Llama.cpp and GGML for RISC-V Vector (RVV)
- Optimizing IREE Compilation and End-to-End Object Detection Pipeline for RISC-V
- Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW
- RISC-V POWERED QUANTUM SENSOR
- Bicameral+: re-assessing split vector and scalar cache designs for increased efficiency
- Integrated Development Environment Features for Unified Database Specification Development
- Integrated Development Environment Features for Unified Database Specification Development
Akif has done in BS in Computer Engineering from ITU Lahore, Pakistan. He has 3+ years of experience in the semiconductor industry, specializing in RISC-V software. His work spans multiple OSes, RTOSes, and microkernel RISC-V enablement. Currently working as Systems/Firmware Engineer at 10xEngineers. He recently joined the Eclipse Foundation as a ThreadX RTOS committer. He is also a core member and developer of Cloud-V platform.
- ATESOR: A Multi-Stage LLM-based Framework for Autonomous RISC-V Software Porting
- Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V
Ph.D. researcher in Electrical/Electronic Engineering with strong organizational skills and high motivation. Experienced in hardware/software co-design for embedded systems, including RISC-V SoC integration, custom accelerator interfaces, RTL development (SystemVerilog), FPGA prototyping, and embedded C. Solid background in Post-Quantum Cryptography implementations and optimization, with a performance-driven mindset and enthusiasm for new technical challenges.
- CIRCE: CROSS Integrated RISC-V Cryptographic Extension
- HORCRUX: a Post-Quantum Cryptography Instruction Set Extension
- CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON
- MAGIA-V: A Heterogeneous Zve32d+GEMM Tile for Emerging Mesh-of-Tiles Accelerators
- EMiX: Emulating Beyond Single-FPGA Limits
- C-Trace: An Open-Source RISC-V Trace Encoder and its Ecosystem
- Accelerating neural networks using SIMD ISA-Extension for RISC-V processor platforms: A complete toolflow
- CHERI RVY development support platform
- Custom RISC‑V SIMD Matrix Extensions with LLVM Support
Computer Architecture Researcher at Barcelona Supercomputing Center & PHD student at Universitat Politècnica de Catalunya.
- Towards Efficient Utilization of RISC-V Long Vector Register Files: A Characterization Study
- RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses
- Locality-Aware Sparse Matrix Multiplication on RISC-V RVV
- Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V
Andreas Mauderer received the diploma degree in computer science from the University of Karlsruhe, Germany, in 2009. He received his PhD in computer science at the University of Tuebingen in 2014. He is working at Bosch since 2009 in the business unit Mobility Electronics in the field of Virtual Prototyping and on-chip processors for automotive ASICs. Furthermore, he is active in various publicly funded projects regarding these topics.
- RISC-V Custom Instructions for Automotive Control and DSP Algorithms Compliant with ISO 26262
- RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions
- RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions
- RISC-V Hardware Accelerator for 2-D Discrete Cosine Transform
- Exploring AI Acceleration Paradigms for Automotive RISC-V Platforms
- CVA6 Optimization
- Coverage-Directed Smoke Regression Optimization via Greedy Set Cover for RISC-V Verification
- Reproducibility in open-source RISC-V HW flows
Anna Duque Antón received her Dipl.-Ing. degree in Electrical and Computer Engineering from the RPTU University Kaiserslautern-Landau in 2019. She is currently a Ph.D. candidate at the Electronic Design Automation group at the same university, working under supervision of Prof. Kunz and Prof. Stoffel. Her research interests include formal security verification, access control mechanisms and hardware trojan detection. For her work on SoC-wide security verification, she received the Intel Hardware Security Academic Award 2022.
- Exhaustive Security Verification of Access Control in Processors
Anne Merlande is a processor architect at STMicroelectronics in Grenoble, within the Computing and Compilers Center. As Senior Member of Technical Staff, her expertise field covers processor and system architecture, CPU microarchitecture and frontend design, low power and energy efficient subsystems, security and functional safety.
She graduated from Institut Supérieur d’Électronique de Paris in 1995 and joined STMicroelectronics in 1999, after four years as an ASIP designer at Matra. At STMicroelectronics, she has led the design of the ST200 processor families, acted as technical lead for ARM Cortex A subsystem frontend design, and led top level integration for automotive SoCs.
She currently works as Processor Architect on the STxP5 core family, with a particular focus on ultra low power operation, security, and functional safety.
- Ultra Low Power RISC-V core: Retention with Warm Restart Extension
- Towards Open User-Space Power-Management Communication Interfaces
Antti Nurmi received the B.Sc. degree in electronics and the M.Sc. degree in embedded systems from Tampere University, Tampere, Finland, in 2019 and 2022, respectively, where he is currently working toward the Ph.D. degree in computer engineering at the SoC Hub Research Centre. His research interests include predictable computer architecture, embedded real-time systems, RISC-V, and SoC design.
- Heterogeneous Interrupts for Ultra-Low Latency Embedded RISC-V Systems
- Maximizing Performance at Low Area Cost in RISC-V Processors Leveraging Fine-Grained Multithreading
- Window-Level Telemetry for Runtime Performance and Reliability Monitoring in RISC-V Systems
- REPTILES: Repeated tiles of Sargantana
- EMiX: Emulating Beyond Single-FPGA Limits
PhD student in machine learning security at CEA-Leti.
- An Open-Source Framework to Enable Float16 On-Device Training on RISC-V Single-Core
- Proposal of State Sensitive Counter (Sssscnt)
- Bicameral+: re-assessing split vector and scalar cache designs for increased efficiency
- A Doom Demo Journey: Tenstorrent's Ascalon CPU on Synopsys emulation and prototyping systems
Harvey Mudd College class of 2026 (B.S. in Computer Science)
- Integrated Development Environment Features for Unified Database Specification Development
- Integrated Development Environment Features for Unified Database Specification Development
- Fully Automated RISC-V ArchitecturalExploration with Chipyard and A-DECA
- Fully Automated RISC-V ArchitecturalExploration with Chipyard and A-DECA
- Bao-CHERI: A Pure-Capability RISC-V Hypervisor
Rafael Tordoya is a Research Associate at the Zurich University of Applied Sciences (ZHAW) in the fields of Artificial Intelligence (AI) and Embedded Systems. His research focuses on leveraging AI in resource-constrained environments, with particular emphasis on optimized AI inference, mathematical backends, and leveraging available hardware capabilities to enhance inference performance in embedded systems.
- RISC-V Packed-SIMD Acceleration for Quantized Edge-AI Inference on Space-Qualified Platforms
- Accelerating neural networks using SIMD ISA-Extension for RISC-V processor platforms: A complete toolflow
Carsten is Professor for Computer Architecture and Operating Systems at TU Munich's Heilbronn campus.
Carsten is also deputy spokesman of Gesellschaft für Informatik (GI)'s special interest group on "Ethics in Informatics", GI liaison lecturer at TU Munich, and member of the Zuse Society's board of directors.
From 2013 to 2019 he was elected member of GI's board of directors.
His research interests comprise high performance computer architectures, microprocessor architectures, multi- and many-core architectures as well as the adaptation of numerical simulation codes to these architectures, with a focus on RISC-V.
- LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions
Catalin Ciobanu has a MSc and PhD from Delft University of Technology, The Netherlands. He is currently Associate Professor at Transilvania University of Brasov, Romania and Senior Researcher at the National Institute for Research and Development in Microtechnologies - IMT Bucharest, Romania. His research interests include RISC-V processors, embedded systems, high performance computing, SIMD architectures, digital signal processing and reconfigurable hardware.
- Accelerating Matrix Operations with a Custom RISC‑V SIMD/Vector Extension and Automated LLVM Support
- Custom RISC‑V SIMD Matrix Extensions with LLVM Support
He is a researcher at Inria in the TIMA laboratory of the University Grenoble Alpes since November 2024, after spending 9 years at CEA. He’s got his computer sciences and electronics PhD from Université Paris 6 in 2015. He works on multi-core heterogeneous architectures, cache hierarchy and cache coherence.
- Flying V: A Radiation-Hardened L1 Data Cache for RISC-V Aerospace Processors
Sr. Staff Performance Engineer, Infrastructure - Tenstorrent
- From Profiling to Performance: Optimizing Small Language Models on RISC‑V Architectures
- Why Edges Matter: A Case Study on Performance Improvements for OpenBLAS GEMM on RISC-V
Christian Wenzel-Benner completed a dual engineering degree at the former DaimlerChrysler AG / University of Cooperative Education in Stuttgart. After several years of ECU development at Bosch, he took on tasks as project manager and later as a specialist for embedded systems & security at ITK Engineering.
During this time, he earned a Master of Science at Brunel University West London and led an embedded systems benchmarking team for the international NIST SHA-3 standardization competition.
Since the end of 2015, he has been responsible for customer-specific solutions and training at GLIWA and works as a part time university lecturer.
- RISC-V vs. ARM in an Embedded Real-Time System
With 20 years of experience in Electronic Design Automation (EDA), I began my journey with a PhD in microelectronics from Sorbonne University. In 2009, I co-founded Flexras Technologies, a startup specializing in FPGA prototyping tools, which was acquired by Mentor Graphics (now Siemens EDA) in 2015. There, I served as Chief Software Architect, leading global R&D teams and helping evolve our technology into a widely adopted product.In 2022, I co-founded a new venture: keplertech.io, an EDA startup built on the belief that Open Source can unlock innovation in one of the most closed and complex industries: integrated circuits and the tools used to design them. In a space dominated by a handful of major players, we aim to create meaningful opportunities for smaller, agile actors to thrive. I’m passionate about building complex systems from scratch and bringing ideas to life in the real world.
- kepler-formal: Open Logic Equivalence Checking for RISC-V CI Workflows
- RISC-V Tournament: Battle of HDLs
- Accelerating the Poseidon2 S-box in a RISC-V SoC with a 4×4 CGRA
- Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V
- Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior
- 1W Envelope: Area-Energy Trade-offs of Scalable RISC-V Systolic Arrays in Sky130
Embedded systems engineer specializing in embedded AI deployment and optimization. My work focuses on adapting machine learning models to resource-constrained hardware and improving performance through efficient compilation and system-level optimization
- Toward an open-source platform for multi-lead Embedded ECG Processing on RISC-V processors
Dave Cremins is a Principal Cloud Software Engineer at OPENCHIP, where he specializes in designing and building advanced cloud‑native systems at scale. With deep expertise in distributed architectures, automation, and infrastructure engineering, Dave plays a key role in shaping technical strategy and delivering high‑impact engineering solutions across the organization.
- Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System
- Exploring AI Acceleration Paradigms for Automotive RISC-V Platforms
- Hardware support in RISC-V for ternary LLMs
David is a software engineer and system architect working in correctness - and latency-critical systems. His background spans academic research in parallel computing, low-level programming in RISC-V and MIPS assembly and embedded C and Rust, and active involvement in both the Rust and RISC-V communities as a speaker and mentor. He is a member of the Safety Critical Rust Consortium.
- Rust on RISC-V: Alignment and Friction at the Hardware-Software Boundary
- The ISOLDE Space Demonstrator: a RISC-V Ecosystem for Low-Power On-board Inference
- RISC-V Address-Encoded Byte Order Extension
- A RISC-V Accelerator for Convex Optimisation
- From Profiling to Performance: Optimizing Small Language Models on RISC‑V Architectures
- A Doom Demo Journey: Tenstorrent's Ascalon CPU on Synopsys emulation and prototyping systems
Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL GmbH, providing strategic R&D for semiconductor companies. He chairs the RISC-V Applications & Tools Committee, serves on the RISC-V Board of Directors, and is Vice-Chair of the Technical Steering Committee, where he champions software ecosystem growth and standards alignment, including efforts to publish RISC-V under ISO.
He instigated the standards-development matrix operations and AI/ML, serving as principal editor of the Integrated Matrix Extension and as the Vice-chair of the Attached Matrix TG.
- All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom
- Accelerating Myers’ Bit-Vector Alignment With RISC-V Vector Intrinsics
Elisabetta Boella received her M.Sc. degree in Energy and Nuclear Engineering in 2009 from Politecnico di Torino (Turin, Italy) and her Ph.D. in Computational Plasma Physics in 2014 from the same institution. She currently works as HPC product specialist at E4 Computer Engineering (Scandiano, Italy), where she leads the company effort in several European projects, including MaX, SPACE and EoCoE. Her research interests include numerical modelling, parallel programming, and co-design practices. She has a long-time experience in the development and optimisation of parallel codes using the Message Passing Interface protocol. She is one of the main developers of the massively parallel plasma code ECsim. She also has extensive experience in Graphical Processing Unit (GPU) programming and off-loading of legacy codes to GPU.
- Evaluating Tenstorrent RISC-V Accelerators for High Performance Scientific Computing
Computer Science and Engineering graduate and Master’s student in HPC, both at Universitat Politècnica de Catalunya. Working as a Junior Research Engineer at the Barcelona Supercomputing Center, developing solutions to advance verification of RISC-V designs.
- The RISC-V test platform; an extension of the omnipresent RISC-V test environments
- ALPES: Advanced Low-Power Edge Skeleton
- ML-KEM on a 22 nm ASIC: Protected, Unprotected, and Hardware-Accelerated Implementations
- Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V Secure Elements
- The ISOLDE Space Demonstrator: a RISC-V Ecosystem for Low-Power On-board Inference
- Monte Cimone v3: Where RISC-V Stands in High-Performance Computing
- AME-PIM: Breaking the Memory Wall with RISC-V Matrix Extensions and HBM-PIM
- Towards Open User-Space Power-Management Communication Interfaces
- CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON
- CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems
Professor Eugenio Villar obtained his PhD in Electronics many years ago. Since 2002, he has been a Professor in the TEISA Department at the University of Cantabria, where he is responsible for the Embedded Systems Design (HW/SW) area within the Microelectronics Engineering Group. His research has always focused on the specification and design of electronic systems. He is currently working on the use of Artificial Intelligence in the co-design and simulation of model-driven systems. Professor Villar has authored over 100 papers published in national and international conferences and journals. He has participated in electronic systems design projects under European (FP and Horizon Europe) and transnational programs, such as Medea-Catrene, Artemis, ECSEL, KDT, and Chips JU. He is the University of Cantabria's representative in Chips JU and the Director of the Cantabria Chip Chair.
- Spike-RTL: Two technologies for fast and accurate SW-RTL co-simulation
- Advanced Interrupt Latency Optimization Approaches in RISC‑V Interrupt Architectures
- UCAgent: An End-to-End Agent for Block-Level Functional Verification
Perf & ASM nerd, practical troublemaker
Care about clean specs, clean mandates, HPC, IEEE754 & the BLAS.
- Towards a Modern Packed SIMD Architecture for RISC-V: Learning from Production Of ET-SIMD
- High-Performance CRC/EC Acceleration for RISC-V Server Storage via Novel ISA Extensions
As a senior Engineer in the Firmware Team at Alibaba Damo Academy, Esther specializes in system and power management software standards, with a focus on architecting and developing power management frameworks across diverse operating systems (OS) and firmware technologies. Her work drives innovation in energy-efficient computing and system optimization, aligning with industry-leading specifications to enhance hardware-software synergy.
- Proposal of State Sensitive Counter (Sssscnt)
Flavia Guella received the B.S. and M.S. (both with summa cum laude) in Electronics Engineering from Università degli Studi di Palermo in 2020, and Politecnico di Torino in 2023, respectively. She is currently pursuing the Ph.D. program in Electronics and Communications Engineering at Politecnico di Torino, under the supervision of Prof. Maurizio Martina and Prof. Guido Masera. Her research interests include RISC-V based in-cache computing, and co-design methodologies for the efficient deployment of neural networks on low-power systems.
- ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V
- Loom: An Open-Source Toolchain for Automatic FPGA Emulation of Simulation-Grade SystemVerilog
Gianmarco Fortunelli is an Electronic Engineering student at Politecnico di Torino and EURECOM, focusing on embedded systems, hardware security, and computer architecture. His work spans RISC-V security research and digital design, with a strong interest in efficient and secure computing.
- From Leakage to Exploitability: Empirical Study of Cross-Process L1 Prime+Probe on RISC-V
- Integrating AES Cryptographic Acceleration with RISC-V Cryptography Extensions in 32-bit processors
Frédéric Desbiens manages the Embedded and IoT programs at the Eclipse Foundation, Europe's largest open-source organisation. In this role, he helps the community drive innovation at the intersection of devices, software, and open collaboration. A passionate advocate for open source, Frédéric works with developers, companies, and researchers to advance the Internet of Things and edge computing. He is also the project lead for Eclipse ThreadX, the first open source real-time operating system (RTOS) certified for safety-critical applications.
Before joining the Eclipse Foundation, he held various technical and leadership roles at Pivotal, Cisco, and Oracle. Frédéric holds an MBA in Electronic Commerce, a BASc in Computer Science, and a BEd from Université Laval in Québec City, Canada.
He is the author of Building Enterprise IoT Solutions using Eclipse IoT Technologies: An Open-Source Approach to Edge Computing (Apress, 2022).
- Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V
- A Proof-of-Concept RISC-V with 128-bit Extension
Frederik Haxel is a researcher at the FZI Research Center for Information Technology. His research interests include developing tools and methods to accelerate the design of safe and efficient RISC-V systems.
- Generator-Driven Functional Safety for RISC-V SoCs with Formal Assurance
- From Fragmentation to Systematization: A Standardized Quality Selection and Reconstruction Approach for RISC-V Courses
Gabriele Ceccolini received his Master's degree in Computer Engineering from the University of Bologna in March 2026. He previously obtained his Bachelor's degree from the same institution in 2023. Since May 2025, Gabriele has been collaborating with CINECA, focusing on the optimization of CFD algorithms on RISC-V platforms.
- Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions
- Priority-Aware Scheduling of Multi-Model, Multi-Precision DNN Inference on Multi-Cores RISC-V
Germano Brunacci earned his degree in Electronic Engineering from the University of Ferrara, Italy, in 2000. He began his career as a firmware developer, contributing to projects across the automotive, medical, and telecommunications sectors from 2000 to 2010.
In 2010 he joined FIAMM, and later MIDAC, where he served as Firmware Lead Engineer, focusing on Battery Management Systems (BMS) for advanced battery technologies. From 2018 to 2023, he was BMS Component Responsible for 800 V Battery Electric Vehicles (BEVs) at MASERATI, playing a key role in high-voltage system development.
Since 2023, Germano has been part of GLIWA, where he is involved in development of customer specific solutions, as well as training and coaching activities in the field of real-time embedded systems.
- RISC-V vs. ARM in an Embedded Real-Time System
Giacomo Valente received the M.S. degree in Electronic Engineering in 2014 and the Ph.D. degree in Information and Communication Technology in 2018 from the University of L'Aquila.
His primary research activities are in electronic design automation, reconfigurable computer architectures, and real-time systems.
Since 2022, he has been an Assistant Professor in Computer Architecture at the Department of Information Engineering, Computer Science, and Mathematics of the University of L’Aquila.
He is the author or co-author of more than 40 research articles in peer-reviewed journals and international conference proceedings. He has been also a reviewer and member of several TPCs related to his research topics
- A Lightweight Multi-Context Architecture for Mixed-Criticality Systems on RISC-V Processors
Driven by complex problem-solving, I am a researcher at VORTEX-CoLab specialising in the safety, cybersecurity, and formal verification of real-time embedded systems. My work focuses on bridging the gap between hardware and software to build dependable, high-performance architectures. With an academic and professional background spanning Brazil, the Netherlands, and Portugal, I have contributed to top-tier research in cyber-physical systems, with publications in premier venues like RTSS and DSN. Beyond research, I also have experience teaching undergraduate and master’s level courses in Assembly, C, and NuSMV model checking. I am currently focusing on identifying industry-ready applications for applied research and cross-border collaboration.
- Hardware-Synthesized Monitor-Actuator Design Patterns: a Proof-of-Concept Application
Research Engineer at CEA-List, I hold a Master’s degree in Cybersecurity Engineering from Politecnico di Torino. I am passionate about hardware and software security, with a strong focus on fault injection and microarchitectural security.
- InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment
- STRiVe-VP: LLVM-based performance simulator for RISC-V processors
- STRiVe-VP: LLVM-based performance simulator for RISC-V processors
- Cycle-Accurate IOPMP Reference Model with Configurable Interfaces, Integration Tests, and a CVA6 SoC Implementation
- PicoNut/RISC-V: One Educational Platform for Hardware and Software Development
Guodong Xu is Director of Software Engineering at RISCstar Solutions, with over 20 years of Linux kernel development experience. Previously at Motorola (Mobile phone low-level software) and Linaro (Sr. Tech Lead 10+ years), he now focuses on RISC-V upstream kernel enablement and BSP development. He is an active contributor to the mainline Linux kernel for RISC-V, including SpacemiT K1/K3 SoC support and RVA23 profile extensions.
- RVA23 Profile Support in Linux Kernel: From Extension Definitions to Userspace Export
A Linux kernel developer focuses on the CPU subsystem, including virtualization, IOMMU, PCIe, Heterogeneous Programming, and RV64ILP32.
Staff Engineer, Alibaba Damo Academy
- SMSIC: Software-Interrupt MSI Controller for RISCV AIA in Large-Scale NoC Systems
- Running ILP32 on RVA(22/23)S64: AI Glasses Product Demo
- Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V Secure Elements
- Wolvrix: A SystemVerilog-Native Graph Infrastructure for RTL Research
- Enabling Confidential Computing on RISC-V: An Open-Source MPT Implementation
Harry has worked in software for 15+ years, with experience in real-time audio processing and open-source projects like OpenAV productions, to datacenter networking SIMD optimizations for DPDK, and now works with Openchip to advance the software ecosystem of Risc-V Vector instructions. As a data-driven technologies he's passionate about tooling to help achieve success, and has presented at many conferences on the topic. He holds 4 patents in the datacenter domain, and many open source contributions.
In his spare time Harry can be found playing badminton or sim-racing, with 24 hour races being the favorite!
- Using RISC-V E-Trace for effective insights for RISC-V Vector Optimizations
- Simulation-Driven Framework for Custom RISC-V HW/SW Co-Development and Debug
Holger Blasum is research engineer at SYSGO GmbH, with interests in architecture, design, implementation and verification (including formal methods) of safe and secure systems.
- Bringing Cloud-Connected Automotive Workloads to RISC-V: A CVA6-Based FPGA Case Study
Hongbin Zhang is a postdoctoral researcher at the Institute of Software, Chinese Academy of Sciences (ISCAS). He received his Ph.D. degree from the University of Chinese Academy of Sciences. His research focuses on AI system software and compiler technology. He leads the RuyiAI system software team at ISCAS. He launched the Buddy Compiler community and has served as a community mentor for the LFX RISC-V Mentorship and OSPP open-source programs. He is a member of the Technical Steering Committee (TSC) of RISC-V International and serves on the Governing Board of CHIPS Alliance.
- End-to-End AI Compilation for RISC-V: A Multi-Level Optimization Approach
- A Decoupled IOPMP Architecture: Open-Source Implementation with Distributed Bridges for Multi-Master SoCs
Co-founder & CTO of Terapines Technology. More than 15 years compiler design and development experience in Andes, S3 Graphics, Imagination and Terapines. Specialized in CPU, GPU, GPGPU, AI compilers based on MLIR, LLVM and GCC.
- End-to-End ML Graph Compiler Fused with Triton Kernel Compiler for RISC-V
- Cincoranch: A Heterogeneous Multi-Microarchitecture RISC-V Test Chip – Silicon Bring-Up
Iacopo Colonnelli is an Assistant Professor in the Department of Computer Science at the University
of Turin. He serves on the Technical Committee of the Common Workflow Language (CWL), and is a founding coordinator of the CWL4HPC working group. He has co-authored over 40 peer-reviewed publications in national and international journals and conferences, and has contributed to more than 10 funded research projects. He is currently the local Principal Investigator for the DARE European project (total budget: e240M). His research interests include workflow modeling and management in heterogeneous distributed architectures, high-performance computing and I/O, distributed confidential computing, and large-scale data science.
- Heuristic-free system call interception on RISC-V
- ANSSI IPECC-Accelerated ECC on CVA6 RISC-V SoC: Integration and Benchmarking
Ihsane Tahir received a M.S. degree in embedded systems from Grenoble INP - Esisar, Valence, France, in 2020. She subsequently joined CEA LIST as a research engineer. She then joined the OpenHW Foundation in 2026 as a hardware verification engineer. Her works include functional verification, FPGA prototyping and digital design.
- Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores
Ilya Tuzov received the Ph.D. degree in computer science from the Universitat Politècnica de València (UPV), Valencia, Spain, in 2020. He is currently working at UPV as a researcher. His current research interest include fault-tolerant embedded systems, reconfigurable computing, automated verification and dependability benchmarking.
- Pre-silicon Robustness Assessment of RISC-V Cores using bit-accurate FPGA fault injection
- An Embedded RISC-V Vector Extension for Edge-Oriented Acceleration
- Integrated Development Environment Features for Unified Database Specification Development
- Integrated Development Environment Features for Unified Database Specification Development
- Compiler-Aided Autovectorization of PQC on RISC-V Vector Extensions
- Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V Secure Elements
- LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions
Jan Zielasko is a PhD student at the University of Bremen and a researcher at the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). His research focuses on Virtual Prototype-driven tracing, analysis, verification and hardware optimization.
- RETrace EX: Interactive Trace Analysis Framework for RISC-V Hardware Optimization
- Low-power Floating Point Unit for RISC-V Processors using FPHUB format
- Implementation of Open RAN software in a RISC-V platform
- ALPES: Advanced Low-Power Edge Skeleton
Jeremy Bennett is Chief Executive of Embecosm, an international open source consultancy specializing in compiler tool chains and AI tooling. He is a former academic and author of the standard text book "Introduction to Compiling Techniques: A first course using ANSI C, Lex and YACC" (McGraw-Hill 1990, 1995, 2003). Dr Bennett holds an MA and PhD from Cambridge University. He is aFellow of the British Computer Society, Fellow of the Royal Society of Arts, Member of the IET and a Chartered Engineer.
- AI inference on bare-metal RISC-V Microcontrollers: A comparison of ExecuTorch and IREE/MLIR
Jérôme Quévremont graduated in telecommunications and electronics in 1995 (Télécom Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology cortAIx Labs as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security.
- Fault-Tolerant Open-Source CVA6 Core for Automotive, Aeronautics and Space
- RISC-V Vector 1.0 code Generation in MLIR-xDSL
Wang Jingwei is an engineer at the Institute of Software, Chinese Academy of Sciences and a member of the openEuler Technical Committee. He is a RISC-V advocate focused on building the RISC-V software ecosystem based on openEuler and related Linux distributions.
- openEuler for RVA23: Building a RISC-V Server OS with Ecosystem Partners
Currently pursuing a PhD in Microelectronics with a focus on digital circuits for edge AI. I work on digital hardware for edge implementations of Transformer models (aka LLMs), with a particular emphasis on attention mechanisms—especially dot-product attention—and on the design of ASICs that implement this computation with optimized power and performance. A goal-oriented and curious engineer, committed to continuous learning and collaboration.
- Co-optimizing Custom Instructions RISC-V and LLM Specialized Accelerator for Attention-Based Edge AI
Johannes Hofmann is a graduate student pursuing a Master of Science (MSc) in Applied Research in Engineering Sciences at the Technical University of Applied Sciences Augsburg. His research interests include embedded systems and debugging methodologies, RISC-V hardware development, and embedded AI.
- PicoNut/RISC-V: One Educational Platform for Hardware and Software Development
- RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions
- wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture
Jonathan Woodruff is a Associate Research Professor with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.
- RV64Y Temporal Safety Exploration
Jon has 25 years of experience in the semiconductor and software industries and has been involved with RISC-V since 2019. He is currently product manager for RISC-V at Canonical driving product development to strengthen the RISC-V ecosystem.
- Building the software ecosystem for a RISC-V datacenter
- RISC-V Address-Encoded Byte Order Extension
- From Profiling to Performance: Optimizing Small Language Models on RISC‑V Architectures
- Memory Protection for MMU-less RISC-V: Current Status of SPMP and vSPMP
Jose Sanchez-Yun received his B.S. degree in Computer Engineering from the University of Cordoba in 2022, and his M.S. degree in Software Engineering and Artificial Intelligence from the University of Malaga in 2024. He is currently pursuing a Ph.D. degree at the University of Malaga. His research interests include the development of RISC-V ISA extensions for neural network optimization and the vectorization of time series analysis algorithms.
- ONNX Runtime Convolution Acceleration on RISC-V via RVV
I am a current PhD student at TUWien. Interested in embedded system design and vector processing.
- Evaluating the Impact of Vector Co-Processors on Memory Hierarchies through Hybrid Simulation
- CREATOR: A RISC-V web simulator based on Sail specification language
- Tightly Coupled Near-Memory Matrix Unit for RISC-V Embedded Computing
- Benchmarking the Vortex RISC-V GPU for Sparse Workloads
Research Assistant at FZI Forschungszentrum Informatik
- Open E-Trace Infrastructure: Tooling for Evaluation, Analysis, and Research
- A Hardware-Software Heterogeneous Framework for Agile RISC-V Verification with Model-Based Processor Fuzzing
- UCAgent: An End-to-End Agent for Block-Level Functional Verification
Before working in the automotive microcontroller area Kajetan Nürnberger has worked in the domain of safety critical aerospace software in an industrial and university environment. He is familiar with various CPU architectures and focused on the HW SW interface. Within Infineon he has contributed to the definition of different automotive controllers with respect to compute architecture SW and tooling.
- Code size reduction by advanced near addressing modes
- Beyond Bare-Metal: A Lightweight Cross-Privilege Framework for RISC-V RTL Security Evaluation
- Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior
- LLM-Driven Multi-Agent Framework for Automated RISC-V Verification Stimulus Generation
- Architectural Scalability Trade-Offs in an RISC-V Vector Processor for Communication Kernels
- RISC-V Instruction-Subset Processors for Extreme Edge Machine Learning.
- LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions
BS/MS Student from Rice University. Background in computer architecture and hardware infrastructure.
- STARBUG: RISC-V Hint Instructions for Lightweight VLIW Execution on Embedded DSP Workloads
- A Lightweight Multi-Context Architecture for Mixed-Criticality Systems on RISC-V Processors
Dr. Leonidas Kosmidis is the Group Leader of the Hardware Dependability for Embedded Systems (HADES) group at the Barcelona Supercomputing Center (BSC) and Faculty member at the Universitat Politècnica de Catalunya (UPC). His research interests include hardware and software design for high performance safe and secure embedded systems, and particularly GPUs. He was the recipient of the RISC-V Educator of the Year Award in 2019 and he is involved in several standardisation efforts around RISC-V, hardware design and GPUs for safety critical systems.
- PQC4eMRTD: Post Quantum Cryptography for Resource Constrained RISC-V Systems
- Fully Automated RISC-V ArchitecturalExploration with Chipyard and A-DECA
- REPTILES: Repeated tiles of Sargantana
I am a PhD Student at the Institute of Information Security at Graz University of Technology.
My research focuses on system security, from the perspective of both hardware/software co-design, as well as improving the security for complex software systems.
I am strongly involved in teaching and have, among other things, helped create a new system security course from scratch.
- Integrating RISC-V into University Education: A Full-Stack Approach to Teaching System Security
- MAGIA-V: A Heterogeneous Zve32d+GEMM Tile for Emerging Mesh-of-Tiles Accelerators
- RIVIERA: A Programmable RISC V Edge Architecture for NFC Signal Processing
- Integrated Development Environment Features for Unified Database Specification Development
- Integrated Development Environment Features for Unified Database Specification Development
- TOXOS: A RISC-V Coprocessor for Non Linear Function Acceleration
Luis Waucquez received his BSc and MSc degrees in Electronic Engineering from Universidad Politécnica de Madrid (UPM).
He is currently pursuing a Ph.D. degree at the Center of Industrial Electronics. His current research interest are open computer architectures and fault-tolerant systems
- Hardware Acceleration Island for Safety-Critical Applications based on RISC-V
- Towards a Secure RISC-V Platform: The Environment Around the CVA6-Core
- Runtime Reconfiguration of Decoders in Minimal-area RISC-V Cores
- Integrated Development Environment Features for Unified Database Specification Development
- Integrated Development Environment Features for Unified Database Specification Development
Manfred Schlägl is a PhD student at the Institute for Complex Systems, JKU Linz, under Prof. Daniel Große. For 15 years, he worked in industry, focusing mainly on low-level firmware and operating systems for industrial embedded systems. In 2021, he left the industry to resume his studies, completed his Master's degree in Computer Science in 2023, and started his PhD immediately afterward. His main research interests are hardware/software co-simulation using virtual prototypes and hardware verification. He is also deeply interested in operating systems, hardware platforms, and computer architectures, especially RISC-V.
- Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V
- Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior
Dr. Manolis Marazakis (Ph.D. in Computer Science, University of Crete, Greece - 2000) is a Principal Staff Research Scientist at the Institute of Computer science, FORTH. His research interests are in architectures and efficient systems software, mainly resource management and storage I/O middleware, for high-performance servers in data center environments. He has contributed to the design, implementation and performance analysis of several system prototypes for HPC, data analytics, multi-tenant workloads, and the convergence of HPC and Cloud infrastructures. He has been FORTH’s technical lead for system software and performance evaluation for European digital sovereignty-focused research and innovation projects, for both HPC and Cloud infrastructure technologies. He is a Senior Member of ACM (since 2018) and IEEE (since 2021), and a Member of the USENIX Technical Society.
- Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform
MANUEL RODRÍGUEZ earned his M.Sc. degree in Electronic and Computer Engineering at the University of Minho, Portugal, with a focus on Embedded Systems and Micro/Nanotechnologies. He is currently pursuing a Ph.D. in Electronics and Computer Engineering at the same institution, focusing on the development of novel RISC-V ISA primitives for secure virtualization in mixed-criticality systems. Throughout his career, he has contributed to the RISC-V ecosystem providing PoC artifacts for ongoing specifications, mostly in the hardware area. His research interests encompass computer architecture, RISC-V, hardware design, embedded virtualization, and safety-critical and mixed-criticality systems.
- Practical Implications of SPMP-Based Virtualization in RISC-V
- Holographic Execution: A Hyperdimensional Computing Approach for Robust RISC-V Instruction Decoding
In 2024 Marcel Ziswiler joined Codethink as a software engineer. Before, he worked
more than 13 years at Toradex spearheading their Embedded Linux adoption. His
introduction of an upstream first policy led to being a top 10 U-Boot as well as Linux
kernel Arm SoC contributor. He has broad experience in designing real-time and
mobile applications for industrial systems. He holds a Certificate in Embedded Systems
Technologies from the UCI and a CS Master from the ETHZ. He spoke at several
international conferences including all ELCs starting 2019 and FOSDEMs starting 2025.
- Deep Dive into Upstream RISC-V Boot Chain
Marco Bertuletti received the B.Sc. and M.Sc. degree in Electrical Engineering in Politecnico di Milano, Milano, Italy. He is currently pursuing his Ph.D. at ETH, Zurich, Switzerland, in the Integrated Systems Laboratory (IIS). His main interests are in the design of multi and many-core clusters of RISC-V processors for next-generation telecommunications.
- The Next Generation RISC-V SoCs for Space Communications
- Energy-Efficiency Optimization of a RISC-V Floating-Point Unit for HPC-Oriented Architectures
- Heuristic-free system call interception on RISC-V
- On-Device Context-Informed Incremental Learning for Myoelectric Control on RISC-V-based Wearable Platform
- RISC-V POWERED QUANTUM SENSOR
- RISC-V Edge Processing for Real-Time Unobtrusive Driver State Monitoring on the Automotive SoC
He received the Diploma and PhD degree in electrical engineering from the Technische Universität Kaiserslautern, Germany, in 2011 and 2017, respectively. From 2011 to 2017 he was a researcher at the Microelectronic Systems Design Research Group of RPTU Kaiserslautern. Since 2017 he is with the Fraunhofer Institute for Experimental Software Engineering in Kaiserslautern as Expert Engineer for virtual hardware engineering. In 2018, he received the EDAA Outstanding Dissertation Award for this work. At Fraunhofer IESE in Kaiserslautern, he has been leading many research and industrial projects in the area of embedded systems since 2017 and has published more than 100 papers in relevant journals and conference proceedings. Since 2023, he is professor at the University of Würzburg. Matthias Jung's scientific focus is on embedded and autonomous systems, especially with a focus on memory architectures, functional safety, and virtual product development of embedded systems through virtual platforms and simulations.
- RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions
- wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture
Mattia Orlandi received his M.Sc. degree in Artificial Intelligence from the University of Bologna, Italy, in 2022. He is currently pursuing his Ph.D. in Data Science and Computation under the supervision of Prof. S. Benatti at the Energy-Efficient Embedded Systems Laboratory (EEES Lab), DEI Department, University of Bologna. His research activities involve bio-signal processing with machine learning on low-power computing platforms. He is investigating how to develop advanced human-machine interfaces based on EMG.
- On-Device Context-Informed Incremental Learning for Myoelectric Control on RISC-V-based Wearable Platform
Mattia Paladino is a Project Manager at E4 Computer Engineering. He is currently involved in several European projects within the HPC sector, focusing on areas such as co-design for optimizing ML applications, green computing, and RISC-V. He holds a master's degree in Nuclear and Subnuclear Physics from the University of Bologna.
- The ISOLDE Space Demonstrator: a RISC-V Ecosystem for Low-Power On-board Inference
RISC-V Engineer, mainly focus on Go compiler/toolchains developement
- Improving ChaCha20 by RISC-V Vector Extension: Design and Engineering Implementation
Michael Rogenmoser received his BSc and MSc degrees from ETH Zurich in 2020 and 2021, respectively. In 2021, he joined the Integrated Systems Laboratory of ETH Zurich as a PhD candidate under the supervision of Prof. Dr. Luca Benini. His research interests include fault-tolerant architectures for space, multicore processors, and reliability in systems-on-chip (SoCs).
- Who Checks the Checker? End-to-End Architectural SEU Tolerance for RISC-V Microcontroller Protection
- RVEdge-Vision: A Fully Open, Ultra-Efficient On-Device AI Platform for Smart Eyewear
- An Efficient Approach to Apply the RISC-V Sail Model to Chip Verification
- Sail-RISCV-WASM A Browser-Native RISC-V Toolchain and Debugging Workbench
Mihailo Obradovic is an electronics engineer at CERN. His current work focuses on co-simulation methodologies for hardware modelling, with a specific interest in evaluating RISC-V SoC integration into detector readout systems and investigating how open-standard processor architectures can satisfy the performance and reliability constraints typical of high-energy physics applications. Mihailo holds a Bachelor's degree in electronics engineering from the University of Belgrade.
- Virtual Prototyping of Pixel Detector Architecture via Co-Simulation of PixESL and GVSoC
I'm a doctoral researcher at Tampere University. My research focus is hardware security and specifically, researching CPU side-channel attacks and defenses. Previously, I worked on hardware design, verification and physical implementation for 2 System-on-Chips at Tampere University, and now I'm starting my doctoral research.
- RISCY Prefetchers
Moritz Waser is a PhD student in the Secure Systems (SESYS) group at ISEC, Graz University of Technology.
His research interests include memory safety, confidential computing, capability systems and hardware security.
- Integrating RISC-V into University Education: A Full-Stack Approach to Teaching System Security
- CAGE-V: Confidential Computing Architecture supporting Guest Enclaves for RISC-V
Nathan Egge is a Staff Software Engineer at Google working on the native tools and libraries used to build AOSP and Android applications, including the C/C++ and Rust toolchains. He serves as co-chair of the Technical Steering Committee in RISE and previously as the chair of the System Libraries WG. Nathan received the RISC-V Board of Directors Software Leadership award in 2024 for contributions to RISC-V industry adoption.
- The RISE Project: Advancing the RISC-V Software Ecosystem
Niccolò Lentini is a PhD student in Computer and Cybersecurity Engineering at Politecnico di Torino, Italy. His research focuses on hardware and system security, with particular emphasis on fault injection attacks, the resilience of RISC-V systems, and post-quantum security. He received his MSc in Cybersecurity Engineering from Politecnico di Torino, where his Master’s thesis focused on securing avionic embedded systems using hardware-assisted security mechanisms. His current research investigates methodologies and tools for evaluating the security of computing platforms against physical attacks.
- InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment
Sr. Engineer at Tenstorrent.
Previously open sourced Riescue, a direct test framework and compliance test generator. I'm using this experience and leveraging AI to create RISC-V stimulus
- LLM-Driven Multi-Agent Framework for Automated RISC-V Verification Stimulus Generation
Tenstorrent systems software developer
- Unleashing the Penguin: Programmable Device Model for verifying RISC-V IOMMU using Linux
- LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions
Recently graduated from Harvey Mudd with a CS degree. I spent the last year building a VS Code extension for the RISC-V Unified Database as part of our Clinic program—think grammar design, validators, and making architectural specs actually usable for developers. Interested in the intersection of tooling, specification, and how good IDE support can make a real difference.
- Integrated Development Environment Features for Unified Database Specification Development
- Integrated Development Environment Features for Unified Database Specification Development
Noam Cohen is the Co-Founder and CTO of keplertech.io. Throughout his
corporate career, he led R&D teams at SNPS and Siemens, dedicated to compiler
development for hardware prototyping and emulation, with a focus on optimizing
solutions to NP-hard problems such as partitioning, placement, and routing, and
with an emphasis on high performance computing. After 10 years with the EDA
industry leaders, he co-founded keplertech.io with the aim of introducing innovation
in both technology and user experience to hardware design software tools.
- kepler-formal: Open Logic Equivalence Checking for RISC-V CI Workflows
- RVV Tips & Tricks
- Heuristic-free system call interception on RISC-V
- Unlocking High-Performance AVX2 Emulation with RVV 1.0
Pasquale Davide Schiavone (Davide) is a Scientist at the Swiss Federal Institute of Technology Lausanne (EPFL) and Director of Engineering of the OpenHW Group. He was previously working in the ESL lab at EPFL as a PostDoc from 2022 to 2025. He obtained the Ph.D. title at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group in 2020 and the BSc. and MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016, respectively. His main activities are the RISC-V CPU design and low-power energy-efficient heterogeneous computer architectures for smart embedded systems and edge-computing devices.
Since the Ph.D., he delivers training workshops to companies and universities.
A list of his publications is available at https://scholar.google.ch/citations?user=mfZQ9zUAAAAJ&hl=en
My GitHub: https://github.com/davideschiavone
- X‑HEEP: An Open Hardware Platform Enabling Research and Education in RISC‑V SoC Design
Dr. Ku works for Andes Technology Corporation and is enthusiastic about processor and platform security. He currently serves the IOPMP TG as the chair (Jul.2022 - now) and the TEE TG as the vice-chair (Apr.2021 - Mar.2022), and has presented several times in RISC-V Summits.
With 20+ years of experience in the semiconductor industry, he has participated in over a dozen ASIC projects, particularly in SoC design, optimization, and security.
He majored in Computer Engineering, was granted a Ph.D., and became an adjunct associate professor at National Tseng Hua University, focusing on processor security, parallel algorithms, and algorithm analysis.
- A Low Latency Real-Time RISC-V MCU for TEE
Having started personal journey in Uzbekistan, and professional career in Delft, Peter delved into SW engineering (at TU/d) towards streaming and multimedia systems for CE (architecture & infrastructure group at Philips Research, NatLab). He developed a passion for fun PLs such as Icon, Scheme and Julia, which he applied in projects such a simulation modeling, virtual prototype environments and a joint project on SDR with Nokia. Dataflow compiler & middleware project got him further into the DSP algorithms and radio & radar transceivers - focus of the work at NXP Semiconductors for more than 10 years, resulting in IPs for, e.g., SAF85xx made with Julia and RoadLink SAF5400 made with SystemC and HLS. At IMEC since 2022, he focuses on SW/HW interfaces, simulation infra and on micro-arch modeling for RISC-V and CMOS2.0. Since 2019 he consults in efficient networking stack simulation, automation and nano-kernels such as Zephyr.
- Reproducibility in open-source RISC-V HW flows
- Priority-Aware Scheduling of Multi-Model, Multi-Precision DNN Inference on Multi-Cores RISC-V
Ms. Prachi Pandey is a Senior Compiler Engineer at C-DAC, where she works on MLIR/LLVM-based compiler development for indigenous processors, GPUs, and AI accelerators. She has nearly two decades of experience in HPC, parallel programming, compilers, and runtime systems. Her research interests include compiler optimization techniques, automatic parallelizing compilers, performance portability for heterogeneous architectures, and parallelization strategies for HPC and AI workloads.
- CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures
- Vishwa: A Scalable RISC-V Based GPGPU
- CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures
- Vishwa: A Scalable RISC-V Based GPGPU
I am a PhD student in Chamers University of Technology and currently in Barcelona Supercomputing Center. My research is about optimizating performance of memory system for CPU and GPU workloads. I am familiar with CPU/GPU archiecture and also gem5 and accel-sim simulators.
- QUICK: QEMU Internal Checkpointing for Gem5
Qiu Jing is a CPU design engineer at Alibaba DAMO Academy, where he has been involved in the design of multiple XuanTie RISC-V processors. He served as the Acting Chair during the inception phase of the RISC-V AME (Attached Matrix Extension) Task Group, and has been actively contributing to the TG's discussions since its establishment. His work focuses on bridging the gap between AI workload requirements and RISC-V ISA design, with particular emphasis on vector/matrix extension architecture and its hardware implementation.
- A Holistic Approach to Attached Matrix Extension on RISC-V From ISA to Software Stack
- LLM-Driven Multi-Agent Framework for Automated RISC-V Verification Stimulus Generation
- AI-Driven Testlist Generation for RISC-V Core Verification
- Coverage-Directed Smoke Regression Optimization via Greedy Set Cover for RISC-V Verification
Rae Parnmukh is Director of IP Product Operations at Tenstorrent, where she focuses on enabling high-performance compute through RISC-V and AI IP and close hardware–software co-development.
- A Doom Demo Journey: Tenstorrent's Ascalon CPU on Synopsys emulation and prototyping systems
- From Profiling to Performance: Optimizing Small Language Models on RISC‑V Architectures
- Why Edges Matter: A Case Study on Performance Improvements for OpenBLAS GEMM on RISC-V
Ramon Canal (PhD ,2004) is a Professor at the Universitat Politècnica de Catalunya (UPC), in Barcelona, Catalonia, EU. He worked at Sun Microsystems in 2000, and he was a Fulbright visiting scholar at Harvard University in 2006/2007 and a visiting professor at the University of Cyprus in 2019/2020. His research focuses on power and thermal aware architectures, as well as reliability and security. He has been programme committee member in several editions of HPCA, ISCA, MICRO, DATE, HiPC, IPDPS, ICCD, ICPADS, CF. He has been co-general chair of DFTS 2025, HPCA 2016 and IOLTS 2012. He has been track co-chair for DATE 2019 and 2020. He is currently an associate editor of the IEEE Transactions on Computers, ACM Transactions on Architecture and Code Optimization (TACO) and the Journal of Parallel and Distributed Computing (JPDC). He is a member of the IEEE.
- Vitamin-V: Results and Lessons Learnt
Rebeca Rasco Flores holds a BSc in Health Engineering from the University of Seville and an MSc in Mechatronics Engineering from the University of Málaga. She is currently a Research Fellow in the Department of Computer Architecture at the University of Málaga, where she is pursuing a PhD in Mechatronics Engineering. Her research focuses on the optimization and acceleration of quantum simulators on high-performance architectures, with a particular interest in RISC-V vector extensions and multi-core parallelism. Her work aims to bridge the gap between advanced classical computing and the efficient simulation of quantum circuits.
- Quantum Computing Simulation on RISC-V: Vector and Multithreaded Evaluation
Riccardo Tedeschi received his Master's Degree in Electronic Engineering from the University of Bologna in 2023. He is now pursuing a Ph.D. in Digital Systems Design within the Department of Electrical and Information Engineering (DEI) at the same university and is currently a visiting researcher at ETH Zürich. His research centers on RISC-V architectures tailored for embedded platforms, particularly in the areas of performance optimization and reliability.
- An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs
- Revisiting Transputers with RISC-V
Representatives from Qualcomm, Synopsys, and an Independent Researcher who are actively contributing the the RISC-V High-Assurance Cryptography task group.
- ACE: Atomic Cryptography Extension for RISC-V
Roberto Giorgi is an Associate Professor in the Department of Information Engineering at the University of Siena, Italy (qualified for Full Professorship). He received his PhD in Computer Engineering and his Master’s in Electronics Engineering, both summa cum laude, from the University of Pisa. He coordinated the 4-year TERAFLUX (Future and Emerging Technologies) and 3-year AXIOM (H2020) projects, was a Work Package leader in Embedded Reconfigurable Architecture, and contributed to HiPEAC and SARC. He participated in ChARM, developing software for ARM-based embedded system performance evaluation. Selected as an ICT/HPC expert by the European Commission, he has authored over 160 scientific papers. His research focuses on Computer Architecture, including Embedded Systems, Multiprocessors, Memory Performance, Workload Characterization, and Reconfigurable Computing. He is a Lifetime Member of ACM and a Senior Member of IEEE and the IEEE Computer Society.
- FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor Tomasulo-Style
Rodrigo Olmos is a researcher in heterogeneous RISC-V SoC design and hardware acceleration at Universidad Politécnica de Madrid (UPM). His work focuses on hardware/software co-design, multicore integration, custom ISA extensions, and FPGA-based prototyping for embedded and high-performance systems.
- Integration of CVA6 in ESP for ISA extensions and coherent multicore: with FFT-butterfly instruction
Roman is a co-founder of Ainekko: a 100% open-source company on a mission to democratize how “the machine learning community collaborates on models, datasets, and applications” and helping “the AI community building the future”. He is a serial entrepreneur, technologist and a co-founder and former CTO of ZEDEDA Inc. who is also deeply involved in the world of Open Source as both VP of Legal Affairs at the ASF and a former VP of Technology at The LF.
- From Open Architecture to Open Silicon: Taping out CORE-ET Many-Core RISC-V Platform
- A Fully Integrated FPGA-Based Reconfigurable Intelligent Surface Controller using an Embedded RISC-V Core
- Transaction-Level Analysis and Optimization of Decision Diagram Packages on RISC-V
- End-to-End On-Device Transformer Training on Ultra-Low Power RISC-V MCU
- Microarchitectural Side-Channel Attack on RISC-V
Sai Rajat is an Engineer working on building high performance RISC-V CPU Cores and System IP at Tenstorrent. His work is deeply rooted in computer architecture, with a specific technical focus on IOMMU and cache coherency. He holds a degree in Electrical and Electronics Engineering from BITS Pilani. Driven by a belief in RISC-V ISA and a strong interest in advancing hardware systems, he joined Tenstorrent in 2024 after stints at Google Hardware and Samsung India.
- Unleashing the Penguin: Programmable Device Model for verifying RISC-V IOMMU using Linux
Sebastian Frey received his M.Sc. degree in Electrical Engineering and Information Technology from
ETH Zürich, Switzerland, in 2022. He is currently working toward his Ph.D. in Information Technology and Electrical Engineering under the supervision of Prof. L. Benini at the Integrated Systems Laboratory, D-ITET, ETH Zurich, Switzerland. His research interests focus on the design of intelligent, head-centric wearables and on applying machine learning for biosignal processing on low-power devices, aiming to advance smart wearable technologies for real-time health monitoring and human-computer interaction.
- RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses
- RoRiV: Porting the RTOS RODOS on RISC-V for future satellite missions
- REPTILES: Repeated tiles of Sargantana
- openEuler for RVA23: Building a RISC-V Server OS with Ecosystem Partners
- RISC-V Instruction-Subset Processors for Extreme Edge Machine Learning.
- AI-Driven Testlist Generation for RISC-V Core Verification
- Coverage-Directed Smoke Regression Optimization via Greedy Set Cover for RISC-V Verification
- CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
Simon Wegener completed his Master’s degree in computer science at the University of Saarland. He joined AbsInt in 2011, specializing in static analysis of binary code. Since then, he has contributed to a multitude of German and European research projects and authored or co-authored a number of peer-reviewed publications on timing analysis for safety-critical embedded systems. As part of TRISTAN, and together with five project partners, he worked on a tracing ecosystem for RISC-V.
- C-Trace: An Open-Source RISC-V Trace Encoder and its Ecosystem
Stefano Di Matteo received his M.Sc. (2019) and Ph.D. (2023) respectively in Electronic Engineering and Information Engineering from the University of Pisa. He is currently a tenure-track researcher in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction Set Extensions for PQC
- Compiler-Aided Autovectorization of PQC on RISC-V Vector Extensions
- ML-KEM on a 22 nm ASIC: Protected, Unprotected, and Hardware-Accelerated Implementations
- Cost-Benefit Analysis of a 22nm ASIC ML-KEM Accelerator for RISC-V Secure Elements
Sven Schönewald received his B.Sc and M.Sc
in 2017 and 2020, respectively, from the Leib-
niz University of Hannover. He is currently a
research associate and Ph.D. candidate at the
Institute of Microelectronics Systems (IMS) from
the Leibniz University of Hannover. His research
focuses on exploring new and efficient archi-
tectures for digital signal-processing tasks. His
main research interest is in the field of RISC-V
based processors.
- Improving DSP Performance in Processors by Repurposing Existing Multiplier Architectures
- Optimizing Llama.cpp and GGML for RISC-V Vector (RVV)
- Functional Verification Strategy for a CVA6 MMU
Tanya is a co-founder of Ainekko: a 100% open-source company on a mission to democratize inference and fine-tuning of all popular open-weight models with a hardware/software product.
Tanya also has started AIFoundry open source ecosystem of AI projects and engineers working on different building blocks of these stacks while maintaining the common goals and compatibility.
Before that Tanya has been involved in the tech world and open source in many different roles. She is an ex-VC @Almaz Capital with OSS and RISC-V portfolio, ex-OSS policy maker, working to integrate developing countries into the global scene while building local independent infrastructure, founder of project helping tech companies affected by the wars to leverage OSS for freedom of tech from politics.
- From Open Architecture to Open Silicon: Taping out CORE-ET Many-Core RISC-V Platform
- Why the industry needs CHERI to be able to meet the EU Cyber Resilience Act
He is a professor at the Institute of Space and Astronautical Science (ISAS) of the Japan Aerospace Exploration Agency (JAXA). He is engaged in solar system exploration, particularly research on planetary exploration rovers for celestial surfaces. As principal investigator, he developed the MINERVA and MINERVA-II rovers for the asteroid sample return missions of the Hayabusa and Hayabusa2 spacecraft. He has also been involved in multiple lunar exploration missions, including the OMOTENASHI CubeSat and the SLIM landing mission. He served as principal investigator for the LEV-1 rover for the SLIM mission.
- World's first lunar exploration rover using FPGA-based RISC-V processor
Dr. Tianhai Liu is a postdoctoral researcher at KIT and a project lead at aicas GmbH. His work focuses on formal methods, consistency analysis, and verification for cyber-physical systems, with applications in automotive software, IoT architectures, and FPGA-cloud integration.
- FPGA Lifecycle Management for RISC-V Systems
- Bringing Cloud-Connected Automotive Workloads to RISC-V: A CVA6-Based FPGA Case Study
Associate professor
Institute of Computing Technology, Chinese Academy of Sciences
Research interests: computer architecture, memory system, memory security
- DASICS: Efficient In-process Protection with Hardware-assisted Dynamic Compartmentalization
- wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture
I'm an Assistant Professor of Reconfigurable Computer Architectures in the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology and a RISC-V Advocate. I completed my PhD under Prof. Marcel Baunach, earning the Doctor of Engineering Sciences (Dr. techn.) degree sub auspiciis Praesidentis. My research focuses on sustainable, flexible, and runtime-reconfigurable microcontroller architectures for embedded systems – especially FPGA-based RISC-V – at the hardware-software interface, including processor logic and embedded operating systems. I teach CPU architecture and implementation, embedded programming, and scientific writing. I have authored peer-reviewed publications in international journals and conference proceedings and am active in several RISC-V SIGs, Euromicro, the ACM, and the German Informatics Society (GI).
- Runtime Reconfiguration of Decoders in Minimal-area RISC-V Cores
Tor Jeremiassen is a senior staff software engineer at Google LLC working on tools supporting architectural exploration, in particular, instruction level simulation frameworks. He brings with him 30 years of experience in writing simulators and frameworks for a variety of processors and application specific accelerators, particularly in the embedded space.
Tor earned a Ph.D. in Computer Science from the University of Washington, specializing in compile time optimizations to improve cache performance on shared memory multiprocessors. Tor also holds an M.S. in Computer Science from the University of Washington, and a B.S in Computer Science from the University of Texas at Austin.
- Accelerating RISC-V Innovation with open MPACT Tools from Google
Trevor is an embedded systems developer at BayLibre, where he works on everything from the Yocto Project, to automation with CI and kernel development.
- RISE and Yocto: Building a RISC-V Board Farm
Tsung-Li Chen is a master’s student in the Department of Computer Science and Information Engineering at National Taiwan University of Science and Technology (NTUST). His research interests focus on computer architecture, microarchitectural performance modeling, and RISC-V processor design. His current work explores lightweight performance simulation frameworks for modern out-of-order processors by integrating timing models with functional simulators. Tsung-Li has been actively involved in RISC-V related research and previously presented work at the RISC-V Summit North America.
- RISCV-Perf: A Performance Modeling Framework for RISC-V Processors Integrated with Spike
A working student at PlanV, currently pursuing a Master's in Embedded Computing Systems at RPTUKaiserslautern, Germany.
- CVA6 Optimization
My name is Utku Budak. I am a research assistant and PhD candidate at the Chair of Security in Information Technology, working in cooperation with Siemens.
- Enhancing Boot Time Security in RISC-V Leveraging Keccak Hardware Accelerator
Valeria Piscopo received the B.Sc. and M.Sc. degrees in Electronic Engineering from Politecnico di Torino, in 2021 and 2024 respectively. Since November 2024, she is a Ph.D student in Electrical, Electronic and Communications Engineering at Politecnico di Torino. Her research activity is centered on the design of secure hardware accelerators for Post-Quantum Cryptography and their integration in RISC-V ecosystems.
- CIRCE: CROSS Integrated RISC-V Cryptographic Extension
- HORCRUX: a Post-Quantum Cryptography Instruction Set Extension
- CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON
- Evaluating the Vulnerability of RISC-V CPUs Against Cache Timing Attacks
Victor Jean-Baptiste Jung received his Bachelor’s Degree in Computer Science and Engineering Physics from Juniata College, and his Master’s Degree in Computer Science from the Institut Supérieur de l’Electronique et du Numérique of Lille (ISEN Lille) in 2022. After 3 months as a research intern with KU Leuven’s MICAS Research group, supervised by Prof. Marian Verhelst, he's currently pursuing his Ph.D. at the Integrated Systems Laboratory with Prof. Dr. Luca Benini. His current research interests include Efficient deployment of ML models on Microcontrollers, Tiny Transformers, Scheduling, and Quantization.
- End-to-End On-Device Transformer Training on Ultra-Low Power RISC-V MCU
- AI-Driven Testlist Generation for RISC-V Core Verification
- ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V
- Showcasing the ARCANE In-Cache computing IP into a RISC-V Linux system
- Performance Characterization and Profiling of HQC Autovectorization on RISC-V Vector cores
Scientist at Centre for Development of Advanced Computing (C-DAC), Bangalore, India
- Vishwa: A Scalable RISC-V Based GPGPU
- UCAgent: An End-to-End Agent for Block-Level Functional Verification
- RuyiSDK Package Manager - A Unified Package Management and Development Environment for RISC-V
PhD student at the LEAT laboratory (Laboratoire d'Électronique, Antennes et Télécommunications), Université Côte d'Azur, France. Research focuses on neuromorphic computing, specifically the design and optimization of energy-efficient hardware accelerators for Spiking Neural Networks (SNNs).
- Energy-Efficient RISC-V based neuromorphic SoC for Edge AI Applications
- An Open-Source RISC-V VM-Level TEE Architecture Implemented on XiangShan Processor
A member of the openKylin Technical Committee, where he leads the RISC-V and RISC-V AI SIGs. An active contributor to the global RISC-V community, he is dedicated to advancing the RISC-V software ecosystem and hardware-software co-design within openKylin. His research interests focus on next-generation operating systems and high-performance RISC-V implementations for AI workloads.
- openKylin: Empowering the RISC-V AI Ecosystem
- A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt
- “One Student One Chip”: Student Board Power-Up Demo Video
- OSOC Mambo Robot: RISC-V processor chip showcase using open-source IP, EDA, and PDK
- "One Student One Chip" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC
- Lessons Learned from Designing Decoupled-Access Hardware Accelerators in a RISC-V Framework
A master's student at Tsinghua University
- Revisiting x86-64 to RISC-V Binary Translation: A Hardware/Software Co-Design Path
- Profiling and Optimizing AME for Matrix Multiplication
Chief Engineer of Institute of Software, Chinese Academy of Sciences
- openEuler for RVA23: Building a RISC-V Server OS with Ecosystem Partners
- wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture
- UCAgent: An End-to-End Agent for Block-Level Functional Verification
- UCAgent: An End-to-End Agent for Block-Level Functional Verification
- Accelerating RISC-V Innovation with open MPACT Tools from Google
Yichao Zhang received his M.Sc. degree from Nanyang Technological University, Singapore, in 2017. He served as a Physical Design Engineer at MediaTek and as the Lead Application Engineer at Cadence Design Systems in Singapore until 2021.
In 2021, he joined the Integrated Systems Laboratory at ETH Zurich to pursue a Ph.D. under the supervision of Prof. Dr. Luca Benini. As a developer of the Parallel Ultra-Low Power (PULP) platform, his research focuses on physically feasible, ultra-large-scale many-core shared-memory architectures with both scalar and vector processing, leveraging scalable, high-bandwidth, low-latency Network-on-Chip. On the application side, he focuses on software-defined B5G/6G Open Radio Access Networks for programmable baseband Physical Uplink Shared Channel processing.
- RISC-V Silicon at Scale in Academia: Designing “Big” Open-Source Chips on PULP Platform
Yinan Xu is an Assistant Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He received his B.Eng. degree from the University of Chinese Academy of Sciences in 2019 and his Ph.D. degree from ICT, CAS in 2025. He is a core developer of the XiangShan open-source high-performance RISC-V processor, where he has pioneered several agile design and verification techniques that have been successfully integrated into the project. His work has been recognized with the CAS President’s Special Award, the ICT Director’s Special Award (Xia Peisu Award), and the National Scholarship. His research contributions have been published in leading venues such as MICRO, HPCA, DAC, and JCST. Notably, XiangShan and its agile design methodology were selected as one of 2022 IEEE Micro Top Picks, recognizing it as one of the year’s most influential conference papers to computer architecture.
- SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification
- The art of zeroing on CHERI RISC-V systems
Dr. Yueh-Feng Lee received his Ph.D. degree in computer science from National Chiao Tung University. He previously worked at Mediatek and Industrial Technology Research Institute. His areas of focus include AI compiler and runtime, hypervisor technology, and embedded systems.
- Accelerating LLM Inference on Edge RISC-V CPUs via Vector Extension Instructions and Flash Attention
I am currently an Assistant Research Fellow at the Center for Advanced Computer Systems, Institute of Computing Technology, Chinese Academy of Sciences. My research interests include formal methods, hardware-software model checking, and deep integration of hardware and software. I completed my Ph.D. in Software Engineering at the Institute of Software, Chinese Academy of Sciences in 2024, and received my Bachelor's degree in Statistics from Northeast Normal University in 2017.
- Scalable Symbolic Quick Error Detection using Lightweight Processor-Level Abstraction
Email: luoyunxiang@iscas.ac.cn
Intelligent Software Research Center (ISRC), Institute of Software, Chinese Academy of Sciences (ISCAS)
- From Fragmentation to Systematization: A Standardized Quality Selection and Reconstruction Approach for RISC-V Courses
- An Efficient Approach to Apply the RISC-V Sail Model to Chip Verification
- RuyiSDK Package Manager - A Unified Package Management and Development Environment for RISC-V
- Sail-RISCV-WASM A Browser-Native RISC-V Toolchain and Debugging Workbench
Yvan Tortorella received the Ph.D. degree from the University of Bologna, Italy, in 2025, with a dissertation on RISC-V-based heterogeneous computing platforms for reliable space computing. He is currently with Fondazione Chips-IT, where he is a postdoctoral researcher and digital IC designer working on mixed-criticality space processors and AI accelerators.
- An Open Heterogeneous RISC-V AI Acceleration Architecture for Next-Generation Space Computers
Zdenek received the PhD degree from the Brno University of Technology, Czechia, where he played a significant role in the research related to processor development automation. It enabled the creation of the processor development tools, Codasip Studio, that he has been driving ever since at Codasip. Zdenek has continued working as the chief architect of Codasip Studio for more than 12 years. He has also been the architect of diverse processor cores, including but not limited to 16/32-bit architectures for IoT, 32/64bit DSP-oriented architectures, or Linux capable architectures. All of these architectures were developed using Codasip Studio, and many of them were based on the RISC-V ISA. Zdenek has been also involved in embedded systems design (software and hardware) and driving R&D activities for many years.
- RISC-V Custom Instructions for Automotive Control and DSP Algorithms Compliant with ISO 26262
- High-Performance CRC/EC Acceleration for RISC-V Server Storage via Novel ISA Extensions
I am Huazhong Zheng, a Master’s student at the Institute of Computing Technology, Chinese Academy of Sciences. My research focuses on RISC-V processor fuzzing. Currently, I am working on adaptive mutation operator scheduling algorithms, enabling fuzzers to dynamically select more effective mutation strategies to improve coverage and vulnerability detection efficiency.
- AdaMut-RV: FPGA-Accelerated RISC-V Fuzzing with Adaptive Mutation Operator Scheduling
- Concolic Execution Guided Hybrid Whitebox Fuzzing for RISC-V Processors