We present the development flow and platform we have built to support CHERI development and ratification of the RVY extension. CHERI is an ISA extension providing hardware support for capabilities - unforgeable memory references embedding a memory address as well as bounds and permissions metadata. It enables spatial and temporal memory safety by design. We have developed a comprehensive workflow used to validate the proposed RVY extension both for functionality and performance. We maintain and make use of a formal golden model, which we leverage for design verification effort through directed-random fuzz testing of architectural features under development. We gather core CHERI functionalities in a reusable RTL library to use across multiple commercial and research implementations, maximising reuse of verification effort. We build and boot soft-core images of CHERI-enabled systems on FPGA at scale, enabling software development and performance
evaluation of RV64Y microarchitectures and software stacks. This infrastructure has enabled rapid convergence for the development of the RVY extension with a high level of confidence in functionality and performance. We are now making use of this infrastructure to further enable various streams of research.