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UID:pretalx-eu-summit-2026-H87VUG@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T105000
DTEND;TZID=CET:20260609T110000
DESCRIPTION:Confidential VMs enable cloud service providers to operate a se
 cure and trustworthy multi-tenant cloud infrastructure.\nWhile confidentia
 l VMs ensure comprehensive protection for cloud workloads\, such heavy-wei
 ght isolation is often omitted for serverless applications that co-locate 
 thousands of cloud workers within the same process to optimize FaaS overhe
 ads through efficient context switches.\nIn this work\, we present CAGE-V\
 , a novel confidential computing architecture that supports lightweight en
 clave-based isolation for individual cloud workers running inside confiden
 tial VMs.\nGuest enclaves support fast context switches within the confide
 ntial VM\, as TLB entries are tagged with Domain Identifiers\, eliminating
  overheads that stem from TLB flushes.\nWe present a CAGE-V prototype\, co
 nsisting of a hardware extension for the CORE-V CVA6 processor and a small
  security monitor\, and evaluate our design in terms of system performance
 \, demonstrating a minor performance impact.
DTSTAMP:20260522T162405Z
LOCATION:Poster Island B
SUMMARY:CAGE-V: Confidential Computing Architecture supporting Guest Enclav
 es for RISC-V - Moritz Waser
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/H87VUG/
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UID:pretalx-eu-summit-2026-B3ASBU@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T103000
DTEND;TZID=CET:20260611T104000
DESCRIPTION:The semiconductor industry increasingly requires engineers skil
 led in both hardware design and software execution. This contribution pres
 ents a RISC-V-centric educational pipeline developed at our institute\, br
 idging foundational bachelor's coursework and specialized master's program
 s. We outline three core courses that integrate practical hardware design\
 , custom ISA extensions\, and full-stack security. First\, a computer orga
 nization course teaches students hardware design in SystemVerilog with the
  goal of modifying and extending a full RISC-V CPU. Second\, a hardware se
 curity course tasks students with both the implementation of security-rela
 ted hardware primitives for open-source RISC-V cores\, and the development
  of software to interact with the extended hardware. Finally\, a secure sy
 stem architectures course addresses memory safety through full system prot
 otyping\, requiring students to modify the RISC-V Spike simulator and writ
 e custom LLVM compiler passes. This hands-on approach provides the ecosyst
 em with engineers equipped to tackle modern microarchitectural and securit
 y challenges.
DTSTAMP:20260522T162405Z
LOCATION:Poster Island D
SUMMARY:Integrating RISC-V into University Education: A Full-Stack Approach
  to Teaching System Security - Lorenz Schumm\, Moritz Waser
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/B3ASBU/
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