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UID:pretalx-eu-summit-2026-33SLKJ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T140000
DTEND;TZID=CET:20260610T141000
DESCRIPTION:The exponential growth in RISC-V processor complexity challenge
 s traditional functional verification. Both directed testing and constrain
 ed-random simulation are inefficient for modern architectural designs. Whi
 le hardware fuzzing has emerged as a powerful alternative for uncovering d
 eep microarchitectural bugs\, existing software-based fuzzers are severely
  bottlenecked by slow RTL simulation speeds and suboptimal mutation strate
 gies that lack adaptive guidance.We propose AdaMut-RV\, a high-throughput\
 , FPGA-accelerated fuzzing framework specifically optimized for RISC-V pro
 cessor verification. Unlike software-bound solutions\, AdaMut-RV offloads 
 both the processor and the fuzzer onto FPGA hardware\, enabling MHz-scale 
 execution speeds. The core innovation of AdaMut-RV is an intelligent mutat
 ion-operator scheduler based on the Multi-Armed Bandit (MAB) reinforcement
  learning algorithm. By categorizing AFL-inspired mutation operators into 
 nine distinct classes\, our scheduler dynamically prioritizes those that y
 ield the highest coverage gains based on real-time hardware feedback. This
  dynamic scheduling mechanism accelerates the exploration of processor des
 ign spaces and critical corner-case logic. Preliminary results demonstrate
  that AdaMut-RV significantly outperforms state-of-the-art software-based 
 fuzzers. It achieves higher Control and Status Register Coverage while rea
 ching the same coverage targets at a significantly faster rate.
DTSTAMP:20260522T162445Z
LOCATION:Poster Island A
SUMMARY:AdaMut-RV: FPGA-Accelerated RISC-V Fuzzing with Adaptive Mutation O
 perator Scheduling - Zheng Huazhong
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/33SLKJ/
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