Spiking Neural Networks (SNNs) offer significant energy efficiency for Edge AI, yet their event-driven nature leads to unpredictable, variable-length output data. In traditional heterogeneous SoCs, this unpredictability causes high CPU overhead and bus inefficiency. This paper presents a specialized Event-Adaptive DMA (EA-DMA) integrated into a RISC-V based SoC. Unlike standard DMAs, the proposed engine performs buffer-triggered, variable-length transfers with maximum-size clamping and hardware backpressure for irregular SNN spike traffic. This work provides a scalable solution for integrating neuromorphic accelerators into the RISC-V ecosystem.