Writing verification stimulus for RISC-V processors requires deep expertise across ISA specifications, microarchitectural implementation, and test framework APIs. We present an LLM-driven multi-agent framework that transforms a brief natural-language scenario description into a comprehensive, executable RISC-V test generator. Five specialized AI agents form a sequential enrichment
pipeline: an ISA expert expands intent into architecturally complete scenarios, an RTL analyst reads hardware source code to inject microarchitecture-targeted stress patterns, a framework specialist maps steps to concrete API calls, a builder synthesizes deployable code, and a validator ensures correctness through static checks and instruction-set-simulator execution. On the RISC-V Svadu extension, a 3-line scenario yields 490 lines of validated, simulation-passing code in under 13 minutes—a ∼40× speedup versus an estimated∼8 hours of manual effort.