While hardware prefetchers accelerate memory performance, they inadvertently leave microarchitectural footprints that attackers can exploit. Previous work showed that instruction and data prefetchers on Intel, AMD and Apple processors are prone to microarchitectural side-channel attacks. In this paper we investigate the data stride prefetcher in the \textit{Xuantie C910} -- a server-grade RISC-V processor extensively deployed in cloud environments. Furthermore, we present the first microarchitectural attack targeting a hardware prefetcher on a RISC-V processors. In that regard, we port StrideRE on RISC-V processors to reverse engineer its hardware prefetcher. Finally, we provide two Proof-of-Concept (PoC) attacks: partial memory address disclosure and control flow leakage. We find that both attacks are effective across privilege levels.