This paper presents a distributed Input-Output Physical Memory Protection (IOPMP) architecture featuring a decoupled I/O bridge and checker. The architecture enables distributed placement of I/O bridges to accommodate multi-master SoC configurations while sharing a single centralized checker, significantly reducing area overhead. The design is implemented in a 7nm process, with a single I/O bridge occupying less than 1200 µm². It incurs less than 0.2% performance overhead under 4KB large-packet transmission. The code has been merged into the OpenXiangShan Git repository and is available as open-source hardware.