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UID:pretalx-eu-summit-2026-MKEL9U@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T155000
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DESCRIPTION:In certain scenarios computer systems have to deal with both li
 ttle-endian and big-endian data regardless their native endianness. A RISC
 -V extension that makes it possible to remove the overhead introduced when
  dealing with foreign-endian data is proposed. It can be implemented with 
 little engineering effort and negligible impact on performance and hardwar
 e resources. Preliminary results show that the extension can remove a 62% 
 or 37% of foreign-endian data processing overhead when compared to softwar
 e solutions using the base Instruction Set Architecture (ISA) or the curre
 ntly available bit manipulation extensions respectively. This performance 
 boost can benefit both new and legacy software once compiler and library s
 upport is put in place.
DTSTAMP:20260522T162431Z
LOCATION:Poster Island D
SUMMARY:RISC-V Address-Encoded Byte Order Extension - David Guerrero Martos
 \, Jorge
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/MKEL9U/
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