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UID:pretalx-eu-summit-2026-TTPKFR@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T153000
DTEND;TZID=CET:20260610T154000
DESCRIPTION:In RISC-V based systems\, a key security mecha-\nnism is the In
 put-Output Physical Memory Protection (IOPMP)\nsubsystem\, which enables c
 ontrolled access to shared memory\nand peripherals by non-core initiators 
 [1]. While the specification\ndefines functional behavior\, the availabili
 ty of a publicly available\ncycle-accurate reference model will encourage 
 early SoC-level\nintegration.\nThis paper presents an open-source cycle-ac
 curate IOPMP\nreference model consisting of a SystemVerilog wrapper integr
 ated\nwith a C-based functional reference model. The SystemVer-\nilog wrap
 per models pipeline timing\, transaction ordering\, and\nstandard bus inte
 rfaces\, while the C-based reference model\nprovides specification-complia
 nt functional evaluation of address\nmatching\, permission checking\, and 
 priority resolution. The\ncombined architecture enables both functional co
 rrectness and\ntiming-accurate system-level validation.\nThe model support
 s AMBA AXI4 for transaction enforcement\nand AMBA AHB3-Lite for configurat
 ion\, to enables seamless re-\nplacement with actual RTL. A reusable suite
  of architectural-level\nbare-metal tests is provided\, and the approach i
 s demonstrated\nthrough integration in an open-source CVA6-based SoC [4].\
 nIndex Terms—RISC-V\, IOPMP\, SoC Security\, Reference\nModel\, Cycle-Ac
 curate Modeling
DTSTAMP:20260522T162745Z
LOCATION:Poster Island B
SUMMARY:Cycle-Accurate IOPMP Reference Model with Configurable Interfaces\,
  Integration Tests\, and a CVA6 SoC Implementation - Gull Ahmed
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/TTPKFR/
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