BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//speaker//9G93MH
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-3MEHL7@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T134000
DTEND;TZID=CET:20260611T135000
DESCRIPTION:Hearing loss is among the most prevalent sensory impairments wo
 rldwide. Hearing aids that incorporate adaptable\, personalized signal pro
 cessing have the potential to improve communication outcomes and social pa
 rticipation for affected individuals. The development and rigorous evaluat
 ion of novel hearing-aid algorithms requires high-level programmable\, low
 -power\, and portable behind-the-ear (BTE) research platforms that enable 
 studies in real-world environments. The RISC-V open source instruction set
  architecture (ISA) presents a flexible and configurable baseline for the 
 development of signal processing architectures.\nThis paper presents a lig
 htweight single instruction multiple data (SIMD) architecture featuring a 
 complex number extension targeted at embedded applications with a specific
  focus on the energy efficiency by reusing existing multiplier hardware. P
 erformance data is gathered from a reference Fast Fourier Transform (FFT) 
 implementation\, with FFT sizes taken from the field of typical hearing ai
 d applications. Power values are obtained by synthesizing the baseline pro
 cessor and the extension in a 22 nm FD-SOI technology\, followed by a gate
 -level simulation to obtain accurate switching activity values. The implem
 ented extension achieves a speedup of up to 26 %. A comparison of the ener
 gy values through gate-level simulation reveals that the energy consumptio
 n of the modified design decreases by 27 % on average.
DTSTAMP:20260522T162735Z
LOCATION:Poster Island A
SUMMARY:Improving DSP Performance in Processors by Repurposing Existing Mul
 tiplier Architectures - Sven Schönewald
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/3MEHL7/
END:VEVENT
END:VCALENDAR