Dr. Erich Focht
Dr. Erich Focht is a system architect and physicist currently working as a Senior Fellow at Openchip, where he leads the Accelerator-AI architecture group and focuses on the development of Artificial Intelligence (AI) and High-Performance Computing (HPC) accelerators. He holds a Ph.D. in theoretical physics from RWTH Aachen and has a professional background that spans computational physics, numeric algorithms, distributed systems software, parallel file systems and hardware-software co-design.
Before his current role at Openchip, Erich spent over 25 years at NEC HPC Europe where he contributed to the system design of dozens of supercomputers, most of them present in the TOP500 list.
Within the RISC-V open-source ecosystem, Dr. Focht contributes to the standardization of matrix operations as an active member of the IME TG, focusing on RISC-V matrix implementations. He also represents Openchip in the RVI Technical Steering Committee.
Session
RISC-V's Zvvm matrix extension stores all tile state in the standard V register file and derives tile geometry algebraically from VLEN, SEW, and a new aspect-ratio field λ. This yields arithmetic intensity that scales with VLEN: a binary compiled at VLEN=256 delivers higher throughput at VLEN=65536 with no recompilation. The same partial-VL mechanism that enables one-column-at-a-time embedded streaming also drives full HPC bulk tiling, while microscaling is integrated via vm-bit opcode aliasing with no new architectural state.
Tile dimensions are not programmer-specified constants — they are consequences of existing parameters. The tile is always square: M = N = VLEN/(SEW×λ), with inner dimension K_eff = λ×W×LMUL. Arithmetic intensity (M/2) grows proportionally with VLEN, and the ratio of intensity to cache-to-VRF bandwidth remains constant — a provable algebraic identity with no equivalent in Arm SME or Intel AMX.
Zvvm's geometry knobs form an intent vocabulary expressed from both sides: software selects LMUL and VL to control K_eff depth and streaming granularity; hardware determines λ and VLEN to shape the tile for its datapath. Setting VL = K_eff with LMUL = 1 gives portable streaming; increasing LMUL or computing multiple C panels trades register pressure for compute intensity — all via the same opcode.
Microscaling (MX) support is integrated by aliasing the vm bit in FP multiply-accumulate opcodes, introducing no new encoding space, registers, or modes.