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UID:pretalx-eu-summit-2026-EGU3RV@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T110000
DTEND;TZID=CET:20260611T113000
DESCRIPTION:The increasing computational demands characteristic of contempo
 rary deep learning models\, particularly those associated with computer vi
 sion tasks employing Vision Transformers\, present considerable constraint
 s for energy-limited smart devices and edge computing platforms. To addres
 s this challenge\, we demonstrate a RISC-V SoC that incorporates ARCANE\, 
 a 512KiB compute-capable Last-Level Cache\, which enables In-Cache Computi
 ng (ICC). This capability is crucial for substantially mitigating the ener
 gy and latency overheads linked to data movement between the central proce
 ssing unit (CPU) and main memory—a primary architectural bottleneck. To 
 validate the system's operational maturity\, we deploy models such as the 
 22-million parameter DINOv2-S and the lightweight MobileNetV2 utilizing th
 e TVM framework. This deployment serves to demonstrate the platform's capa
 city to efficiently execute both state-of-the-art\, computationally intens
 ive computer vision workloads and standard image classification tasks with
 in a unified environment. The system\, instantiated on a ZCU104 FPGA featu
 ring 1GiB of DDR4 memory\, operates at a clock frequency of 80MHz and furn
 ishes a Linux operating environment complete with a dedicated suite of use
 r applications. These applications provide quantitative evidence of the si
 gnificant performance advantages conferred by ARCANE's near-memory computi
 ng paradigm when compared against CPU-only execution. By integrating a cus
 tom tensor ISA that remains transparent and lock-less to the application p
 rogrammer\, ARCANE establishes itself as a valuable and pioneering contrib
 ution to the RISC-V ecosystem\, representing one of the first In-Cache Com
 puting IP cores integrated into a Linux operating environment.
DTSTAMP:20260522T162438Z
LOCATION:Devzone
SUMMARY:Showcasing the ARCANE In-Cache computing IP into a RISC-V Linux sys
 tem - Vincenzo Petrolo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/EGU3RV/
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UID:pretalx-eu-summit-2026-G7Y79Q@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T121500
DTEND;TZID=CET:20260611T123000
DESCRIPTION:Modern data-centric workloads increasingly expose the limitatio
 ns of traditional von Neumann architectures\, where excessive data movemen
 t limits throughput and energy efficiency.\n        While hardware acceler
 ators improve performance\, they often lack flexibility and still require 
 costly memory transfers.\n        Existing compute in- and near-memory sol
 utions reduce the memory bottleneck but introduce usability challenges rel
 ated to constraints on data placement.\n        ARCANE is a cache architec
 ture that doubles as a tightly-coupled near-memory coprocessor.\n        T
 he embedded RISC-V cache controller executes custom instructions offloaded
  by the host CPU relying on near-memory vector processing units within the
  cache memory subsystem. This architecture hides memory synchronization an
 d data mapping from application software\, while offering software-based I
 nstruction Set Architecture extensibility.\n        Evaluations demonstrat
 e up to an 84x speedup on 8-bit convolution layers over a traditional syst
 em-on-chip\, incurring only a 41.3\\% area overhead.
DTSTAMP:20260522T162438Z
LOCATION:Plenary
SUMMARY:ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RIS
 C-V - Flavia Guella\, Vincenzo Petrolo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/G7Y79Q/
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