Yong Yang
Yong Yang received his Ph.D. in Engineering and holds the title of vice Professor. He is the Vice General Manager and Board Member of WCH (Nanjing Qinheng Microelectronics), and Chairman of the Nanjing RISC-V Microcontroller Research Institute. He was the inaugural Vice-Chair of the RISC-V International Certification Steering Committee (CSC). He also serves as an off-campus supervisor at Southeast University and an Industry Professor of Jiangsu Province. With over a decade of R&D experience in embedded systems and IoT integrated circuits, he has spearheaded the design and mass production of proprietary RISC-V MCUs, Bluetooth Low Energy (BLE) SoCs, and USB 3.0 SuperSpeed chips. His technical expertise spans RISC-V ISA, processor microarchitecture, RISC-V Domain-Specific Architectures (DSA), interrupt controllers, and RF transceivers and Antenna design.
Session
This work presents a novel, highly integrated dual-core microcontroller architecture based on the RISC-V ISA, specifically designed for First Person View(FPV) Drone On-Screen Display (OSD) systems. Traditional solutions suffer from computational bottlenecks or multi-chip synchronization latency. By leveraging a specialized RISC-V asymmetric dual-core architecture, this design achieves sub-microsecond synchronization between complex flight control execution and high-framerate video rendering. Incorporating advanced ISA extensions and custom microarchitectural features, the proposed SoC successfully injects rendered OSD data during the video signal's blanking period with pixel-level precision, showcasing the potential of RISC-V in mission-critical vertical application domains.