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UID:pretalx-eu-summit-2026-ZTNLUP@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T141000
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DESCRIPTION:This work presents a novel\, highly integrated dual-core microc
 ontroller architecture based on the RISC-V ISA\, specifically designed for
  First Person View(FPV) Drone On-Screen Display (OSD) systems. Traditional
  solutions suffer from computational bottlenecks or multi-chip synchroniza
 tion latency. By leveraging a specialized RISC-V asymmetric dual-core arch
 itecture\, this design achieves sub-microsecond synchronization between co
 mplex flight control execution and high-framerate video rendering. Incorpo
 rating advanced ISA extensions and custom microarchitectural features\, th
 e proposed SoC successfully injects rendered OSD data during the video sig
 nal's blanking period with pixel-level precision\, showcasing the potentia
 l of RISC-V in mission-critical vertical application domains.
DTSTAMP:20260715T065843Z
LOCATION:Poster Island C
SUMMARY:A RISC-V Dual-Core Microcontroller Architecture for Flight Control 
 OSD: A Single-Chip Implementation - Yong Yang
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZTNLUP/
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