As system complexity increases, so does the difficulty in demonstrating their overall correctness. The Monitor-Actuator design pattern is one the main approaches in the literature proposing ways to ensure that systems can work safely, even in the presence of undetected or unpatched system defects. This design pattern consists of coupling verification monitors to, at execution time, verify if a target system is executing as expected and intervene when needed. Therefore, maximizing the isolation between the target system and the monitoring unit becomes a fundamental factor to reduce mutual interference, both in functionality and in terms of computational overhead. This work presents a Monitor-Actuator proof of concept system developed for the PolarFire SoC Icicle Kit. The system consists of a target application executing on the PolarFire SoC’s processing system and a dedicated runtime verification monitor IP executing on the programmable logic unit. We detail how the monitor IP is generated from a formal specification that is used to, first synthesize it's equivalent CPP code, and later serve as input to the process of high-level synthesis of hardware description language. The description of the development process and setup is designed to serve as a reference for future applications requiring low interference hardware synthesized runtime monitors capable of detecting user-specified property violations in a platform’s hardcore and softcore RISC-V processors.