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UID:pretalx-eu-summit-2026-F7UKA3@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T140000
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DESCRIPTION:As system complexity increases\, so does the difficulty in demo
 nstrating their overall correctness. The Monitor-Actuator design pattern i
 s one the main approaches in the literature proposing ways to ensure that 
 systems can work safely\, even in the presence of undetected or unpatched 
 system defects. This design pattern consists of coupling verification moni
 tors to\, at execution time\, verify if a target system is executing as ex
 pected and intervene when needed. Therefore\, maximizing the isolation bet
 ween the target system and the monitoring unit becomes a fundamental facto
 r to reduce mutual interference\, both in functionality and in terms of co
 mputational overhead. This work presents a Monitor-Actuator proof of conce
 pt system developed for the PolarFire SoC Icicle Kit. The system consists 
 of a target application executing on the PolarFire SoC’s processing syst
 em and a dedicated runtime verification monitor IP executing on the progra
 mmable logic unit. We detail how the monitor IP is generated from a formal
  specification that is used to\, first synthesize it's equivalent CPP code
 \, and later serve as input to the process of high-level synthesis of hard
 ware description language. The description of the development process and 
 setup is designed to serve as a reference for future applications requirin
 g low interference hardware synthesized runtime monitors capable of detect
 ing user-specified property violations in a platform’s hardcore and soft
 core RISC-V processors.
DTSTAMP:20260522T162438Z
LOCATION:Poster Island B
SUMMARY:Hardware-Synthesized Monitor-Actuator Design Patterns: a Proof-of-C
 oncept Application - Giann Spilere Nandi
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/F7UKA3/
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