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UID:pretalx-eu-summit-2026-WVYG7T@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T105000
DTEND;TZID=CET:20260611T110000
DESCRIPTION:With the proliferation of data-hungry accelerators and co-proce
 ssors in embedded system design\, co-design of processors and memory syste
 ms is becoming more important.  Current simulation techniques for processo
 rs rely on oversimplified and inflexible memory models\, while techniques 
 for memory system simulation tend to only utilize simple processor models.
   In this work\, we integrate a cycle-accurate Verilator processor and vec
 tor co-processor model with the Gem5 memory simulator in order to evaluate
  the full impact of a data-hungry co-processor on the memory system and ma
 in core performance\, and to provide a framework for future co-design of b
 oth processor and memory systems.
DTSTAMP:20260522T162735Z
LOCATION:Poster Island B
SUMMARY:Evaluating the Impact of Vector Co-Processors on Memory Hierarchies
  through Hybrid Simulation - J Parker Jones
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/WVYG7T/
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