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UID:pretalx-eu-summit-2026-B3ASBU@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T103000
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DESCRIPTION:The semiconductor industry increasingly requires engineers skil
 led in both hardware design and software execution. This contribution pres
 ents a RISC-V-centric educational pipeline developed at our institute\, br
 idging foundational bachelor's coursework and specialized master's program
 s. We outline three core courses that integrate practical hardware design\
 , custom ISA extensions\, and full-stack security. First\, a computer orga
 nization course teaches students hardware design in SystemVerilog with the
  goal of modifying and extending a full RISC-V CPU. Second\, a hardware se
 curity course tasks students with both the implementation of security-rela
 ted hardware primitives for open-source RISC-V cores\, and the development
  of software to interact with the extended hardware. Finally\, a secure sy
 stem architectures course addresses memory safety through full system prot
 otyping\, requiring students to modify the RISC-V Spike simulator and writ
 e custom LLVM compiler passes. This hands-on approach provides the ecosyst
 em with engineers equipped to tackle modern microarchitectural and securit
 y challenges.
DTSTAMP:20260522T162354Z
LOCATION:Poster Island D
SUMMARY:Integrating RISC-V into University Education: A Full-Stack Approach
  to Teaching System Security - Lorenz Schumm\, Moritz Waser
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/B3ASBU/
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