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UID:pretalx-eu-summit-2026-9MT9QK@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T105000
DTEND;TZID=CET:20260611T110000
DESCRIPTION:The development of our tightly coupled SIMD/Vector accelerator 
 for matrix operations requires extending the RISC-V instruction set. Speci
 al compiler support is required for this extension. Our methodology starts
  from a Sail description of the ISA extension and generates the compiler t
 arget description data. The instructions are described in Sail and are tes
 ted in the generated simulator. The compiler is generated from the descrip
 tion model and is tested with the accelerator implemented in hardware. The
  experimental results suggest that for matrix multiplication we obtained s
 peed-ups up to 1413x compared to an ARM A72 core.
DTSTAMP:20260522T162358Z
LOCATION:Poster Island C
SUMMARY:Custom RISC‑V SIMD Matrix Extensions with LLVM Support - Alexandr
 u Puscasu\, Catalin Ciobanu
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/9MT9QK/
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UID:pretalx-eu-summit-2026-UC3AZA@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T130000
DTEND;TZID=CET:20260611T133000
DESCRIPTION:The development of our tightly coupled SIMD/Vector accelerator 
 for matrix operations requires extending the RISC-V instruction set. Speci
 al compiler support is required for this extension. Our methodology starts
  from a Sail description of the ISA extension and generates the compiler t
 arget description data.\n\nThe accelerator main features are: 32 software 
 defined 2D registers\, dedicated hardware for matrix operations and a dedi
 cated memory interface. The accelerator employs the CoreV-eXtension-Interf
 ace (CV-X-IF) and could be connected to multiple RISC–V cores that featu
 re this interface. \n\nThe custom instructions extend the RISC–V ISA and
  follow their encoding. The custom instructions are of three types: to def
 ine matrix registers\, matrix operations and memory operations.\n\nThe ins
 tructions are described in Sail and are tested in the generated simulator.
  adl_tool transforms the Sail architecture description into compiler model
  artifacts needed to build a functional prototype compiler for the given s
 pecification. Additionally\, provides automatically generated tests to val
 idate the correctness of the instruction encodings. \n\nThe compiler was g
 enerated from the description model and tested with the accelerator implem
 ented in hardware. The experimental results suggest that for matrix multip
 lication we obtained speed-ups up to 1413x compared to an ARM A72 core.
DTSTAMP:20260522T162358Z
LOCATION:Devzone
SUMMARY:Accelerating Matrix Operations with a Custom RISC‑V SIMD/Vector E
 xtension and Automated LLVM Support - Catalin Ciobanu
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/UC3AZA/
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