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UID:pretalx-eu-summit-2026-DSMVHN@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T160000
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DESCRIPTION:This work presents CVA6-RT\, a real-time micro-architectural ex
 tension of the CVA6 core to bound worst-case latency and reduce task's tim
 ing execution variability. CVA6-RT implements the rv64gch ISA and features
  advanced support for real-time execution\, including TLB partitioning and
  locking for predictable address translation\, a dynamically reconfigurabl
 e scratchpad mode in the L1 caches for deterministic memory access\, and l
 ow-latency interrupt handling via an enhanced interrupt controller combine
 d with hardware-assisted context stacking. With real-time features enabled
 \, CVA6-RT achieves an interrupt latency of 12 cycles\, comparable to that
  of simpler Arm Cortex-M microcontrollers\, and 10x lower than the baselin
 e CVA6 core.
DTSTAMP:20260522T162745Z
LOCATION:Poster Island C
SUMMARY:CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-C
 riticality Systems - Enrico Zelioli
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/DSMVHN/
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