Processor designs are increasingly complex, making verification a critical challenge in the chip development process. Traditional verification techniques, heavily reliant on software simulations and random test inputs, often fail to effectively identify complex corner cases, leading to slow convergence and high verification costs. To address these challenges, we propose a heterogeneous hardware-accelerated RISC-V verification framework that integrates FPGA acceleration with a domain-specific generative model. This framework generates semantically-aware RISC-V instruction sequences and executes them in parallel with a reference model, providing real-time coverage collection and differential checking. The system improves verification efficiency by generating high-quality test inputs and reducing the time required for coverage convergence. Experimental results show that our framework outperforms existing fuzzers in terms of both coverage and speed, achieving up to 1.27× higher coverage and accelerates verification by up to 107×(Cascade) to 3343×(DifuzzRTL) compared to state-of-the-art fuzzers, with consistently lower convergence difficulty.