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UID:pretalx-eu-summit-2026-JZAHPN@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T141000
DTEND;TZID=CET:20260610T142000
DESCRIPTION:Processor designs are increasingly complex\, making verificatio
 n a critical challenge in the chip development process. Traditional verifi
 cation techniques\, heavily reliant on software simulations and random tes
 t inputs\, often fail to effectively identify complex corner cases\, leadi
 ng to slow convergence and high verification costs. To address these chall
 enges\, we propose a heterogeneous hardware-accelerated RISC-V verificatio
 n framework that integrates FPGA acceleration with a domain-specific gener
 ative model. This framework generates semantically-aware RISC-V instructio
 n sequences and executes them in parallel with a reference model\, providi
 ng real-time coverage collection and differential checking. The system imp
 roves verification efficiency by generating high-quality test inputs and r
 educing the time required for coverage convergence. Experimental results s
 how that our framework outperforms existing fuzzers in terms of both cover
 age and speed\, achieving up to 1.27× higher coverage and accelerates ver
 ification by up to 107×(Cascade) to 3343×(DifuzzRTL) compared to state-o
 f-the-art fuzzers\, with consistently lower convergence difficulty.
DTSTAMP:20260522T162345Z
LOCATION:Poster Island A
SUMMARY:A Hardware-Software Heterogeneous Framework for Agile RISC-V Verifi
 cation with Model-Based Processor Fuzzing - Juncheng Huo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/JZAHPN/
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