Assessing the vulnerability of caches against side-channel attacks is of critical importance when enhanced microarchitectural security is a primary requirement for multicore CPU implementations. Previous works have proposed various metrics and methodologies to assess such vulnerabilities. However, those works suffer from limitations regarding either the range of target cache attacks, the support for the RISC-V ISA, or the reliance on in-house simulators and tools. The goal of this paper is to provide support for systematically evaluating RISC-V multicore CPUs against a wide range of cache timing attacks. Our approach enables the assessment of both hardware implementations and simulated systems, facilitating early-stage security evaluation during the processor design phase using the open-source gem5 microarchitectural simulator. Specifically, we extend the Cache Timing Vulnerability Score (CTVS) methodology along two axes. We port CTVS to RISC-V, and then we integrate it with gem5 to support both RISC-V and x86 simulated systems. Finally, we evaluate our enhanced CTVS framework on simulated RISC-V and x86 multicore CPUs to demonstrate its effectiveness.