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UID:pretalx-eu-summit-2026-BREVML@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T154000
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DESCRIPTION:Writing verification stimulus for RISC-V processors requires de
 ep expertise across ISA specifications\, microarchitectural implementation
 \, and test framework APIs. We present an LLM-driven multi-agent framework
  that transforms a brief natural-language scenario description into a comp
 rehensive\, executable RISC-V test generator. Five specialized AI agents f
 orm a sequential enrichment\npipeline: an ISA expert expands intent into a
 rchitecturally complete scenarios\, an RTL analyst reads hardware source c
 ode to inject microarchitecture-targeted stress patterns\, a framework spe
 cialist maps steps to concrete API calls\, a builder synthesizes deployabl
 e code\, and a validator ensures correctness through static checks and ins
 truction-set-simulator execution. On the RISC-V Svadu extension\, a 3-line
  scenario yields 490 lines of validated\, simulation-passing code in under
  13 minutes—a ∼40× speedup versus an estimated∼8 hours of manual ef
 fort.
DTSTAMP:20260522T162441Z
LOCATION:Poster Island A
SUMMARY:LLM-Driven Multi-Agent Framework for Automated RISC-V Verification 
 Stimulus Generation - Kavya Sri Endukuri\, Nicholas Matus\, Radha Govindar
 adjou
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/BREVML/
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