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UID:pretalx-eu-summit-2026-BYLQDM@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T133000
DTEND;TZID=CET:20260609T134000
DESCRIPTION:The RISC-V architecture has experienced rapid growth in recent 
 years\, evolving from an academic research project into a global ecosystem
  spanning industry\, academia\, and open-source communities. However\, ach
 ieving competitive application performance across the diverse RISC-V micro
 architectures requires a mature compiler infrastructure capable of realizi
 ng the performance potential of the underlying hardware. In this work\, we
  present XSCC\, a high-performance compiler built on LLVM 19.1.0\, designe
 d to meet industrial-grade performance demands while actively contributing
  to open-source ecosystem development. XSCC performs a systematic cross-ar
 chitecture optimization analysis\, distilling compiler insights from matur
 e architectures into a cohesive set of optimizations for RISC-V\, includin
 g enhanced loop transformations\, memory access reordering\, and microarch
 itecture-specific scheduling models. Four of these optimizations have been
  upstreamed to the LLVM project. Experimental evaluation demonstrates cons
 istent improvements over baseline LLVM 19 and GCC 12\, achieving up to 1.1
 4x speedup on SPEC CPU 2006 FP on the simulated XiangShan KMHv3 and up to 
 1.30x speedup on SPEC CPU 2006 INT on commercial RISC-V hardware SpacemiT 
 X60.
DTSTAMP:20260715T065445Z
LOCATION:Poster Island C
SUMMARY:XSCC: A High-Performance Compiler for RISC-V - Lei Qiu\, Lulin Wang
 \, Kangda Hao
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/BYLQDM/
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