Microarchitectural performance evaluation is an essential step in modern processor design and architecture exploration. However, developing a cycle-accurate simulator from scratch requires implementing both instruction semantics and detailed microarchitectural models, which significantly increases development complexity.

This work presents RISCV-Perf, a lightweight performance modeling framework designed to integrate with the Spike RISC-V functional simulator. The framework decouples functional execution from cycle-level timing simulation through a minimal instruction interface that captures key instruction attributes such as program counters, operand registers, and memory access information. By reusing the functional correctness provided by Spike, RISCV-Perf focuses solely on modeling microarchitectural timing behavior.

RISCV-Perf adopts an execution-driven simulation approach, enabling cycle-level modeling of superscalar out-of-order processors without generating execution traces. The timing model represents major microarchitectural components including an instruction flow model, register renaming mechanism, memory operation pipelines, and cache hierarchy interactions. In addition, the framework is implemented using a modular policy-based design, allowing architectural components such as branch predictors and cache policies to be easily replaced or extended.

Experimental evaluation using the MiBench benchmark suite on an RV64GC configuration demonstrates that RISCV-Perf can effectively generate performance insights such as CPI behavior and branch prediction miss rates across workloads. These results show that the framework provides a practical platform for workload characterization and microarchitectural policy exploration.