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UID:pretalx-eu-summit-2026-LNBB8V@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T130000
DTEND;TZID=CET:20260610T131000
DESCRIPTION:Microarchitectural performance evaluation is an essential step 
 in modern processor design and architecture exploration. However\, develop
 ing a cycle-accurate simulator from scratch requires implementing both ins
 truction semantics and detailed microarchitectural models\, which signific
 antly increases development complexity.\n\nThis work presents RISCV-Perf\,
  a lightweight performance modeling framework designed to integrate with t
 he Spike RISC-V functional simulator. The framework decouples functional e
 xecution from cycle-level timing simulation through a minimal instruction 
 interface that captures key instruction attributes such as program counter
 s\, operand registers\, and memory access information. By reusing the func
 tional correctness provided by Spike\, RISCV-Perf focuses solely on modeli
 ng microarchitectural timing behavior.\n\nRISCV-Perf adopts an execution-d
 riven simulation approach\, enabling cycle-level modeling of superscalar o
 ut-of-order processors without generating execution traces. The timing mod
 el represents major microarchitectural components including an instruction
  flow model\, register renaming mechanism\, memory operation pipelines\, a
 nd cache hierarchy interactions. In addition\, the framework is implemente
 d using a modular policy-based design\, allowing architectural components 
 such as branch predictors and cache policies to be easily replaced or exte
 nded.\n\nExperimental evaluation using the MiBench benchmark suite on an R
 V64GC configuration demonstrates that RISCV-Perf can effectively generate 
 performance insights such as CPI behavior and branch prediction miss rates
  across workloads. These results show that the framework provides a practi
 cal platform for workload characterization and microarchitectural policy e
 xploration.
DTSTAMP:20260522T162730Z
LOCATION:Poster Island B
SUMMARY:RISCV-Perf: A Performance Modeling Framework  for RISC-V Processors
  Integrated with Spike - Tsung-LI
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/LNBB8V/
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