BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//speaker//DLHEHX
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-ZZ7ADW@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T103000
DTEND;TZID=CET:20260609T104000
DESCRIPTION:Side-channel attacks leveraging microarchitectural features are
  well-studied on x86 and ARM\, but less so on RISC-V. This work implements
  and evaluates Flush+Reload cache-side-channel attacks on user-space softw
 are in a RISC-V system simulated in gem5 full-system mode. We develop both
  eviction-based and cache-block-invalidate (cbo.inval) probes\, establishi
 ng an attack methodology for an unprivileged process using the RISC-V cycl
 e counter. Our experiments reveal timing differences between cached and ev
 icted accesses\, confirming the existence of exploitable timing channels. 
 While key recovery remains partial\, these results demonstrate the feasibi
 lity of cache side-channel attacks on RISC-V and validate gem5 as an effec
 tive platform for microarchitectural security research.
DTSTAMP:20260522T162440Z
LOCATION:Poster Island A
SUMMARY:Microarchitectural Side-Channel Attack on RISC-V - Sadia Shamas
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ZZ7ADW/
END:VEVENT
END:VCALENDAR