Modern interrupt controllers combine hardware and software mechanisms to reduce interrupt latency, optimizing either worst-case latency, average-case latency, or both. The paper provides analysis of interrupt-latency optimization techniques and their trade-offs in the context of RISC‑V interrupt architectures. It draws on an end-to-end workflow that began with functional modeling and continued through simulation, OS porting, and RTL implementation. This provides practical insight into how these techniques behave both in isolation and in real-world systems. The paper shows that each technique admits multiple realizations, which redistribute cost across latency metrics, software and hardware implementation complexity, memory footprint, and other factors, and that the techniques are interdependent, so the benefits of enabling them are not directly additive.