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UID:pretalx-eu-summit-2026-FMQNTD@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T131000
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DESCRIPTION:Modern interrupt controllers combine hardware and software mech
 anisms to reduce interrupt latency\, optimizing either worst-case latency\
 , average-case latency\, or both. The paper provides analysis of interrupt
 -latency optimization techniques and their trade-offs in the context of RI
 SC‑V interrupt architectures. It draws on an end-to-end workflow that be
 gan with functional modeling and continued through simulation\, OS porting
 \, and RTL implementation. This provides practical insight into how these 
 techniques behave both in isolation and in real-world systems. The paper s
 hows that each technique admits multiple realizations\, which redistribute
  cost across latency metrics\, software and hardware implementation comple
 xity\, memory footprint\, and other factors\, and that the techniques are 
 interdependent\, so the benefits of enabling them are not directly additiv
 e.
DTSTAMP:20260522T162846Z
LOCATION:Poster Island D
SUMMARY:Advanced Interrupt Latency Optimization Approaches in RISC‑V Inte
 rrupt Architectures - Evgenii Paltsev
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/FMQNTD/
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