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UID:pretalx-eu-summit-2026-TMWG8J@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T105000
DTEND;TZID=CET:20260609T110000
DESCRIPTION:Compilers play a central role in unlocking the full performance
  potential of rapidly evolving RISC-V processors. In the practice of optim
 izing SPEC CPU 2006 and SPEC CPU 2017 using LLVM for RISC-V\, a few compil
 er optimizations targeting RISC-V have been implemented\, involving approa
 ches that both enhance the effectiveness of individual optimization passes
  and refine how passes interact within the optimization pipeline. \nThis w
 ork introduces four such optimizations integrated into LLVM: (1) extending
  loop interchange to support loops containing reduction patterns\, (2) enh
 ancing loop strength reduction for nested loops\, (3) eliminating unnecess
 ary loop counters to unlock further optimizations such as loop unroll\, an
 d (4) refactoring multi-dimensional array accesses to enable subsequent re
 dundant computation elimination. While motivated by RISC-V performance tun
 ing\, the proposed techniques can also benefit other architectures such as
  x86. Evaluated on SPEC CPU 2006 and SPEC CPU 2017\, these improvements ac
 hieve performance gains ranging from 6\\% to 54\\% across Intel i9-11900K\
 , SpacemiT Key Stone K1\, and XiangShan KMHv3 platforms.
DTSTAMP:20260715T065913Z
LOCATION:Poster Island C
SUMMARY:Loop Optimization Practices for RISC-V - Lei Qiu\, Lulin Wang\, Yin
 gying Wang
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/TMWG8J/
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UID:pretalx-eu-summit-2026-BYLQDM@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T133000
DTEND;TZID=CET:20260609T134000
DESCRIPTION:The RISC-V architecture has experienced rapid growth in recent 
 years\, evolving from an academic research project into a global ecosystem
  spanning industry\, academia\, and open-source communities. However\, ach
 ieving competitive application performance across the diverse RISC-V micro
 architectures requires a mature compiler infrastructure capable of realizi
 ng the performance potential of the underlying hardware. In this work\, we
  present XSCC\, a high-performance compiler built on LLVM 19.1.0\, designe
 d to meet industrial-grade performance demands while actively contributing
  to open-source ecosystem development. XSCC performs a systematic cross-ar
 chitecture optimization analysis\, distilling compiler insights from matur
 e architectures into a cohesive set of optimizations for RISC-V\, includin
 g enhanced loop transformations\, memory access reordering\, and microarch
 itecture-specific scheduling models. Four of these optimizations have been
  upstreamed to the LLVM project. Experimental evaluation demonstrates cons
 istent improvements over baseline LLVM 19 and GCC 12\, achieving up to 1.1
 4x speedup on SPEC CPU 2006 FP on the simulated XiangShan KMHv3 and up to 
 1.30x speedup on SPEC CPU 2006 INT on commercial RISC-V hardware SpacemiT 
 X60.
DTSTAMP:20260715T065913Z
LOCATION:Poster Island C
SUMMARY:XSCC: A High-Performance Compiler for RISC-V - Lei Qiu\, Lulin Wang
 \, Kangda Hao
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/BYLQDM/
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