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UID:pretalx-eu-summit-2026-7AQXJK@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T112000
DTEND;TZID=CET:20260610T113000
DESCRIPTION:Functional safety (FuSa) in modern SoC designs demands rigorous
  fault detection mechanisms alongside standardized error reporting. We pre
 sent a fully automated\, generator-driven design flow that automatically a
 pplies dual modular redundancy (DMR) through a pass implemented in CIRCT\,
  an MLIR-based hardware compiler framework\, without requiring manual RTL 
 modification. To validate the correctness of the generated design\, we app
 ly formal verification\, providing strong assurance that the DMR compositi
 on itself introduces no spurious faults. In addition\, we address the syst
 em-level integration of the generated fault detection signals by routing t
 hem to a safety controller that adheres to the "RISC-V RERI Architecture S
 pecification" for error reporting across the SoC\, capturing each error's 
 severity\, nature\, and location. We validate our generation flow through 
 fault injection\, demonstrating reliable fault detection across arbitrary 
 hardware modules and correct propagation\, recording\, and reporting of de
 tected errors in the safety controller. Combined\, our contributions form 
 an automated path from module-level fault hardening to system-level error 
 observability\, advancing the practical adoption of FuSa practices in gene
 rator-based RISC-V SoCs.
DTSTAMP:20260522T162735Z
LOCATION:Poster Island D
SUMMARY:Generator-Driven Functional Safety for RISC-V SoCs with Formal Assu
 rance - Frederik Haxel
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/7AQXJK/
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