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UID:pretalx-eu-summit-2026-SCCL9S@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T135000
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DESCRIPTION:This work presents a co-simulation methodology for the evaluati
 on of pixel detector architecture\, combining two independently developed 
 tools: PixESL\, a virtual prototyping framework targeting the architectura
 l exploration and performance assessment of pixel detector systems\, and G
 VSoC\, a full-platform simulator for RISC-V IoT SoCs.  \nIn parallel with 
 PixESL's development\, studies on integrating RISC-V-based SoCs with pixel
  detector readout circuitry were carried out using GVSoC. Rather than rely
 ing on fixed ASIC readout architectures\, this approach introduces a progr
 ammable processing layer alongside the pixel readout\, enabling software-l
 evel control over data handling.  \nIn the outlined co-simulation flow\, P
 ixESL generates data for a given readout architecture and set of stimuli\,
  while GVSoC simulates the target application executing on the PULP RISC-V
  SoC platform. Additionally\, in order to accurately capture the overhead 
 of data movement within this chain\, a virtual prototype of the DMA block 
 responsible for transfers between pixel readout and SoC was developed. Tog
 ether\, these components provide a unified view of the full readout chain\
 , from initial stimulus to processed data\, opening possibilities for more
  informed hardware-software co-design in future detectors.
DTSTAMP:20260522T162445Z
LOCATION:Poster Island B
SUMMARY:Virtual Prototyping of Pixel Detector Architecture via Co-Simulatio
 n of PixESL and GVSoC - mobradovic00
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/SCCL9S/
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