Quentin MÉLOTTE
About Me
Study and work
I am currently an embedded systems engineering student at ESISAR engineering school and a work-study research engineer at the CEA in Grenoble. I work on compiler research while assisting Henri-Pierre Charles (https://blog.hpch.net/), focusing on low-level optimization and embedded computing systems.
Passion
I am passionate about embedded systems, firmware development, hardware architecture, and the interaction between software and hardware.
My Specialities
- Embedded systems engineering
- Low-level programming
- Compiler research
- Dynamic runtime compilation
- Firmware and system optimization
- Hardware/software co-design
Why RISC-V Interests Me
RISC-V interests me because of its open and flexible philosophy, enabling experimentation and innovation in embedded computing. I find it especially exciting as it allows deeper exploration of the relationship between compilers, architectures, and runtime performance.
I believe open architectures like RISC-V will play a key role in future embedded systems.
Session
RISC-V is a major breakthrough in the computing ecosystem. It open
opportunities for hardware research, innovation for
industry. Researcher or industrial can customize a CPU core for a
given specific application, thus provide industrial advantage.
It would be strange not to take advantage of this opportunity to
revisit the ecosystem of software tools.
In this article, we propose a new compiler for generating a part
of the binary code at runtime.
This has several advantages: (1) generating code by leveraging
knowledge of user data which provide speed optimization, (2)
generating code with knowledge of the accelerators available on a
given platform, and (3) taking advantage of unconventional
accelerators specific to a computing platform.
The 2 later points are specifically interesting for the RISC-V
community which already show a wide variety of platforms.