Communication baseband workloads such as covariance estimation, synchronization and reduction operations exhibit substantial data-level parallelism. The RISC-V Vector Extension (RVV) introduces vector-length agnostic (VLA) execution, enabling scalable vector implementations independent of a fixed hardware width. In this work, we explore architectural scalability trade-offs of a configurable RVV-based vector processor across VLEN, lane count, and lane width. Using representative communication kernels and synthesis with the predictive ASAP7 PDK, we analyze architectural scaling behavior and the interaction between cycle reduction and frequency degradation. While increasing VLEN reduces cycle counts, critical-path growth and bandwidth imbalance introduce a parallelism–frequency trade-off that yields kernel-dependent optimal configurations. We further demonstrate how a lightweight custom vector complex multiplication instruction improves efficiency for covariance-based workloads. The results highlight the importance of balanced compute–memory design for practical and physically realizable RVV implementations.

Hearing loss is among the most prevalent sensory impairments worldwide. Hearing aids that incorporate adaptable, personalized signal processing have the potential to improve communication outcomes and social participation for affected individuals. The development and rigorous evaluation of novel hearing-aid algorithms requires high-level programmable, low-power, and portable behind-the-ear (BTE) research platforms that enable studies in real-world environments. The RISC-V open source instruction set architecture (ISA) presents a flexible and configurable baseline for the development of signal processing architectures.
This paper presents a lightweight single instruction multiple data (SIMD) architecture featuring a complex number extension targeted at embedded applications with a specific focus on the energy efficiency by reusing existing multiplier hardware. Performance data is gathered from a reference Fast Fourier Transform (FFT) implementation, with FFT sizes taken from the field of typical hearing aid applications. Power values are obtained by synthesizing the baseline processor and the extension in a 22 nm FD-SOI technology, followed by a gate-level simulation to obtain accurate switching activity values. The implemented extension achieves a speedup of up to 26 %. A comparison of the energy values through gate-level simulation reveals that the energy consumption of the modified design decreases by 27 % on average.