BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//speaker//HKYAWD
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-XSLFRB@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T111000
DTEND;TZID=CET:20260610T112000
DESCRIPTION:The Monte Cimone project provides a RISC-V testbed for High-Per
 formacne Computing cluster. This paper presents Monte Cimone v3 (MCv3)\, t
 he third iteration of the Monte Cimone RISC-V HPC cluster\, integrating th
 e SOPHGO Sophon SG2044 processor\, an evolution of the SG2042 used in MCv2
 . We characterize MCv3 using HPL and STREAM benchmarks coupled with power 
 measurements\, and compare it against two reference platforms: the Intel X
 eon Platinum 8480+ (Sapphire Rapids) and the NVIDIA Grace CPU Superchip. O
 ur results show that the SG2044 more than doubles single-core performance 
 and improves scalability compared to SG2042. MCv3 achieves an energy effic
 iency of 3.08GFLOPs/W which improves of 10x w.r.t. MCv1 and is in the rang
 e of x86-64 and Arm servers. On pure performance when normalized on the SI
 MD/Vector length MCv3 on its peak efficiency point (16 cores) achieves 46%
  performance of Intel Sapphire Rapids server and 91% performance of NVIDIA
  Grace CPU superchip.
DTSTAMP:20260522T162434Z
LOCATION:Poster Island C
SUMMARY:Monte Cimone v3: Where RISC-V Stands in High-Performance Computing 
 - Emanuele Venieri
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/XSLFRB/
END:VEVENT
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-HKZX8R@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T135000
DTEND;TZID=CET:20260610T140000
DESCRIPTION:Modern processors delegate power and thermal management to dedi
 cated Power Control Systems (PCS)\, communicating through kernel-mediated 
 interfaces such as SCMI or the emerging RPMI. \nPrior work has shown that 
 end-to-end control quality is dominated by the power-management policy rat
 her than by interface latency\, leaving room to choose communication parad
 igms based on flexibility rather than raw latency. \nWe integrate Micro XR
 CE-DDS on ControlPULP\, a RISC-V–based PCS\, connecting it to a user-spa
 ce Agent on an ARM host via a custom shared-memory transport. \nThis desig
 n removes protocol logic from kernel drivers and naturally supports multi-
 controller coordination through a shared middleware layer. Experiments on 
 a ZCU102 FPGA at 20 MHz show 490 μs of active processing per publication\
 , 0.8 MB/s throughput\, and a memory footprint under 11.2 KB for 32 topics
 . The resulting latency is comparable to SCMI [1] while enabling a more fl
 exible communication model.
DTSTAMP:20260522T162434Z
LOCATION:Poster Island D
SUMMARY:Towards Open User-Space Power-Management Communication Interfaces -
  Antonio del Vecchio\, Emanuele Venieri
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/HKZX8R/
END:VEVENT
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-FP7AUZ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T111000
DTEND;TZID=CET:20260611T112000
DESCRIPTION:Matrix workloads\, essential in generative AI\, increasingly re
 ly on ISA-level (i.e. AMX\, SME). The attached matrix extension (AME) is o
 ne of the three (IME\, AME\, VME) ISA extensions  under standardization in
  RISC-V. In common\, all these matrix-ISA assumes extensions of the proces
 sor datapath with dedicated matrix acceleration hardware. However\, execut
 ing matrix kernels requires moving large tiles between memory and processo
 r registers\, making performance limited by memory bandwidth.\nWe investig
 ate whether High Bandwidth Memory with Processing-in-Memory (HBM--PIM) can
  serve as alternative implementation of AME instructions. We propose a PIM
  Execution Primitive (PEP) computational model mapping AME ISA onto Samsun
 g Aquabolt-XL HBM-PIM microkernels\, using an outer-product dataflow to en
 able in-memory accumulation\, as well as remapping AME tile registers into
  memory regions—making possible to chain AME instructions without leavin
 g the memory.\nOur experiments show AME tile multiplication reaching 14.9 
 GFLOP/s (59.4 FLOP/cycle) on a HBM--PIM pseudo-channel\, demonstrating tha
 t HBM--PIM can serve as an implementation of RISC-V matrix extensions.
DTSTAMP:20260522T162434Z
LOCATION:Poster Island B
SUMMARY:AME-PIM: Breaking the Memory Wall with RISC-V Matrix Extensions and
  HBM-PIM - Emanuele Venieri
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/FP7AUZ/
END:VEVENT
END:VCALENDAR