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UID:pretalx-eu-summit-2026-7TD7TB@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T112000
DTEND;TZID=CET:20260611T113000
DESCRIPTION:This work details a high-performance Vector Processing Unit (VP
 U) architecture designed to exploit data-Level Parallelism (DLP) within th
 e strict power and area constraints of embedded environments. Addressing t
 he parallelization needs of data-intensive tasks\, the proposed modular ar
 chitecture implements a subset of the RISC-V Vector (RVV) Zve32x sub-exten
 sion\, focusing on essential 32-bit integer operations. The VPU is integra
 ted as a co-processor to a CV32E20 core within the eXtendable Heterogeneou
 s Energy-efficient Platform (X-HEEP) ecosystem. It leverages the Core-V eX
 tension Interface (CV-X-IF) 1.0 for low-latency instruction offloading and
  the Open Bus Interface (OBI) v1.0 protocol to ensure high-throughput data
  memory access during load/store operations. The implementation\, featurin
 g a Vector Register Length (VLEN) of 128 bits\, was validated through Regi
 ster Transfer Level (RTL) simulation and in hardware using a Xilinx Pynq-Z
 2 FPGA. Performance was evaluated using standard data-parallel kernels inc
 luding SAXPY\, Indexed Arithmetic\, and Matrix Multiplication (Matmul). Ad
 ditionally\, this research investigates the RISC-V GNU Compiler Toolchain\
 , comparing standard C auto-vectorization against manual vectorization usi
 ng RISC-V Vector C Intrinsics.
DTSTAMP:20260522T162740Z
LOCATION:Poster Island A
SUMMARY:An Embedded RISC-V Vector Extension for Edge-Oriented Acceleration 
 - Iñigo Diez de Ulzurrun
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/7TD7TB/
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