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UID:pretalx-eu-summit-2026-3XNCRH@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T130000
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DESCRIPTION:Non-compliant RISC-V extensions remain a practical obstacle for
  custom and legacy CPU designs. We present a two-phase workflow that uses 
 the RISC-V Unified Database (UDB) as the source of truth for extension def
 inition and a Large Language Model (LLM) connected through Model Context P
 rotocol (MCP) tools to accelerate migration into compliant custom opcode s
 pace. In Phase 1\, the agent inspects instruction encodings\, identifies c
 onflicts against ratified and reserved space\, and proposes remappings for
  human approval. In Phase 2\, it generates hardware and software artifacts
  from the approved mapping and validates them through automated build-and-
 test loops. To evaluate the flow\, we are open-sourcing two packed-SIMD ex
 tensions and the supporting hardware and software\, including a full-syste
 m simulator\, GNU assembler support\, Zephyr runtime support and even the 
 RTL design for the more than 140 migrated instructions. The result is a wo
 rking open-source end-to-end stack\, from decoder to application code\, de
 monstrating AI assistance as a practical aid for ISA architects and as an 
 automation layer for the associated hardware and software engineering.
DTSTAMP:20260522T162353Z
LOCATION:Poster Island C
SUMMARY:Conflict to Compliance: RISC-V Extension Migration Across Spec\, HW
 \, and SW - Afonso Oliveira
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/3XNCRH/
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