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UID:pretalx-eu-summit-2026-8QKTQW@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T110000
DTEND;TZID=CET:20260609T111000
DESCRIPTION:Sparse matrix–dense matrix multiplication (SpMM) is a fundame
 ntal workload in high-performance computing and emerging edge workloads\, 
 yet its performance is typically memory-bound due to irregular and indirec
 t memory accesses. While the RISC-V Vector Extension (RVV) provides flexib
 le data-parallel execution\, efficiently exploiting it for sparse workload
 s remains challenging.\n\nThis work evaluates an iterative SpMM kernel on 
 an RVV-enabled RISC-V processor (Spacemit X60\, 8 cores) and investigates 
 the combined impact of locality-aware data layout and explicit vectorizati
 on. We compare scalar\, compiler-vectorized\, library-based\, and manual i
 ntrinsic implementations. Additionally\, we apply Morton (Z-order) reorder
 ing to improve spatial locality in memory.\n\nExperimental results show th
 at vectorization alone provides limited benefits in memory-bound regimes. 
 However\, when combined with Morton reordering\, manual RVV vectorization 
 achieves the best performance. Microarchitectural analysis confirms reduce
 d cache misses and improved IPC\, although the workload remains fundamenta
 lly bandwidth-limited.\n\nThe study highlights the importance of data layo
 ut co-design when targeting sparse workloads on emerging RISC-V platforms.
DTSTAMP:20260522T162433Z
LOCATION:Poster Island C
SUMMARY:Locality-Aware Sparse Matrix Multiplication on RISC-V RVV - Andrea 
 Herrerías León
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/8QKTQW/
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