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UID:pretalx-eu-summit-2026-3TQ3K9@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T110000
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DESCRIPTION:Embedded applications increasingly rely on highly efficient\, l
 ow-area RISC-V processors. However\, short 3-stage pipelines often suffer 
 from data and control hazards that degrade performance by introducing freq
 uent stalls. This paper presents the implementation of Fine-Grained Multit
 hreading (FGMT) on [OMITTED FOR BLIND REVIEW]\, an industrial 32-bit RISC-
 V core supporting the RV32ECM instruction set. By interleaving two hardwar
 e threads\, the design effectively hides pipeline stalls and simplifies br
 anch target calculation without requiring complex branch prediction. To fu
 rther mitigate structural hazards and the underutilization caused by inact
 ive thread contexts in fixed round-robin scheduling\, we introduce a novel
  "Thread Forwarding" (TF) technique which enables a form of TLP (Thread-Le
 vel Parallelism). Implemented in 40nm (C40) technology with a target frequ
 ency of 300MHz\, the standard FGMT achieves a 14\\% IPC improvement over t
 he baseline at the cost of a 9\\% area overhead within an MCU SoC featurin
 g 16 KBytes of instruction and data memory. The TF architecture achieves a
  Pareto optimal configuration\, further boosting IPC to 0.958 (+18.8\\% ov
 er baseline) while maintaining the same area footprint as the standard FGM
 T implementation.
DTSTAMP:20260522T162454Z
LOCATION:Poster Island D
SUMMARY:Maximizing Performance at Low Area Cost in RISC-V Processors Levera
 ging Fine-Grained Multithreading - Arbi
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/3TQ3K9/
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