The complexity of modern electronic systems has increased significantly over the past decades due to continuous technological advances. To cope with this growing complexity, data structures, algorithms, and the underlying hardware platforms used in Electronic Design Automation (EDA) must be continuously improved. Decision Diagrams (DDs) constitute a fundamental graph-based structure for formal verification, enabling efficient representation and algorithmic manipulation of switching functions. Owing to their practical relevance, numerous optimizations have been incorporated into existing DD software packages. However, these optimizations are typically designed in an architecture-agnostic manner and do not explicitly exploit characteristics of a specific target platform. As a consequence, architecture-specific optimization opportunities may remain untapped. In this work, a transaction-level analysis of a representative DD package is conducted using a RISC-V-based trace analysis tool to investigate this potential. The study reveals recurring instruction sequences with strong potential for hardware-level aggregation, enabling more efficient hardware designs. Furthermore, the derived insights provide guidance for higher-level software optimizations.