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UID:pretalx-eu-summit-2026-RRK9ZJ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T155000
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DESCRIPTION:The Cincoranch Test Chip 1 (TC1)\, manufactured in Intel3 techn
 ology\, integrates three RISC-V processors\nwith a Vector Processing Unit 
 (VPU) accelerator and an HPC-oriented cache hierarchy. This work presents 
 the\nelectrical characterization of the silicon\, the power-on bring-up pr
 ocedure\, and basic functionality verification\nof the TC1 chips. Initial 
 measurements focused on power consumption and temperature of each core und
 er idle\nconditions\, providing insight into the chip’s behavior and rea
 diness for further workload testing.
DTSTAMP:20260522T162432Z
LOCATION:Poster Island C
SUMMARY:Cincoranch: A Heterogeneous Multi-Microarchitecture RISC-V Test Chi
 p – Silicon Bring-Up - Hugo Safadi
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/RRK9ZJ/
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