New RISC-V CPU cores are released every year, and while these cores typically conform to standardized RISC-V ISA profiles, vendors frequently introduce additional proprietary extensions. This growing diversity makes it difficult for developers to accurately determine the exact instruction sets supported by a specific CPU core, thereby complicating the selection of appropriate toolchains, firmware, and operating system images. The RuyiSDK Package Manager addresses this challenge by aggregating information on RISC-V CPUs, MCUs, and development boards together with their corresponding toolchains, firmware, and system images. It establishes a comprehensive mapping between CPU architectures, development boards, and required software resources. This mapping is maintained in a structured packages index, which provides a unified, metadata-driven representation of RISC-V hardware and software resources, along with associated download links. This paper presents the overall architecture and design of the RuyiSDK Package Manager, focusing on three core components: package management, virtual environment isolation, and device provisioning. The system currently supports most commercially available RISC-V development boards. Beyond toolchain integration, it lays the foundation for IDE integration and other developer utilities. By streamlining access to software resources and standardizing development workflows, the system lowers the barrier to entry for RISC-V software development, facilitates developer onboarding, and improves visibility into software support across heterogeneous RISC-V platforms.

This paper presents Sail-RISCV-WASM, which addresses three common limitations of existing browser-based RISC-V tools: fragmented capabilities, limited configurability, and disconnected build/debug pipelines. The system uses sail-riscv as its semantic baseline and compiles it to WebAssembly, forming a three-layer architecture in a pure browser environment: a Sail decode/execute layer, a toolchain layer (gas/ld/objdump), and a metadata layer based on the RISC-V UDB. Based on this architecture, the paper defines two core workflows. The first is configuration-sensitive online encode/decode with instruction metadata navigation for cross-configuration behavior comparison. The second is an in-browser assemble-to-ELF, execute, and interactive debugging loop, supporting instruction-level stepping, source-line stepping, synchronized source/disassembly views, and register/memory tracing. Results show that the system provides a complete single-page flow from exploration to build to diagnosis, with strong extension coverage and configuration flexibility.

The Sail RISC-V Model can generate an executable file from its formal specification,. Currrently RISC-V tests only provides limited test cases and cannot comprehensively test your RISC-V implementation. Some chips may use self-developed simulators for testing, but they cannot obtain formal verification-based guarantees like RISC-V Sail Model, nor can they offer full configurability. This work introduces a new test framework that uses the RISC-V Sail Model as the ref model, ensuring the model's completeness and accuracy. To improve simulation performance, we choose to use Pydrofoil, which is an improved version of the Sail Model that delivers ultra-high performance. To enhance test compatibility and usability, we provide a set of simple test interfaces (including register access, memory access, etc.) and support customizing model configurations. Currently, it has successfully integrated tests for some open-source RISC-V implementations.

The development of RISC-V technology faces challenges such as the existence of low-quality online courses, fragmented content, a lack of hierarchical and systematic course series, insufficient online experimental practice environments, and limited channels for learning Q&A. The paper sets out to develop a standardized model for assessing the quality of RISC-V courses. In addition, it puts forward a reconstruction method based on course classification tags, organized the individual video into a structured course series. The solution integrates a online RISC-V lab with offline community activities, thereby establishing an integrated online-offline practical teaching environment. This project has produced over 1,000 original RISC-V lecture videos, with total views exceeding 1.3 million. The experimental results demonstrate that the systematically organized course collections generated by this method significantly improve viewership and user engagement, providing a systematic solution for the development of the RISC-V education ecosystem.