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UID:pretalx-eu-summit-2026-TYLEYW@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T142000
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DESCRIPTION:This paper presents a radiation-hardened\, open-source RISC-V C
 VA6 core designed for space\, aeronautics\, and automotive applications\, 
 where Single Event Upsets (SEUs) threaten reliability or safety. The desig
 n integrates error detection and recovery in L1 caches and Dual-Core Locks
 tep (DCLS) with temporal diversity. For non-critical workloads\, the syste
 m supports Asymmetric Multiprocessing (AMP)\, enabling independent core op
 eration. Tested with Linux and Zephyr\, this work is inspired by RISC-V In
 ternational’s Functional Safety white paper and advances open-source\, f
 ault-tolerant computing for critical systems. It is being integrated in a 
 new 18 nm SoC for AI.
DTSTAMP:20260522T162432Z
LOCATION:Poster Island C
SUMMARY:Fault-Tolerant Open-Source CVA6 Core for Automotive\, Aeronautics a
 nd Space - Jérôme Quévremont
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/TYLEYW/
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