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UID:pretalx-eu-summit-2026-8MCLHT@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T111000
DTEND;TZID=CET:20260610T112000
DESCRIPTION:Processor implementations designed to occupy minimal areas\, su
 ch as SERV or FazyRV\, are becoming increasingly popular. Some of these de
 signs focus on flexibility and configurability while maintaining their com
 pact design. However\, due to their minimal area\, implementations often i
 nvolve compromises in specific components to achieve this level of efficie
 ncy. The FazyRV decoder\, e.g.\, is highly optimized for area and therefor
 e omits certain checks for illegal instructions. \nTo address these drawba
 cks\, we propose a concept that uses partial runtime reconfiguration to dy
 namically replace the decoder's logic with a more robust variant to enable
  stricter instruction checking. These modifications introduce an area over
 head of up to 39% more flip-flops than the original implementation. Dynami
 c partial reconfiguration can be triggered during runtime via a memory-map
 ped register\, enabling the processor to continue normal operation seamles
 sly.
DTSTAMP:20260522T162438Z
LOCATION:Poster Island D
SUMMARY:Runtime Reconfiguration of Decoders in Minimal-area RISC-V Cores - 
 Tobias Scheipel\, Lukas Glantschnig
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/8MCLHT/
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